505 lines
20 KiB
ArmAsm
505 lines
20 KiB
ArmAsm
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/*********************************************************************************************************************
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* @file startup_XMC1200.S
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* @brief CMSIS Core Device Startup File for Infineon XMC1200 Device Series
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* @version V1.15
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* @date 05 Jan 2016
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2012-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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**************************** Change history ********************************
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* V1.0, Oct, 02, 2012 PKB:Startup file for XMC1
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* V1.1, Oct, 19, 2012 PKB:ERU and MATH interrupt handlers
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* V1.2, Nov, 02, 2012 PKB:Renamed AllowPLLInitByStartup to AllowClkInitByStartup
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* V1.3, Dec, 11, 2012 PKB:Attributes of .XmcVeneerCode section changed
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* V1.4, Dec, 13, 2012 PKB:Removed unwanted interrupts/veneers
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* V1.5, Jan, 26, 2013 PKB:Corrected the SSW related entries
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* V1.6, Feb, 13, 2013 PKB:Relative path to Device_Data.h
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* V1.7, Feb, 19, 2013 PKB:Included XMC1100_SCU.inc
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* V1.8, Jan, 24, 2014 PKB:Removed AllowClkInitStartup and DAVE Extended init
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* V1.9, Feb, 05, 2014 PKB:Removed redundant alignment code from copy+clear funcs
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* V1.10, Feb, 14, 2014 PKB:Added software_init_hook and hardware_init_hook
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* V1.11, May, 06, 2014 JFT:__COPY_FLASH2RAM to initialize ram
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* Added ram_code section initialization
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* V1.12, Sep, 29, 2014 JFT:One single default handler
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* Device_Data.h not included, user may use CLKVAL1_SSW
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* and CLKVAL2_SSW.
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* software_init_hook and hardware_init_hook removed
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* Misc optimizations
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* V1.13, Dec, 11,2014 JFT:Default clocking changed, MCLK=32MHz and PCLK=64MHz
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* V1.14, Sep, 03,2015 JFT:SSW default clocking changed, MCLK=8MHz and PCLK=16MHz avoid problems with BMI tool timeout
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* V1.15, Jan, 05,2016 JFT:Fix .reset section attributes
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*
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* @endcond
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*/
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/*****************************************************************************
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* <h> Clock system handling by SSW
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* <h> CLK_VAL1 Configuration
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* <o0.0..7> FDIV Fractional Divider Selection
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* <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (2 x (IDIV + (FDIV / 256)))
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* <o0.8..15> IDIV Divider Selection (limited to 1-16)
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* <0=> Divider is bypassed
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* <1=> MCLK = 32 MHz
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* <2=> MCLK = 16 MHz
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* <3=> MCLK = 10.67 MHz
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* <4=> MCLK = 8 MHz
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* <254=> MCLK = 126 kHz
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* <255=> MCLK = 125.5 kHz
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* <i> Deafult: 4. Interger part of clock divider, MCLK = DCO1 / (2 x (IDIV + (FDIV / 256))) = 8MHz
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* <o0.16> PCLKSEL PCLK Clock Select
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* <0=> PCLK = MCLK
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* <1=> PCLK = 2 x MCLK
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* <i> Deafult: 2 x MCLK
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* <o0.17..19> RTCCLKSEL RTC Clock Select
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* <0=> 32.768kHz standby clock
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* <1=> 32.768kHz external clock from ERU0.IOUT0
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* <2=> 32.768kHz external clock from ACMP0.OUT
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* <3=> 32.768kHz external clock from ACMP1.OUT
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* <4=> 32.768kHz external clock from ACMP2.OUT
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* <5=> Reserved
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* <6=> Reserved
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* <7=> Reserved
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* <i> Deafult: 32.768kHz standby clock
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* <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
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* </h>
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*****************************************************************************/
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#define CLKVAL1_SSW 0x00010400
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/*****************************************************************************
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* <h> CLK_VAL2 Configuration
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* <o0.0> disable VADC and SHS Gating
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* <o0.1> disable CCU80 Gating
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* <o0.2> disable CCU40 Gating
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* <o0.3> disable USIC0 Gating
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* <o0.4> disable BCCU0 Gating
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* <o0.5> disable LEDTS0 Gating
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* <o0.6> disable LEDTS1 Gating
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* <o0.7> disable POSIF0 Gating
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* <o0.8> disable MATH Gating
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* <o0.9> disable WDT Gating
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* <o0.10> disable RTC Gating
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* <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
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* </h>
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*****************************************************************************/
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#define CLKVAL2_SSW 0x80000000
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/* A macro to define vector table entries */
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.macro Entry Handler
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.long \Handler
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.endm
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/* A couple of macros to ease definition of the various handlers */
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.macro Insert_ExceptionHandler Handler_Func
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.weak \Handler_Func
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.thumb_set \Handler_Func, Default_handler
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.endm
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/* ================== START OF VECTOR TABLE DEFINITION ====================== */
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/* Vector Table - This is indirectly branched to through the veneers */
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.syntax unified
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.cpu cortex-m0
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.section .reset, "a", %progbits
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.align 2
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.globl __Vectors
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.type __Vectors, %object
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__Vectors:
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.long __initial_sp /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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/*
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* All entries below are redundant for M0, but are retained because they can
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* in the future be directly ported to M0 Plus devices.
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*/
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.long 0 /* Reserved */
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Entry HardFault_Handler /* Hard Fault Handler */
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.long CLKVAL1_SSW /* Reserved */
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.long CLKVAL2_SSW /* Reserved */
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#ifdef RETAIN_VECTOR_TABLE
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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Entry SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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Entry PendSV_Handler /* PendSV Handler */
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Entry SysTick_Handler /* SysTick Handler */
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/* Interrupt Handlers for Service Requests (SR) from XMC1200 Peripherals */
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Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
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Entry SCU_1_IRQHandler /* Handler name for SR SCU_1 */
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Entry SCU_2_IRQHandler /* Handler name for SR SCU_2 */
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Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
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Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
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Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
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Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
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Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
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Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
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Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
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Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
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Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
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Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
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Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
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Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
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Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
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Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
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Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
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Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
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Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
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Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
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Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
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Entry LEDTS1_0_IRQHandler /* Handler name for SR LEDTS1_0 */
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Entry BCCU0_0_IRQHandler /* Handler name for SR BCCU0_0 */
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#endif
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.size __Vectors, . - __Vectors
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/* ================== END OF VECTOR TABLE DEFINITION ======================= */
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/* ================== START OF VECTOR ROUTINES ============================= */
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.thumb
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.align 1
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/* Reset Handler */
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.thumb_func
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Initialize interrupt veneer */
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ldr r1, =eROData
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ldr r2, =VeneerStart
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ldr r3, =VeneerEnd
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bl __copy_data
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ldr r0, =SystemInit
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blx r0
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/* Initialize data */
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ldr r1, =DataLoadAddr
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ldr r2, =__data_start
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ldr r3, =__data_end
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bl __copy_data
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/* RAM code */
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ldr r1, =__ram_code_load
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ldr r2, =__ram_code_start
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ldr r3, =__ram_code_end
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bl __copy_data
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/* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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#ifndef __SKIP_BSS_CLEAR
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __SKIP_BSS_CLEAR */
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#ifndef __SKIP_LIBC_INIT_ARRAY
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ldr r0, =__libc_init_array
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blx r0
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#endif
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ldr r0, =main
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blx r0
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.thumb_func
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.type __copy_data, %function
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__copy_data:
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/* The ranges of copy from/to are specified by following symbols
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* r1: start of the section to copy from.
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* r2: start of the section to copy to
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* r3: end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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* Uses r0
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*/
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subs r3, r2
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ble .L_loop_done
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.L_loop:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop
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.L_loop_done:
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bx lr
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.pool
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.size Reset_Handler,.-Reset_Handler
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/* ======================================================================== */
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/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
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.align 1
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.thumb_func
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.weak Default_handler
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.type Default_handler, %function
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Default_handler:
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b .
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.size Default_handler, . - Default_handler
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Insert_ExceptionHandler HardFault_Handler
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Insert_ExceptionHandler SVC_Handler
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Insert_ExceptionHandler PendSV_Handler
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Insert_ExceptionHandler SysTick_Handler
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Insert_ExceptionHandler SCU_0_IRQHandler
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Insert_ExceptionHandler SCU_1_IRQHandler
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Insert_ExceptionHandler SCU_2_IRQHandler
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Insert_ExceptionHandler ERU0_0_IRQHandler
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Insert_ExceptionHandler ERU0_1_IRQHandler
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Insert_ExceptionHandler ERU0_2_IRQHandler
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Insert_ExceptionHandler ERU0_3_IRQHandler
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Insert_ExceptionHandler VADC0_C0_0_IRQHandler
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Insert_ExceptionHandler VADC0_C0_1_IRQHandler
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Insert_ExceptionHandler VADC0_G0_0_IRQHandler
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Insert_ExceptionHandler VADC0_G0_1_IRQHandler
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Insert_ExceptionHandler VADC0_G1_0_IRQHandler
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Insert_ExceptionHandler VADC0_G1_1_IRQHandler
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Insert_ExceptionHandler CCU40_0_IRQHandler
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Insert_ExceptionHandler CCU40_1_IRQHandler
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Insert_ExceptionHandler CCU40_2_IRQHandler
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Insert_ExceptionHandler CCU40_3_IRQHandler
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Insert_ExceptionHandler USIC0_0_IRQHandler
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Insert_ExceptionHandler USIC0_1_IRQHandler
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Insert_ExceptionHandler USIC0_2_IRQHandler
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Insert_ExceptionHandler USIC0_3_IRQHandler
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Insert_ExceptionHandler USIC0_4_IRQHandler
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Insert_ExceptionHandler USIC0_5_IRQHandler
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Insert_ExceptionHandler LEDTS0_0_IRQHandler
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Insert_ExceptionHandler LEDTS1_0_IRQHandler
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Insert_ExceptionHandler BCCU0_0_IRQHandler
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/* ======================================================================== */
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/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
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.section ".XmcVeneerCode","ax",%progbits
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.align 1
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.globl HardFault_Veneer
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HardFault_Veneer:
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LDR R0, =HardFault_Handler
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MOV PC,R0
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.long 0
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.long 0
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.long 0
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|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SVC_Veneer
|
||
|
|
SVC_Veneer:
|
||
|
|
LDR R0, =SVC_Handler
|
||
|
|
MOV PC,R0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl PendSV_Veneer
|
||
|
|
PendSV_Veneer:
|
||
|
|
LDR R0, =PendSV_Handler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SysTick_Veneer
|
||
|
|
SysTick_Veneer:
|
||
|
|
LDR R0, =SysTick_Handler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_0_Veneer
|
||
|
|
SCU_0_Veneer:
|
||
|
|
LDR R0, =SCU_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_1_Veneer
|
||
|
|
SCU_1_Veneer:
|
||
|
|
LDR R0, =SCU_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_2_Veneer
|
||
|
|
SCU_2_Veneer:
|
||
|
|
LDR R0, =SCU_2_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_3_Veneer
|
||
|
|
SCU_3_Veneer:
|
||
|
|
LDR R0, =ERU0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_4_Veneer
|
||
|
|
SCU_4_Veneer:
|
||
|
|
LDR R0, =ERU0_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_5_Veneer
|
||
|
|
SCU_5_Veneer:
|
||
|
|
LDR R0, =ERU0_2_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl SCU_6_Veneer
|
||
|
|
SCU_6_Veneer:
|
||
|
|
LDR R0, =ERU0_3_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_0_Veneer
|
||
|
|
USIC0_0_Veneer:
|
||
|
|
LDR R0, =USIC0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_1_Veneer
|
||
|
|
USIC0_1_Veneer:
|
||
|
|
LDR R0, =USIC0_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_2_Veneer
|
||
|
|
USIC0_2_Veneer:
|
||
|
|
LDR R0, =USIC0_2_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_3_Veneer
|
||
|
|
USIC0_3_Veneer:
|
||
|
|
LDR R0, =USIC0_3_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_4_Veneer
|
||
|
|
USIC0_4_Veneer:
|
||
|
|
LDR R0, =USIC0_4_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl USIC0_5_Veneer
|
||
|
|
USIC0_5_Veneer:
|
||
|
|
LDR R0, =USIC0_5_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_C0_0_Veneer
|
||
|
|
VADC0_C0_0_Veneer:
|
||
|
|
LDR R0, =VADC0_C0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_C0_1_Veneer
|
||
|
|
VADC0_C0_1_Veneer:
|
||
|
|
LDR R0, =VADC0_C0_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_G0_0_Veneer
|
||
|
|
VADC0_G0_0_Veneer:
|
||
|
|
LDR R0, =VADC0_G0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_G0_1_Veneer
|
||
|
|
VADC0_G0_1_Veneer:
|
||
|
|
LDR R0, =VADC0_G0_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_G1_0_Veneer
|
||
|
|
VADC0_G1_0_Veneer:
|
||
|
|
LDR R0, =VADC0_G1_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl VADC0_G1_1_Veneer
|
||
|
|
VADC0_G1_1_Veneer:
|
||
|
|
LDR R0, =VADC0_G1_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl CCU40_0_Veneer
|
||
|
|
CCU40_0_Veneer:
|
||
|
|
LDR R0, =CCU40_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl CCU40_1_Veneer
|
||
|
|
CCU40_1_Veneer:
|
||
|
|
LDR R0, =CCU40_1_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl CCU40_2_Veneer
|
||
|
|
CCU40_2_Veneer:
|
||
|
|
LDR R0, =CCU40_2_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl CCU40_3_Veneer
|
||
|
|
CCU40_3_Veneer:
|
||
|
|
LDR R0, =CCU40_3_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
.long 0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl LEDTS0_0_Veneer
|
||
|
|
LEDTS0_0_Veneer:
|
||
|
|
LDR R0, =LEDTS0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl LEDTS1_0_Veneer
|
||
|
|
LEDTS1_0_Veneer:
|
||
|
|
LDR R0, =LEDTS1_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
/* ======================================================================== */
|
||
|
|
.globl BCCU0_0_Veneer
|
||
|
|
BCCU0_0_Veneer:
|
||
|
|
LDR R0, =BCCU0_0_IRQHandler
|
||
|
|
MOV PC,R0
|
||
|
|
|
||
|
|
/* ======================================================================== */
|
||
|
|
/* ======================================================================== */
|
||
|
|
|
||
|
|
/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */
|
||
|
|
|
||
|
|
.end
|