339 lines
15 KiB
ArmAsm
339 lines
15 KiB
ArmAsm
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;*********************************************************************************************************************
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;* @file startup_XMC1200.s
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;* @brief CMSIS Core Device Startup File for Infineon XMC1200 Device Series
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;* @version V1.4
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;* @date 03 Sep 2015
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;*
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;* @cond
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;*********************************************************************************************************************
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;* Copyright (c) 2013-2016, Infineon Technologies AG
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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;* following conditions are met:
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;*
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;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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;* disclaimer.
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;*
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;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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;* disclaimer in the documentation and/or other materials provided with the distribution.
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;*
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;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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;* products derived from this software without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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;* Infineon Technologies AG dave@infineon.com).
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;*********************************************************************************************************************
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;*
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;**************************** Change history ********************************
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;* V1.0, Jan, 21, 2013 TYS:Startup file for XMC1
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;* V1.1, Jul, 17, 2013 TYS:remove redundant vector table
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;* V1.2, Nov, 25, 2014 JFT:Removed DAVE3 dependency.
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;* Default handler used for all IRQs
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;* V1.3, Dec, 11, 2014 JFT:Default clocking changed, MCLK=32MHz and PCLK=64MHz
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;* V1.4, Sep, 03, 2015 JFT:SSW default clocking changed, MCLK=8MHz and PCLK=16MHz avoid problems with BMI tool timeout
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;*
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;* @endcond
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;*
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; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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; <h> Clock system handling by SSW
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; <h> CLK_VAL1 Configuration
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; <o0.0..7> FDIV Fractional Divider Selection
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; <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (2 x (IDIV + (FDIV / 256)))
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; <o0.8..15> IDIV Divider Selection (limited to 1-16)
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; <0=> Divider is bypassed
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; <1=> MCLK = 32 MHz
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; <2=> MCLK = 16 MHz
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; <3=> MCLK = 10.67 MHz
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; <4=> MCLK = 8 MHz
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; <254=> MCLK = 126 kHz
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; <255=> MCLK = 125.5 kHz
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; <i> Deafult: 4. Interger part of clock divider, MCLK = DCO1 / (2 x (IDIV + (FDIV / 256))) = 8MHz
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; <o0.16> PCLKSEL PCLK Clock Select
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; <0=> PCLK = MCLK
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; <1=> PCLK = 2 x MCLK
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; <i> Deafult: 2 x MCLK
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; <o0.17..19> RTCCLKSEL RTC Clock Select
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; <0=> 32.768kHz standby clock
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; <1=> 32.768kHz external clock from ERU0.IOUT0
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; <2=> 32.768kHz external clock from ACMP0.OUT
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; <3=> 32.768kHz external clock from ACMP1.OUT
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; <4=> 32.768kHz external clock from ACMP2.OUT
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; <5=> Reserved
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; <6=> Reserved
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; <7=> Reserved
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; <i> Deafult: 32.768kHz standby clock
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; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
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; </h>
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CLK_VAL1_Val EQU 0x00010400
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; <h> CLK_VAL2 Configuration
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; <o0.0> disable VADC and SHS Gating
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; <o0.1> disable CCU80 Gating
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; <o0.2> disable CCU40 Gating
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; <o0.3> disable USIC0 Gating
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; <o0.4> disable BCCU0 Gating
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; <o0.5> disable LEDTS0 Gating
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; <o0.6> disable LEDTS1 Gating
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; <o0.7> disable POSIF0 Gating
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; <o0.8> disable MATH Gating
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; <o0.9> disable WDT Gating
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; <o0.10> disable RTC Gating
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; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
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; </h>
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; *****************************************************************************/
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CLK_VAL2_Val EQU 0x80000000
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; </h>
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD CLK_VAL1_Val ; CLK_VAL1
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DCD CLK_VAL2_Val ; CLK_VAL2
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"
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; The real veneers will be copied later from the scatter loader before reaching main.
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; This init code should handle an exception before the real veneers are copied.
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SRAM_BASE EQU 0x20000000
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VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .
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LDR R1, =SRAM_BASE
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LDR R2, =VENEER_INIT_CODE
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MOVS R0, #48 ; Veneer 0..47
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Init_Veneers
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STR R2, [R1]
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ADDS R1, #4
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SUBS R0, R0, #1
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BNE Init_Veneers
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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Default_Handler PROC
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EXPORT HardFault_Handler [WEAK]
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EXPORT SVC_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT SCU_0_IRQHandler [WEAK]
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EXPORT SCU_1_IRQHandler [WEAK]
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EXPORT SCU_2_IRQHandler [WEAK]
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EXPORT ERU0_0_IRQHandler [WEAK]
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EXPORT ERU0_1_IRQHandler [WEAK]
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EXPORT ERU0_2_IRQHandler [WEAK]
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EXPORT ERU0_3_IRQHandler [WEAK]
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EXPORT USIC0_0_IRQHandler [WEAK]
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EXPORT USIC0_1_IRQHandler [WEAK]
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EXPORT USIC0_2_IRQHandler [WEAK]
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EXPORT USIC0_3_IRQHandler [WEAK]
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EXPORT USIC0_4_IRQHandler [WEAK]
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EXPORT USIC0_5_IRQHandler [WEAK]
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EXPORT VADC0_C0_0_IRQHandler [WEAK]
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EXPORT VADC0_C0_1_IRQHandler [WEAK]
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EXPORT VADC0_G0_0_IRQHandler [WEAK]
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EXPORT VADC0_G0_1_IRQHandler [WEAK]
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EXPORT VADC0_G1_0_IRQHandler [WEAK]
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EXPORT VADC0_G1_1_IRQHandler [WEAK]
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EXPORT CCU40_0_IRQHandler [WEAK]
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EXPORT CCU40_1_IRQHandler [WEAK]
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EXPORT CCU40_2_IRQHandler [WEAK]
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EXPORT CCU40_3_IRQHandler [WEAK]
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EXPORT LEDTS0_0_IRQHandler [WEAK]
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EXPORT LEDTS1_0_IRQHandler [WEAK]
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EXPORT BCCU0_0_IRQHandler [WEAK]
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HardFault_Handler
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SVC_Handler
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PendSV_Handler
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SysTick_Handler
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SCU_0_IRQHandler
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SCU_1_IRQHandler
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SCU_2_IRQHandler
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ERU0_0_IRQHandler
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ERU0_1_IRQHandler
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ERU0_2_IRQHandler
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ERU0_3_IRQHandler
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USIC0_0_IRQHandler
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USIC0_1_IRQHandler
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USIC0_2_IRQHandler
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USIC0_3_IRQHandler
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USIC0_4_IRQHandler
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USIC0_5_IRQHandler
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VADC0_C0_0_IRQHandler
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VADC0_C0_1_IRQHandler
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VADC0_G0_0_IRQHandler
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VADC0_G0_1_IRQHandler
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VADC0_G1_0_IRQHandler
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VADC0_G1_1_IRQHandler
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CCU40_0_IRQHandler
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CCU40_1_IRQHandler
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CCU40_2_IRQHandler
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CCU40_3_IRQHandler
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LEDTS0_0_IRQHandler
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LEDTS1_0_IRQHandler
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BCCU0_0_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */
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; Veneers are located to fix SRAM Address 0x2000'0000
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AREA |.ARM.__at_0x20000000|, CODE, READWRITE
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; Each Veneer has exactly a lengs of 4 Byte
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MACRO
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STAYHERE $IrqNumber
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LDR R0, =$IrqNumber
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B .
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MEND
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MACRO
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JUMPTO $Handler
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LDR R0, =$Handler
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BX R0
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MEND
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STAYHERE 0x0 ;* Reserved
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STAYHERE 0x1 ;* Reserved
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STAYHERE 0x2 ;* Reserved
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JUMPTO HardFault_Handler ;* HardFault Veneer
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STAYHERE 0x4 ;* Reserved
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STAYHERE 0x5 ;* Reserved
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STAYHERE 0x6 ;* Reserved
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STAYHERE 0x7 ;* Reserved
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STAYHERE 0x8 ;* Reserved
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STAYHERE 0x9 ;* Reserved
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STAYHERE 0xA ;* Reserved
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JUMPTO SVC_Handler ;* SVC Veneer
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STAYHERE 0xC ;* Reserved
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STAYHERE 0xD ;* Reserved
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JUMPTO PendSV_Handler ;* PendSV Veneer
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JUMPTO SysTick_Handler ;* SysTick Veneer
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JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer
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JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer
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JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer
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JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer
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JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer
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JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer
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JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer
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STAYHERE 0x17 ;* Reserved
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STAYHERE 0x18 ;* Reserved
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JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer
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JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer
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JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer
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JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer
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JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer
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JUMPTO USIC0_5_IRQHandler ;* USIC0_5 Veneer
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JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer
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JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer
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JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer
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JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer
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JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer
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JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer
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JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer
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JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer
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JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer
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JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer
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STAYHERE 0x29 ;* Reserved
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STAYHERE 0x2A ;* Reserved
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STAYHERE 0x2B ;* Reserved
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STAYHERE 0x2C ;* Reserved
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JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer
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JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer
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JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer
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ALIGN
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;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */
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END
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