340 lines
16 KiB
ArmAsm
340 lines
16 KiB
ArmAsm
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;*********************************************************************************************************************
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;* @file startup_XMC1400.s
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;* @brief CMSIS Core Device Startup File for Infineon XMC1400 Device Series
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;* @version V1.0
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;* @date 03 Sep 2015
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;*
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;* @cond
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;*********************************************************************************************************************
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;* Copyright (c) 2015-2016, Infineon Technologies AG
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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;* following conditions are met:
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;*
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;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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;* disclaimer.
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;*
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;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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;* disclaimer in the documentation and/or other materials provided with the distribution.
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;*
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;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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;* products derived from this software without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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;* Infineon Technologies AG dave@infineon.com).
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;*********************************************************************************************************************
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;*
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;**************************** Change history ********************************
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;* V1.0, Sep, 03, 2015 JFT:Initial version
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;* MCLK=8MHz, PCLK=16MHz
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;*
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;* @endcond
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;*
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; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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;****************************************************************************
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; <h> Clock system handling by SSW
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; <h> CLK_VAL1 Configuration
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; <o0.0..9> FDIV Fractional Divider Selection <0-1023>
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; <i> Deafult: 0. Fractional part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024))
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; <o0.10..17> IDIV Divider Selection <1-16>
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; <i> Deafult: 6. Interger part of clock divider, MCLK = DCO1 / (IDIV + (FDIV / 1024) = 8MHz)
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; <o0.18> PCLKSEL PCLK Clock Select
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; <0=> PCLK = MCLK
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; <1=> PCLK = 2 x MCLK
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; <i> Deafult: 2 x MCLK
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; <o0.19..21> RTCCLKSEL RTC Clock Select
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; <0=> 32.768kHz standby clock
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; <1=> 32.768kHz external clock from ERU0.IOUT0
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; <2=> 32.768kHz external clock from ACMP0.OUT
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; <3=> 32.768kHz external clock from ACMP1.OUT
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; <4=> 32.768kHz external clock from ACMP2.OUT
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; <5=> 32.768kHz XTAL clock via OSC_LP
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; <6=> Reserved
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; <7=> Reserved
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; <i> Deafult: 32.768kHz standby clock
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; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]
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; </h>
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;*****************************************************************************
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CLK_VAL1_Val EQU 0x00041800
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;*****************************************************************************
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; <h> CLK_VAL2 Configuration
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; <o0.0> disable VADC and SHS Gating
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; <o0.1> disable CCU80 Gating
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; <o0.2> disable CCU40 Gating
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; <o0.3> disable USIC0 Gating
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; <o0.4> disable BCCU0 Gating
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; <o0.5> disable LEDTS0 Gating
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; <o0.6> disable LEDTS1 Gating
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; <o0.7> disable POSIF0 Gating
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; <o0.8> disable MATH Gating
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; <o0.9> disable WDT Gating
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; <o0.10> disable RTC Gating
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; <o0.16> disable CCU81 Gating
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; <o0.17> disable CCU41 Gating
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; <o0.18> disable USIC1 Gating
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; <o0.19> disable LEDTS2 Gating
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; <o0.20> disable POSIF1 Gating
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; <o0.21> disable MCAN0 Gating
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; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]
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; </h>
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;*****************************************************************************
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CLK_VAL2_Val EQU 0x00000100
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; </h>
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD CLK_VAL1_Val ; CLK_VAL1
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DCD CLK_VAL2_Val ; CLK_VAL2
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"
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; The real veneers will be copied later from the scatter loader before reaching main.
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; This init code should handle an exception before the real veneers are copied.
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SRAM_BASE EQU 0x20000000
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VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .
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LDR R1, =SRAM_BASE
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LDR R2, =VENEER_INIT_CODE
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MOVS R0, #48 ; Veneer 0..47
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Init_Veneers
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STR R2, [R1]
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ADDS R1, #4
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SUBS R0, R0, #1
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BNE Init_Veneers
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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Default_Handler PROC
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EXPORT HardFault_Handler [WEAK]
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EXPORT SVC_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT IRQ0_Handler [WEAK] ; SCU.SR0, CAN0.SR0, CCU40.SR0, SCU.SR0 | CAN0.SR0
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EXPORT IRQ1_Handler [WEAK] ; SCU.SR1, CAN0.SR1, CCU80.SR0, SCU.SR1 | CAN0.SR1
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EXPORT IRQ2_Handler [WEAK] ; SCU.SR2, CAN0.SR2, CCU80.SR1, SCU.SR2 | CAN0.SR2
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EXPORT IRQ3_Handler [WEAK] ; ERU0.SR0, ERU1.SR0, CAN0.SR0, ERU0.SR0 | ERU1.SR0
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EXPORT IRQ4_Handler [WEAK] ; ERU0.SR1, ERU1.SR1, CAN0.SR1, ERU0.SR1 | ERU1.SR1
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EXPORT IRQ5_Handler [WEAK] ; ERU0.SR2, ERU1.SR2, CAN0.SR2, ERU0.SR2 | ERU1.SR2
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EXPORT IRQ6_Handler [WEAK] ; ERU0.SR3, ERU1.SR3, CAN0.SR3, ERU0.SR3 | ERU1.SR3
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EXPORT IRQ7_Handler [WEAK] ; MATH.SR0, CAN0.SR3, CCU40.SR1, MATH.SR0 | CAN0.SR3
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EXPORT IRQ8_Handler [WEAK] ; LEDTS2.SR0, CCU40.SR0, CCU80.SR0, LEDTS2.SR0 | CCU40.SR0
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EXPORT IRQ9_Handler [WEAK] ; USIC0.SR0, USIC1.SR0, ERU0.SR0, USIC0.SR0 | USIC1.SR0
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EXPORT IRQ10_Handler [WEAK] ; USIC0.SR1, USIC1.SR1, ERU0.SR1, USIC0.SR1 | USIC1.SR1
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EXPORT IRQ11_Handler [WEAK] ; USIC0.SR2, USIC1.SR2, ERU0.SR2, USIC0.SR2 | USIC1.SR2
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EXPORT IRQ12_Handler [WEAK] ; USIC0.SR3, USIC1.SR3, ERU0.SR3, USIC0.SR3 | USIC1.SR3
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EXPORT IRQ13_Handler [WEAK] ; USIC0.SR4, USIC1.SR4, CCU80.SR1, USIC0.SR4 | USIC1.SR4
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EXPORT IRQ14_Handler [WEAK] ; USIC0.SR5, USIC1.SR5, POSIF0.SR0, USIC0.SR5 | USIC1.SR5
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EXPORT IRQ15_Handler [WEAK] ; VADC0.C0SR0, USIC0.SR0, POSIF0.SR1, VADC0.C0SR0 | USIC0.SR0
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EXPORT IRQ16_Handler [WEAK] ; VADC0.C0SR1, USIC0.SR1, CCU40.SR2, VADC0.C0SR1 | USIC0.SR1
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EXPORT IRQ17_Handler [WEAK] ; VADC0.G0SR0, USIC0.SR2, CAN0.SR0, VADC0.G0SR0 | USIC0.SR2
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EXPORT IRQ18_Handler [WEAK] ; VADC0.G0SR1, USIC0.SR3, CAN0.SR1, VADC0.G0SR1 | USIC0.SR3
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EXPORT IRQ19_Handler [WEAK] ; VADC0.G1SR0, USIC0.SR4, CAN0.SR2, VADC0.G1SR0 | USIC0.SR4
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EXPORT IRQ20_Handler [WEAK] ; VADC0.G1SR1, USIC0.SR5, CAN0.SR3, VADC0.G1SR1 | USIC0.SR5
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EXPORT IRQ21_Handler [WEAK] ; CCU40.SR0, CCU41.SR0, USIC0.SR0, CCU40.SR0 | CCU41.SR0
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EXPORT IRQ22_Handler [WEAK] ; CCU40.SR1, CCU41.SR1, USIC0.SR1, CCU40.SR1 | CCU41.SR1
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EXPORT IRQ23_Handler [WEAK] ; CCU40.SR2, CCU41.SR2, USIC0.SR2, CCU40.SR2 | CCU41.SR2
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EXPORT IRQ24_Handler [WEAK] ; CCU40.SR3, CCU41.SR3, USIC0.SR3, CCU40.SR3 | CCU41.SR3
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EXPORT IRQ25_Handler [WEAK] ; CCU80.SR0, CCU81.SR0, USIC0.SR4, CCU80.SR0 | CCU81.SR0
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EXPORT IRQ26_Handler [WEAK] ; CCU80.SR1, CCU81.SR1, USIC0.SR5, CCU80.SR1 | CCU81.SR1
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EXPORT IRQ27_Handler [WEAK] ; POSIF0.SR0, POSIF1.SR0, CCU40.SR3, POSIF0.SR0 | POSIF1.SR0
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EXPORT IRQ28_Handler [WEAK] ; POSIF0.SR1, POSIF1.SR1, ERU0.SR0, POSIF0.SR1 | POSIF1.SR1
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EXPORT IRQ29_Handler [WEAK] ; LEDTS0.SR0, CCU40.SR1, ERU0.SR1, LEDTS0.SR0 | CCU40.SR1
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EXPORT IRQ30_Handler [WEAK] ; LEDTS1.SR0, CCU40.SR2, ERU0.SR2, LEDTS1.SR0 | CCU40.SR2
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EXPORT IRQ31_Handler [WEAK] ; BCCU0.SR0, CCU40.SR3, ERU0.SR3, BCCU0.SR0 | CCU40.SR3
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HardFault_Handler
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SVC_Handler
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PendSV_Handler
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SysTick_Handler
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IRQ0_Handler
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IRQ1_Handler
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IRQ2_Handler
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IRQ3_Handler
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IRQ4_Handler
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IRQ5_Handler
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IRQ6_Handler
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IRQ7_Handler
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IRQ8_Handler
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IRQ9_Handler
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IRQ10_Handler
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IRQ11_Handler
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IRQ12_Handler
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IRQ13_Handler
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IRQ14_Handler
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IRQ15_Handler
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IRQ16_Handler
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IRQ17_Handler
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IRQ18_Handler
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IRQ19_Handler
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IRQ20_Handler
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IRQ21_Handler
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IRQ22_Handler
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IRQ23_Handler
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IRQ24_Handler
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IRQ25_Handler
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IRQ26_Handler
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IRQ27_Handler
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IRQ28_Handler
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IRQ29_Handler
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IRQ30_Handler
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IRQ31_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */
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; Veneers are located to fix SRAM Address 0x2000'000C
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AREA |.ARM.__at_0x2000000C|, CODE, READWRITE
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; Each Veneer has exactly a length of 4 Byte
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MACRO
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JUMPTO $Handler
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LDR R0, =$Handler
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BX R0
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MEND
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JUMPTO HardFault_Handler
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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JUMPTO SVC_Handler
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DCD 0
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DCD 0
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JUMPTO PendSV_Handler
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JUMPTO SysTick_Handler
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JUMPTO IRQ0_Handler
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JUMPTO IRQ1_Handler
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JUMPTO IRQ2_Handler
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JUMPTO IRQ3_Handler
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JUMPTO IRQ4_Handler
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JUMPTO IRQ5_Handler
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JUMPTO IRQ6_Handler
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JUMPTO IRQ7_Handler
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JUMPTO IRQ8_Handler
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JUMPTO IRQ9_Handler
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JUMPTO IRQ10_Handler
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JUMPTO IRQ11_Handler
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JUMPTO IRQ12_Handler
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JUMPTO IRQ13_Handler
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JUMPTO IRQ14_Handler
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JUMPTO IRQ15_Handler
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JUMPTO IRQ16_Handler
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JUMPTO IRQ17_Handler
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JUMPTO IRQ18_Handler
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JUMPTO IRQ19_Handler
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JUMPTO IRQ20_Handler
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JUMPTO IRQ21_Handler
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|
JUMPTO IRQ22_Handler
|
||
|
|
JUMPTO IRQ23_Handler
|
||
|
|
JUMPTO IRQ24_Handler
|
||
|
|
JUMPTO IRQ25_Handler
|
||
|
|
JUMPTO IRQ26_Handler
|
||
|
|
JUMPTO IRQ27_Handler
|
||
|
|
JUMPTO IRQ28_Handler
|
||
|
|
JUMPTO IRQ29_Handler
|
||
|
|
JUMPTO IRQ30_Handler
|
||
|
|
JUMPTO IRQ31_Handler
|
||
|
|
|
||
|
|
ALIGN
|
||
|
|
|
||
|
|
;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */
|
||
|
|
|
||
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|
END
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