133 lines
6.4 KiB
C
133 lines
6.4 KiB
C
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/*********************************************************************************************************************
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* @file system_XMC1100.c
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* @brief Device specific initialization for the XMC1100-Series according to CMSIS
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* @version V1.11
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* @date 19 Jun 2017
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2012-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* *************************** Change history ********************************
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* V1.2, 13 Dec 2012, PKB : Created change history table
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* V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation
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* V1.4, 02 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK
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* V1.5, 27 Nov 2013, DNE : Comments added in SystemInit function for MCLK support
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* V1.6, 19 Feb 2014, JFT : Fixed SystemCoreClock when FDIV != 0
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* V1.7, 11 Dec 2014, JFT : SystemCoreClockSetup, SystemCoreSetup as weak functions
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* V1.8, 03 Sep 2015, JFT : Override values of CLOCK_VAL1 and CLOCK_VAL2 defined in vector table (startup.s)
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* MCLK = 32MHz, PCLK = 64MHz
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* V1.9, 31 Mar 2016, JFT : Fix flash wait states to 1 cycle
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* V1.10,22 Aug 2016, JFT : Update coding for fixed flash wait states using new macros in device header file
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* Add macro guard USE_DYNAMIC_FLASH_WS. If defined in compiler options, adaptive wait states
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* are used for read accesses to the flash memory. Otherwise a fixed 1 WS is used.
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* V1.11,19 Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK
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* Added support for ARM Compiler 6 (armclang)
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*
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* @endcond
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*/
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/*******************************************************************************
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* HEADER FILES
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*******************************************************************************/
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#include <XMC1100.h>
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#include "system_XMC1100.h"
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/*******************************************************************************
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* MACROS
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*******************************************************************************/
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#define DCO1_FREQUENCY (64000000U)
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/*******************************************************************************
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* GLOBAL VARIABLES
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*******************************************************************************/
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((at(0x20003FFC)));
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x20003FFC")));
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#elif defined ( __ICCARM__ )
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__no_init uint32_t SystemCoreClock;
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((section(".no_init")));
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#elif defined ( __TASKING__ )
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uint32_t SystemCoreClock __at( 0x20003FFC );
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#endif
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/*******************************************************************************
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* API IMPLEMENTATION
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*******************************************************************************/
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__WEAK void SystemInit(void)
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{
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SystemCoreSetup();
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SystemCoreClockSetup();
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}
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__WEAK void SystemCoreSetup(void)
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{
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#ifndef USE_DYNAMIC_FLASH_WS
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/* Fix flash wait states to 1 cycle (see DS Addendum) */
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NVM->NVMCONF |= NVM_NVMCONF_WS_Msk;
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NVM->CONFIG1 |= NVM_CONFIG1_FIXWS_Msk;
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#endif
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}
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__WEAK void SystemCoreClockSetup(void)
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{
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/* Override values of CLOCK_VAL1 and CLOCK_VAL2 defined in vector table */
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/* MCLK = 32MHz, PCLK = 64MHz */
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SCU_GENERAL->PASSWD = 0x000000C0UL; /* disable bit protection */
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SCU_CLK->CLKCR = 0x3FF10100UL;
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while((SCU_CLK->CLKCR & SCU_CLK_CLKCR_VDDC2LOW_Msk));
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SCU_GENERAL->PASSWD = 0x000000C3UL; /* enable bit protection */
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SystemCoreClockUpdate();
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}
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__WEAK void SystemCoreClockUpdate(void)
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{
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static uint32_t IDIV, FDIV;
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IDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;
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FDIV = ((SCU_CLK->CLKCR) & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;
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if (IDIV != 0)
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{
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/* Fractional divider is enabled and used */
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SystemCoreClock = ((DCO1_FREQUENCY << 6U) / ((IDIV << 8) + FDIV)) << 1U;
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}
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else
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{
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/* Fractional divider bypassed. Simply divide DCO_DCLK by 2 */
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SystemCoreClock = DCO1_FREQUENCY >> 1U;
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}
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}
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