Infineon XMC1300 1.3.0 (Reference Manual v1.3) SVD file CM0 r0p0 little false false 2 false 8 32 PPB Cortex-M0 Private Peripheral Block 0xE000E000 0x0 0x1000 registers SYST_CSR SysTick Control and Status Register 0x0010 32 0x00000000 0xFFFFFFFF ENABLE Counter Enable 0 0 read-write value1 Counter disabled. #0 value2 Counter enabled. #1 TICKINT SysTick Exception Request 1 1 read-write value1 Counting down to zero does not assert the SysTick exception request. #0 value2 Counting down to zero to assert the SysTick exception request. #1 CLKSOURCE Clock Source 2 2 read-write value1 External clock. #0 value2 Processor clock. #1 COUNTFLAG Counter Flag 16 16 read-write SYST_RVR SysTick Reload Value Register 0x0014 32 0x00000000 0x00000000 RELOAD Reload Value 0 23 read-write SYST_CVR SysTick Current Value Register 0x0018 32 0x00000000 0x00000000 CURRENT SysTick Counter Current Value 0 23 read-write SYST_CALIB SysTick Calibration Value Register 0x001C 32 0x40000147 0xFFFFFFFF TENMS 10 Milliseconds 0 23 read-only SKEW Clock Skew 30 30 read-only NOREF Reference Clock 31 31 read-only NVIC_ISER Interrupt Set-enable Register 0x0100 32 0x00000000 0xFFFFFFFF SETENA Interrupt Node Set-enable 0 31 read-write value1 Read: Interrupt node disabled. Write: No effect. #0 value2 Read: Interrupt node enabled. Write: Enable interrupt node #1 NVIC_ICER IInterrupt Clear-enable Register 0x0180 32 0x00000000 0xFFFFFFFF CLRENA Interrupt Node Clear-enable 0 31 read-write value1 Read: Interrupt node disabled. Write: No effect #0 value2 Read: Interrupt node enabled. Write: Disable interrupt node. #1 NVIC_ISPR Interrupt Set-pending Register 0x0200 32 0x00000000 0xFFFFFFFF SETPEND Interrupt Node Set-pending 0 31 read-write value1 Read: Interrupt node is not pending. Write: No effect #0 value2 Read: Interrupt node is pending. Write: Change interrupt state to pending. #1 NVIC_ICPR Interrupt Clear-pending Register 0x0280 32 0x00000000 0xFFFFFFFF CLRPEND Interrupt Node Clear-pending 0 31 read-write value1 Read: Interrupt node is not pending. Write: No effect. #0 value2 Read: Interrupt node is pending. Write: Remove interrupt state from pending. #1 NVIC_IPR0 Interrupt Priority Register 0 0x0400 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR1 Interrupt Priority Register 1 0x0404 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR2 Interrupt Priority Register 2 0x0408 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR3 Interrupt Priority Register 3 0x040C 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR4 Interrupt Priority Register 4 0x0410 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR5 Interrupt Priority Register 5 0x0414 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR6 Interrupt Priority Register 6 0x0418 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write NVIC_IPR7 Interrupt Priority Register 7 0x041C 32 0x00000000 0xFFFFFFFF PRI_3 Priority, Byte Offset 3 24 31 read-write PRI_2 Priority, Byte Offset 2 16 23 read-write PRI_1 Priority, Byte Offset 1 8 15 read-write PRI_0 Priority, Byte Offset 0 0 7 read-write CPUID CPUID Base Register 0x0D00 32 0x410CC200 0xFFFFFFFF Revision Revision Number 0 3 read-only value1 Patch 0 0x0 PartNo Part Number of the Processor 4 15 read-only value1 Cortex-M0 0xC20 Architecture Architecture 16 19 read-only value1 ARMv6-M 0xC Variant Variant Number 20 23 read-only value1 Revision 0 0x0 Implementer Implementer Code 24 31 read-only value1 ARM 0x41 ICSR Interrupt Control and State Register 0x0D04 32 0x00000000 0xFFFFFFFF VECTACTIVE Active Exception Number 0 5 read-only value1 Thread mode 0x00 VECTPENDING Pending Exception Number 12 17 read-only value1 No pending exceptions 0x0 ISRPENDING Interrupt Pending Flag 22 22 read-only value1 Interrupt not pending #0 value2 Interrupt pending. #1 PENDSTCLR SysTick Exception Clear-pending 25 25 write-only value1 No effect #0 value2 removes the pending state from the SysTick exception. #1 PENDSTSET SysTick Exception Set-pending 26 26 read-write value1 SysTick exception is not pending 0 value2 SysTick exception is pending. 1 PENDSVCLR PendSV Clear Pending 27 27 write-only value1 Do not clear. #0 value2 Removes pending state from PendSV exception. #1 PENDSVSET PendSV Set Pending 28 28 read-write value1 PendSV exception is not pending. #0 value2 PendSV excepton is pending. #1 AIRCR Application Interrupt and Reset Control Register 0x0D0C 32 0xFA050000 0xFFFFFFFF SYSRESETREQ System Reset Request 2 2 write-only value1 No effect. #0 value2 Requests a system level reset. #1 ENDIANNESS Data Endianness 15 15 read-only value1 Little-endian #0 VECTKEY Register Key 16 31 read-write SCR System Control Register 0x0D10 32 0x00000000 0xFFFFFFFF SLEEPONEXIT Sleep-on-exit 1 1 read-write value1 Do not sleep when returning to Thread mode. #0 value2 Enter sleep, or deep sleep, on return from an ISR to Thread mode. #1 SLEEPDEEP Low Power Sleep Mode 2 2 read-write value1 Sleep #0 value2 Deep sleep #1 SEVONPEND Send Event on Pending bit 4 4 read-write value1 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. #0 value2 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. #1 CCR Configuration and Control Register 0x0D14 32 0x00000208 0xFFFFFFFF UNALIGN_TRP Unaligned Access Traps 3 3 read-only STKALIGN Stack Alignment 9 9 read-only SHPR2 System Handler Priority Register 2 0x0D1C 32 0x00000000 0xFFFFFFFF PRI_11 Priority of System Handler 11 24 31 read-write SHPR3 System Handler Priority Register 3 0x0D20 32 0x00000000 0xFFFFFFFF PRI_14 Priority of System Handler 14 16 23 read-write PRI_15 Priority of System Handler 15 24 31 read-write SHCSR System Handler Control and State Register 0x0D24 32 0x00000000 0xFFFFFFFF SVCALLPENDED SVCall Pending bit 15 15 read-write value1 SVCall is not pending. #0 value2 SVCall is pending. #1 ERU0 Event Request Unit 0 ERU 0x40010600 0x0 0x0100 registers ERU0_0 External Request Unit 0 3 ERU0_1 External Request Unit 0 4 ERU0_2 External Request Unit 0 5 ERU0_3 External Request Unit 0 6 EXISEL Event Input Select 0x00 32 0x00000000 0xFFFFFFFF EXS0A Event Source Select for A0 (ERS0) 0 1 read-write value1 Input ERU_0A0 is selected #00 value2 Input ERU_0A1 is selected #01 value3 Input ERU_0A2 is selected #10 value4 Input ERU_0A3 is selected #11 EXS0B Event Source Select for B0 (ERS0) 2 3 read-write value1 Input ERU_0B0 is selected #00 value2 Input ERU_0B1 is selected #01 value3 Input ERU_0B2 is selected #10 value4 Input ERU_0B3 is selected #11 EXS1A Event Source Select for A1 (ERS1) 4 5 read-write value1 Input ERU_1A0 is selected #00 value2 Input ERU_1A1 is selected #01 value3 Input ERU_1A2 is selected #10 value4 Input ERU_1A3 is selected #11 EXS1B Event Source Select for B1 (ERS1) 6 7 read-write value1 Input ERU_1B0 is selected #00 value2 Input ERU_1B1 is selected #01 value3 Input ERU_1B2 is selected #10 value4 Input ERU_1B3 is selected #11 EXS2A Event Source Select for A2 (ERS2) 8 9 read-write value1 Input ERU_2A0 is selected #00 value2 Input ERU_2A1 is selected #01 value3 Input ERU_2A2 is selected #10 value4 Input ERU_2A3 is selected #11 EXS2B Event Source Select for B2 (ERS2) 10 11 read-write value1 Input ERU_2B0 is selected #00 value2 Input ERU_2B1 is selected #01 value3 Input ERU_2B2 is selected #10 value4 Input ERU_2B3 is selected #11 EXS3A Event Source Select for A3 (ERS3) 12 13 read-write value1 Input ERU_3A0 is selected #00 value2 Input ERU_3A1 is selected #01 value3 Input ERU_3A2 is selected #10 value4 Input ERU_3A3 is selected #11 EXS3B Event Source Select for B3 (ERS3) 14 15 read-write value1 Input ERU_3B0 is selected #00 value2 Input ERU_3B1 is selected #01 value3 Input ERU_3B2 is selected #10 value4 Input ERU_3B3 is selected #11 4 4 EXICON[%s] Event Input Control 0x10 32 0x00000000 0xFFFFFFFF PE Output Trigger Pulse Enable for ETLx 0 0 read-write value1 The trigger pulse generation is disabled #0 value2 The trigger pulse generation is enabled #1 LD Rebuild Level Detection for Status Flag for ETLx 1 1 read-write value1 The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software. #0 value2 The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. #1 RE Rising Edge Detection Enable ETLx 2 2 read-write value1 A rising edge is not considered as edge event #0 value2 A rising edge is considered as edge event #1 FE Falling Edge Detection Enable ETLx 3 3 read-write value1 A falling edge is not considered as edge event #0 value2 A falling edge is considered as edge event #1 OCS Output Channel Select for ETLx Output Trigger Pulse 4 6 read-write value1 Trigger pulses are sent to OGU0 #000 value2 Trigger pulses are sent to OGU1 #001 value3 Trigger pulses are sent to OGU2 #010 value4 Trigger pulses are sent to OGU3 #011 FL Status Flag for ETLx 7 7 read-write value1 The enabled edge event has not been detected #0 value2 The enabled edge event has been detected #1 SS Input Source Select for ERSx 8 9 read-write value1 Input A without additional combination #00 value2 Input B without additional combination #01 value3 Input A OR input B #10 value4 Input A AND input B #11 NA Input A Negation Select for ERSx 10 10 read-write value1 Input A is used directly #0 value2 Input A is inverted #1 NB Input B Negation Select for ERSx 11 11 read-write value1 Input B is used directly #0 value2 Input B is inverted #1 4 4 EXOCON[%s] Event Output Trigger Control 0x20 32 0x00000008 0xFFFFFFFF ISS Internal Trigger Source Selection 0 1 read-write value1 The peripheral trigger function is disabled #00 value2 Input ERU_OGUy1 is selected #01 value3 Input ERU_OGUy2 is selected #10 value4 Input ERU_OGUy3 is selected #11 GEEN Gating Event Enable 2 2 read-write value1 The event detection is disabled #0 value2 The event detection is enabled #1 PDR Pattern Detection Result Flag 3 3 read-only value1 A pattern miss is detected #0 value2 A pattern match is detected #1 GP Gating Selection for Pattern Detection Result 4 5 read-write value1 ERU_GOUTy is always disabled and ERU_IOUTy can not be activated #00 value2 ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy #01 value3 ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) #10 value4 ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) #11 IPEN0 Pattern Detection Enable for ETL0 12 12 read-write value1 Flag EXICONx.FL is excluded from the pattern detection #0 value2 Flag EXICONx.FL is included in the pattern detection #1 IPEN1 Pattern Detection Enable for ETL1 13 13 read-write value1 Flag EXICONx.FL is excluded from the pattern detection #0 value2 Flag EXICONx.FL is included in the pattern detection #1 IPEN2 Pattern Detection Enable for ETL2 14 14 read-write value1 Flag EXICONx.FL is excluded from the pattern detection #0 value2 Flag EXICONx.FL is included in the pattern detection #1 IPEN3 Pattern Detection Enable for ETL3 15 15 read-write value1 Flag EXICONx.FL is excluded from the pattern detection #0 value2 Flag EXICONx.FL is included in the pattern detection #1 MATH MATH Unit 0x40030000 0x0 0x60 registers MATH0_0 MATH Unit 0 7 GLBCON Global Control Register 0x04 32 0x00000000 0xFFFFFFFF DVDRC Dividend Register Result Chaining 0 2 read-write value1 No result chaining is selected #000 value2 QUOT register is the selected source #001 value3 RMD register is the selected source #010 value4 CORRX is the selected source #011 value5 CORRY is the selected source #100 value6 CORRZ is the selected source #101 DVSRC Divisor Register Result Chaining 3 5 read-write value1 No result chaining is selected #000 value2 QUOT register is the selected source #001 value3 RMD register is the selected source #010 value4 CORRX is the selected source #011 value5 CORRY is the selected source #100 value6 CORRZ is the selected source #101 CORDXRC CORDX Register Result Chaining 6 7 read-write value1 No result chaining is selected #00 value2 QUOT register is the selected source #01 value3 RMD register is the selected source #10 CORDYRC CORDY Register Result Chaining 9 10 read-write value1 No result chaining is selected #00 value2 QUOT register is the selected source #01 value3 RMD register is the selected source #10 CORDZRC CORDZ Register Result Chaining 12 13 read-write value1 No result chaining is selected #00 value2 QUOT register is the selected source #01 value3 RMD register is the selected source #10 SUSCFG Suspend Mode Configuration 16 17 read-write value1 Suspend mode is never entered. #00 value2 Hard suspend mode will be entered when CPU is halted. #01 value3 Soft suspend mode will be entered when CPU is halted. #10 ID Module Identification Register 0x08 32 0x00F2C000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only EVIER Event Interrupt Enable Register 0x0C 32 0x00000000 0xFFFFFFFF DIVEOCIEN Divider End of Calculation Interrupt Enable 0 0 read-write value1 Divider end of calculation interrupt generation is disabled. #0 value2 Divider end of calculation interrupt generation is enabled. #1 DIVERRIEN Divider Error Interrupt Enable 1 1 read-write value1 Divider error interrupt generation is disabled #0 value2 Divider error interrupt generation is enabled #1 CDEOCIEN CORDIC End of Calculation Interrupt Enable 2 2 read-write value1 CORDIC end of calculation interrupt generation is disabled. #0 value2 CORDIC end of calculation interrupt generation is enabled. #1 CDERRIEN CORDIC Error Interrupt Enable 3 3 read-write value1 CORDIC error interrupt generation is disabled #0 value2 CORDIC error interrupt generation is enabled #1 EVFR Event Flag Register 0x10 32 0x00000000 0xFFFFFFFF DIVEOC Divider End of Calculation Event Flag 0 0 read-only value1 Divider end of calculation event has not been detected. #0 value2 Divider end of calculation event has been detected. #1 DIVERR Divider Error Event Flag 1 1 read-only value1 Divider error event has not been detected #0 value2 Divider error event has been detected #1 CDEOC CORDIC End of Calculation Event Flag 2 2 read-only value1 CORDIC end of calculation event has not been detected. #0 value2 CORDIC end of calculation event has been detected. #1 CDERR CORDIC Error Event Flag 3 3 read-only value1 CORDIC error event has not been detected #0 value2 CORDIC error event has been detected #1 EVFSR Event Flag Set Register 0x14 32 0x00000000 0xFFFFFFFF DIVEOCS Divider End of Calculation Event Flag Set 0 0 write-only value1 No effect. #0 value2 Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. #1 DIVERRS Divider Error Event Flag Set 1 1 write-only value1 No effect. #0 value2 Sets the Divider error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. #1 CDEOCS CORDIC Event Flag Set 2 2 write-only value1 No effect. #0 value2 Sets the CORDIC end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. #1 CDERRS CORDIC Error Event Flag Set 3 3 write-only value1 No effect. #0 value2 Sets the CORDIC error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register. #1 EVFCR Event Flag Clear Register 0x18 32 0x00000000 0xFFFFFFFF DIVEOCC Divider End of Calculation Event Flag Clear 0 0 write-only value1 No effect. #0 value2 Clears the Divider end of calculation event flag in EVFR register. #1 DIVERRC Divider Error Event Flag Clear 1 1 write-only value1 No effect. #0 value2 Clears the Divider error event flag in EVFR register. #1 CDEOCC CORDIC End of Calculation Event Flag Clear 2 2 write-only value1 No effect. #0 value2 Clears the CORDIC end of calculation event flag in EVFR register. #1 CDERRC CORDIC Error Event Flag Clear 3 3 write-only value1 No effect. #0 value2 Clears the CORDIC error event flag in EVFR register. #1 DVD Dividend Register 0x20 32 0x00000000 0xFFFFFFFF VAL Dividend Value 0 31 read-write DVS Divisor Register 0x24 32 0x00000000 0xFFFFFFFF VAL Divisor Value 0 31 read-write QUOT Quotient Register 0x28 32 0x00000000 0xFFFFFFFF VAL Quotient Value 0 31 read-only RMD Remainder Register 0x2C 32 0x00000000 0xFFFFFFFF VAL Remainder Value 0 31 read-only DIVST Divider Status Register 0x30 32 0x00000000 0xFFFFFFFF BSY Busy Indication 0 0 read-only value1 Divider is not running any division operation. #0 value2 Divider is still running a division operation. #1 DIVCON Divider Control Register 0x34 32 0x00000000 0xFFFFFFFF ST Start Bit 0 0 read-write value1 No effect #0 value2 Start the division operation when STMODE=1# #1 STMODE Start Mode 1 1 read-write value1 Calculation is automatically started with a write to DVS register #0 value2 Calculation is started by setting the ST bit to 1 #1 USIGN Unsigned Division Enable 2 2 read-write value1 Signed division is selected #0 value2 Unsigned division is selected #1 DIVMODE Division Mode 3 4 read-write value1 32-bit divide by 32-bit #00 value2 32-bit divide by 16-bit #01 value3 16-bit divide by 16-bit #10 QSDIR Quotient Shift Direction 15 15 read-write value1 Left shift #0 value2 Right shift #1 QSCNT Quotient Shift Count 8 12 read-write DVDSLC Dividend Shift Left Count 16 20 read-write DVSSRC Divisor Shift Right Count 24 28 read-write STATC CORDIC Status and Data Control Register 0x40 32 0x00000000 0xFFFFFFFF BSY Busy Indication 0 0 read-only KEEPX Last X Result as Initial Data for New Calculation 5 5 read-write KEEPY Last Y Result as Initial Data for New Calculation 6 6 read-write KEEPZ Last Z Result as Initial Data for New Calculation 7 7 read-write CON CORDIC Control Register 0x44 32 0x00000062 0xFFFFFFFF ST Start Calculation 0 0 read-write MODE Operating Mode 1 2 read-write value1 Linear Mode #00 value2 Circular Mode (default) #01 value4 Hyperbolic Mode #11 ROTVEC Rotation Vectoring Selection 3 3 read-write value1 Vectoring Mode (default) #0 value2 Rotation Mode #1 ST_MODE Start Method 4 4 read-write value1 Auto start of calculation after write access to X parameter data register CORDX(default). #0 value2 Start calculation only after bit ST is set #1 X_USIGN Result Data Format for X in Circular Vectoring Mode 5 5 read-write value1 Signed, twos complement #0 value2 Unsigned (default) #1 MPS X and Y Magnitude Prescaler 6 7 read-write value1 Divide by 1 #00 value2 Divide by 2 (default) #01 value3 Divide by 4 #10 value4 Reserved, retain the last MPS setting #11 CORDX CORDIC X Data Register 0x48 32 0x00000000 0xFFFFFFFF DATA Initial X Parameter Data 8 31 read-write CORDY CORDIC Y Data Register 0x4C 32 0x00000000 0xFFFFFFFF DATA Initial Y Parameter Data 8 31 read-write CORDZ CORDIC Z Data Register 0x50 32 0x00000000 0xFFFFFFFF DATA Initial Z Parameter Data 8 31 read-write CORRX CORDIC X Result Register 0x54 32 0x00000000 0xFFFFFFFF RESULT X Calculation Result 8 31 read-only CORRY CORDIC Y Result Register 0x58 32 0x00000000 0xFFFFFFFF RESULT Y Calculation Result 8 31 read-only CORRZ CORDIC Z Result Register 0x5C 32 0x00000000 0xFFFFFFFF RESULT Z Calculation Result 8 31 read-only PAU PAU Unit 0x40000000 0x0 0x010000 registers AVAIL0 Peripheral Availability Register 0 0x0040 32 0x01FF00FF 0xFFFFFFFF AVAIL5 RAM Block 1 Availability Flag 5 5 read-only value1 RAM block 1 is not available. #0 value2 RAM block 1 is available. #1 AVAIL6 RAM Block 2 Availability Flag 6 6 read-only value1 RAM block 2 is not available. #0 value2 RAM block 2 is available. #1 AVAIL7 RAM Block 3 Availability Flag 7 7 read-only value1 RAM block 3 is not available. #0 value2 RAM block 3 is available. #1 AVAIL20 MATH Global SFRs and Divider Availability Flag 20 20 read-only value1 MATH Global SFRs and Divider are not available. #0 value2 MATH Global SFRs and Divider are available. #1 AVAIL21 MATH CORDIC Availability Flag 21 21 read-only value1 MATH CORDIC is not available. #0 value2 MATH CORDIC is available. #1 AVAIL22 Port 0 Availability Flag 22 22 read-only value1 Port 0 is not available. #0 value2 Port 0 is available. #1 AVAIL23 Port 1 Availability Flag 23 23 read-only value1 Port 1 is not available. #0 value2 Port 1 is available. #1 AVAIL24 Port 0 Availability Flag 24 24 read-only value1 Port 2 is not available. #0 value2 Port 2 is available. #1 AVAIL1 Peripheral Availability Register 1 0x0044 32 0x00001FF7 0xFFFFFFFF AVAIL0 USIC0 Channel 0 Availability Flag 0 0 read-only value1 USIC0 Channel 0 is not available. #0 value2 USIC0 Channel 0 is available. #1 AVAIL1 USIC0 Channel 1 Availability Flag 1 1 read-only value1 USIC0 Channel 1 is not available. #0 value2 USIC0 Channel 1 is available. #1 AVAIL4 PRNG Availability Flag 4 4 read-only value1 PRNG is not available. #0 value2 PRNG is available. #1 AVAIL5 VADC0 Basic SFRs Availability Flag 5 5 read-only value1 VADC0 Basic SFRs are not available. #0 value2 VADC0 Basic SFRs are available. #1 AVAIL6 VADC0 Group 0 SFRs Availability Flag 6 6 read-only value1 VADC0 Group 0 SFRs are not available. #0 value2 VADC0 Group 0 SFRs are available. #1 AVAIL7 VADC0 Group 1 SFRs Availability Flag 7 7 read-only value1 VADC0 Group 1 SFRs are not available. #0 value2 VADC0 Group 1 SFRs are available. #1 AVAIL8 SHS0 Availability Flag 8 8 read-only value1 SHS0 is not available. #0 value2 SHS0 is available. #1 AVAIL9 CC40 Availability Flag 9 9 read-only value1 CC40 is not available. #0 value2 CC40 is available. #1 AVAIL10 CC41 Availability Flag 10 10 read-only value1 CC41 is not available. #0 value2 CC41 is available. #1 AVAIL11 CC42 Availability Flag 11 11 read-only value1 CC42 is not available. #0 value2 CC42 is available. #1 AVAIL12 CC43 Availability Flag 12 12 read-only value1 CC43 is not available. #0 value2 CC43 is available. #1 AVAIL2 Peripheral Availability Register 2 0x0048 32 0x0000900F 0xFFFFFFFF AVAIL0 CC80 and CCU80 kernel SFRs Availability Flag 0 0 read-only value1 CC80 and CCU80 kernel SFRs are not available. #0 value2 CC80 and CCU80 kernel SFRs are available. #1 AVAIL1 CC81 Availability Flag 1 1 read-only value1 CC81 is not available. #0 value2 CC81 is available. #1 AVAIL2 CC82 Availability Flag 2 2 read-only value1 CC82 is not available. #0 value2 CC82 is available. #1 AVAIL3 CC83 Availability Flag 3 3 read-only value1 CC83 is not available. #0 value2 CC83 is available. #1 AVAIL12 POSIF0 Availability Flag 12 12 read-only value1 POSIF0 is not available. #0 value2 POSIF0 is available. #1 AVAIL15 BCCU0 Availability Flag 15 15 read-only value1 BCCU0 is not available. #0 value2 BCCU0 is available. #1 PRIVDIS0 Peripheral Privilege Access Register 0 0x0080 32 0x00000000 0xFFFFFFFF PDIS2 Flash SFRs Privilege Disable Flag 2 2 read-write value1 Flash SFRs are accessible. #0 value2 Flash SFRs are not accessible. #1 PDIS5 RAM Block 1 Privilege Disable Flag 5 5 read-write value1 RAM Block 1 is accessible. #0 value2 RAM Block 1 is not accessible. #1 PDIS6 RAM Block 2 Privilege Disable Flag 6 6 read-write value1 RAM Block 2 is accessible. #0 value2 RAM Block 2 is not accessible. #1 PDIS7 RAM Block 3 Privilege Disable Flag 7 7 read-write value1 RAM Block 3 is accessible. #0 value2 RAM Block 3 is not accessible. #1 PDIS19 WDT Privilege Disable Flag 19 19 read-write value1 WDT is accessible. #0 value2 WDT is not accessible. #1 PDIS20 MATH Global SFRs and Divider Privilege Disable Flag 20 20 read-write value1 MATH Global SFRs and Divider are accessible. #0 value2 MATH Global SFRs and Divider are not accessible. #1 PDIS21 MATH CORDIC Privilege Disable Flag 21 21 read-write value1 MATH CORDIC is accessible. #0 value2 MATH CORDIC is not accessible. #1 PDIS22 Port 0 Privilege Disable Flag 22 22 read-write value1 Port 0 is accessible. #0 value2 Port 0 is not accessible. #1 PDIS23 Port 1 Privilege Disable Flag 23 23 read-write value1 Port 1 is accessible. #0 value2 Port 1 is not accessible. #1 PDIS24 Port 2 Privilege Disable Flag 24 24 read-write value1 Port 2 is accessible. #0 value2 Port 2 is not accessible. #1 PRIVDIS1 Peripheral Privilege Access Register 1 0x0084 32 0x00000000 0xFFFFFFFF PDIS0 USIC0 Channel 0 Privilege Disable Flag 0 0 read-write value1 USIC0 Channel 0 is accessible. #0 value2 USIC0 Channel 0 is not accessible. #1 PDIS1 USIC0 Channel 1 Privilege Disable Flag 1 1 read-write value1 USIC0 Channel 1 is accessible. #0 value2 USIC0 Channel 1 is not accessible. #1 PDIS5 VADC0 Basic SFRs Privilege Disable Flag 5 5 read-write value1 VADC0 Basic SFRs are accessible. #0 value2 VADC0 Basic SFRs are not accessible. #1 PDIS6 VADC0 Group 0 SFRs Privilege Disable Flag 6 6 read-write value1 VADC0 Group 0 SFRs are accessible. #0 value2 VADC0 Group 0 SFRs are not accessible. #1 PDIS7 VADC0 Group 1 SFRs Privilege Disable Flag 7 7 read-write value1 VADC0 Group 1 SFRs are accessible. #0 value2 VADC0 Group 1 SFRs are not accessible. #1 PDIS8 SHS0 Privilege Disable Flag 8 8 read-write value1 SHS0 is accessible. #0 value2 SHS0 is not accessible. #1 PDIS9 CC40 and CCU40 Kernel SFRs Privilege Disable Flag 9 9 read-write value1 CC40 and CCU40 Kernel SFRs are accessible. #0 value2 CC40 and CCU40 Kernel SFRs are not accessible. #1 PDIS10 CC41 Privilege Disable Flag 10 10 read-write value1 CC41 is accessible. #0 value2 CC41 is not accessible. #1 PDIS11 CC42 Privilege Disable Flag 11 11 read-write value1 CC42 is accessible. #0 value2 CC42 is not accessible. #1 PDIS12 CC43 Privilege Disable Flag 12 12 read-write value1 CC43 is accessible. #0 value2 CC43 is not accessible. #1 PRIVDIS2 Peripheral Privilege Access Register 2 0x0088 32 0x00000000 0xFFFFFFFF PDIS0 CC80 and CCU80 Kernel SFRs Privilege Disable Flag 0 0 read-write value1 CC80 and CCU80 Kernel SFRs are accessible. #0 value2 CC80 and CCU80 Kernel SFRs are not accessible. #1 PDIS1 CC81 Privilege Disable Flag 1 1 read-write value1 CC81 is accessible. #0 value2 CC81 is not accessible. #1 PDIS2 CC82 Privilege Disable Flag 2 2 read-write value1 CC82 is accessible. #0 value2 CC82 is not accessible. #1 PDIS3 CC83 Privilege Disable Flag 3 3 read-write value1 CC83 is accessible. #0 value2 CC83 is not accessible. #1 PDIS12 POSIF0 Privilege Disable Flag 12 12 read-write value1 POSIF0 is accessible. #0 value2 POSIF0 is not accessible. #1 PDIS15 BCCU0 Privilege Disable Flag 15 15 read-write value1 BCCU0 is accessible. #0 value2 BCCU0 is not accessible. #1 ROMSIZE ROM Size Register 0x0400 32 0x00000B00 0xFFFFFFFF ADDR ROM Size 8 13 read-only FLSIZE Flash Size Register 0x0404 32 0x00033000 0xFFFFFFFF ADDR Flash Size 12 17 read-only RAM0SIZE RAM0 Size Register 0x0410 32 0x00001000 0xFFFFFFFF ADDR RAM0 Size 8 12 read-only NVM NVM Unit 0x40050000 0x0 0x0100 registers NVMSTATUS NVM Status Register 0x0000 16 0x0002 0xFFFF WRPERR Write Protocol Error 6 6 read-only value1 No write protocol failure occurred. #0 value2 At least one write protocol failure was detected. #1 ECC2READ ECC2 Read 5 5 read-only value1 No ECC two bit failure during memory read operations. #0 value2 At least one ECC two bit failure was detected. #1 ECC1READ ECC1 Read 4 4 read-only value1 No ECC single bit failure occurred. #0 value2 At least one ECC single bit failure was detected and corrected. #1 VERR Verify Error 2 3 read-only value1 No fail bit. #00 value2 One fail bit in one data block. #01 value3 Two fail bits in two different data blocks. #10 value4 Two or more fail bits in one data block, or three or more fail bits overall. #11 SLEEP Sleep Mode 1 1 read-only value1 NVM not in sleep mode, and no sleep or wake up procedure in progress. #0 value2 NVM in sleep mode, or busy due to a sleep or wake up procedure. #1 BUSY Busy 0 0 read-only value1 The NVM is not busy. Memory reads from the cell array and register write accesses are possible. #0 value2 The NVM is busy. Memory reads and register write accesses are not possible. #1 NVMPROG NVM Programming Control Register 0x0004 16 0x0000 0xFFFF RSTECC Reset ECC 13 13 read-write value1 No action. #0 value2 Reset of .ECCxREAD and NVMSTATUS.WRPERR. #1 RSTVERR Reset Verify Error 12 12 read-write value1 No action. #0 value2 Reset of .VERR. #1 ACTION ACTION: [VERIFY, ONE_SHOT, OPTYPE] 0 7 read-write value1 Idle state, no action triggered. Writing 0x00 exits current mode. 0x00 value2 Start one-shot write operation with automatic verify. 0x51 value3 Start one-shot write operation without verify. 0x91 value4 Start continuous write operation with automatic verify of every write. 0x61 value5 Start continuous write operation without verify. 0xA1 value6 Start one-shot page erase operation. 0x92 value7 Start continuous page erase operation. 0xA2 value8 Start one-shot verify-only: Written data is compared to array content. 0xD0 value9 Start continuous verify-only: Written data is compared to array content. 0xE0 NVMCONF NVM Configuration Register 0x0008 16 0x9000 0xFFFF NVM_ON NVM On 15 15 read-write value1 NVM is switched to or stays in sleep mode. #0 value2 NVM is switched to or stays in normal mode. #1 INT_ON Interrupt On 14 14 read-write value1 No NVM ready interrupts are generated. #0 value2 NVM ready interrupts are generated. #1 WS Number of fixed Wait States 12 12 read-write value1 0 fixed wait states. #0 value2 1 fixed wait state. #1 SECPROT Sector Protection 4 11 read-write HRLEV Hardread Level 1 2 read-write value1 Normal read #00 value2 Hardread written #01 value3 Hardread erased #10 CONFIG1 Configuration 1 Register 0x0048 16 0x0000 0x0000 FIXWS Wait States Scheme 11 11 read-write Const_0 adaptive wait states. #0 Const_1 fixed wait states. #1 WDT Watch Dog Timer 0x40020000 0x0 0x010000 registers ID WDT Module ID Register 0x00 32 0x00ADC000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only CTR WDT Control Register 0x04 32 0x00000000 0xFFFFFFFF ENB Enable 0 0 read-write PRE Pre-warning 1 1 read-write DSP Debug Suspend 4 4 read-write SPW Service Indication Pulse Width 8 15 read-write SRV WDT Service Register 0x08 32 0x00000000 0xFFFFFFFF SRV Service 0 31 write-only TIM WDT Timer Register 0x0C 32 0x00000000 0xFFFFFFFF TIM Timer Value 0 31 read-only WLB WDT Window Lower Bound Register 0x10 32 0x00000000 0xFFFFFFFF WLB Window Lower Bound 0 31 read-write WUB WDT Window Upper Bound Register 0x14 32 0xFFFFFFFF 0xFFFFFFFF WUB Window Upper Bound 0 31 read-write WDTSTS WDT Status Register 0x18 32 0x00000000 0xFFFFFFFF ALMS Pre-warning Alarm 0 0 read-only WDTCLR WDT Clear Register 0x1C 32 0x00000000 0xFFFFFFFF ALMC Pre-warning Alarm 0 0 write-only RTC Real Time Clock 0x40010A00 0x0 0x0100 registers ID RTC Module ID Register 0x00 32 0x00A3C000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only CTR RTC Control Register 0x04 32 0x7FFF0000 0xFFFFFFFF ENB RTC Module Enable 0 0 read-write SUS Debug Suspend Control 1 1 read-write DIV Divider Value 16 31 read-write RAWSTAT RTC Raw Service Request Register 0x08 32 0x00000000 0xFFFFFFFF RPSE Raw Periodic Seconds Service Request 0 0 read-only RPMI Raw Periodic Minutes Service Request 1 1 read-only RPHO Raw Periodic Hours Service Request 2 2 read-only RPDA Raw Periodic Days Service Request 3 3 read-only RPMO Raw Periodic Months Service Request 5 5 read-only RPYE Raw Periodic Years Service Request 6 6 read-only RAI Alarm Service Request 8 8 read-only STSSR RTC Service Request Status Register 0x0C 32 0x00000000 0xFFFFFFFF SPSE Periodic Seconds Service Request Status after masking 0 0 read-only SPMI Periodic Minutes Service Request Status after masking 1 1 read-only SPHO Periodic Hours Service Request Status after masking 2 2 read-only SPDA Periodic Days Service Request Status after masking 3 3 read-only SPMO Periodic Months Service Request Status after masking 5 5 read-only SPYE Periodic Years Service Request Status after masking 6 6 read-only SAI Alarm Service Request Status after masking 8 8 read-only MSKSR RTC Service Request Mask Register 0x10 32 0x00000000 0xFFFFFFFF MPSE Periodic Seconds Interrupt Mask 0 0 read-write MPMI Periodic Minutes Interrupt Mask 1 1 read-write MPHO Periodic Hours Interrupt Mask 2 2 read-write MPDA Periodic Days Interrupt Mask 3 3 read-write MPMO Periodic Months Interrupt Mask 5 5 read-write MPYE Periodic Years Interrupt Mask 6 6 read-write MAI Alarm Interrupt Mask 8 8 read-write CLRSR RTC Clear Service Request Register 0x14 32 0x00000000 0xFFFFFFFF RPSE Raw Periodic Seconds Interrupt Clear 0 0 write-only RPMI Raw Periodic Minutes Interrupt Clear 1 1 write-only RPHO Raw Periodic Hours Interrupt Clear 2 2 write-only RPDA Raw Periodic Days Interrupt Clear 3 3 write-only RPMO Raw Periodic Months Interrupt Clear 5 5 write-only RPYE Raw Periodic Years Interrupt Clear 6 6 write-only RAI Raw Alarm Interrupt Clear 8 8 write-only ATIM0 RTC Alarm Time Register 0 0x18 32 0x00000000 0xFFFFFFFF ASE Alarm Seconds Compare Value 0 5 read-write AMI Alarm Minutes Compare Value 8 13 read-write AHO Alarm Hours Compare Value 16 20 read-write ADA Alarm Days Compare Value 24 28 read-write ATIM1 RTC Alarm Time Register 1 0x1C 32 0x00000000 0xFFFFFFFF AMO Alarm Month Compare Value 8 11 read-write AYE Alarm Year Compare Value 16 31 read-write TIM0 RTC Time Register 0 0x20 32 0x00000000 0xFFFFFFFF SE Seconds Time Value 0 5 read-write MI Minutes Time Value 8 13 read-write HO Hours Time Value 16 20 read-write DA Days Time Value 24 28 read-write TIM1 RTC Time Register 1 0x24 32 0x00000000 0xFFFFFFFF DAWE Days of Week Time Value 0 2 read-write MO Month Time Value 8 11 read-write YE Year Time Value 16 31 read-write PRNG PRNG Unit 0x48020000 0x0 0x10 registers WORD PRNG Word Register 0x00 16 0x0000 0xFFFF RDATA Random Data 0 15 read-write CHK PRNG Status Check Register 0x04 16 0x0000 0xFFFF RDV Random Data / Key Valid Flag 0 0 read-only value1 New random data block is not yet ready to be read. In ) this flag is set to #0 while loading is in progress. #0 value2 Random data block is valid. In key loading mode this value indicates that the next partial key word can be written to PRNG_WORD. #1 CTRL PRNG Control Register 0x0C 16 0x0000 0xFFFF KLD Key Load Operation Mode 3 3 read-write value1 Streaming mode (default) #0 value2 Key loading mode #1 RDBS Random Data Block Size 1 2 read-write value1 Reset state (no random data block size defined), value of PRNG_WORD is undefined. #00 value2 8 bits in PRNG_WORD.RDATA[7:0] #01 value3 16 bits in PRNG_WORD.RDATA[15:0] #10 USIC0 Universal Serial Interface Controller 0 USIC USIC 0x48000008 0 4 registers USIC0_0 Universal Serial Interface Channel (Module 0) 9 USIC0_1 Universal Serial Interface Channel (Module 0) 10 USIC0_2 Universal Serial Interface Channel (Module 0) 11 USIC0_3 Universal Serial Interface Channel (Module 0) 12 USIC0_4 Universal Serial Interface Channel (Module 0) 13 USIC0_5 Universal Serial Interface Channel (Module 0) 14 ID Module Identification Register 0 32 0x00AAC000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only USIC0_CH0 Universal Serial Interface Controller 0 USIC USIC_CH 0x48000000 0x0 0x0200 registers CCFG Channel Configuration Register 0x004 32 0x000080CF 0xFFFFFFFF SSC SSC Protocol Available 0 0 read-only value1 The SSC protocol is not available. #0 value2 The SSC protocol is available. #1 ASC ASC Protocol Available 1 1 read-only value1 The ASC protocol is not available. #0 value2 The ASC protocol is available. #1 IIC IIC Protocol Available 2 2 read-only value1 The IIC protocol is not available. #0 value2 The IIC protocol is available. #1 IIS IIS Protocol Available 3 3 read-only value1 The IIS protocol is not available. #0 value2 The IIS protocol is available. #1 RB Receive FIFO Buffer Available 6 6 read-only value1 A receive FIFO buffer is not available. #0 value2 A receive FIFO buffer is available. #1 TB Transmit FIFO Buffer Available 7 7 read-only value1 A transmit FIFO buffer is not available. #0 value2 A transmit FIFO buffer is available. #1 KSCFG Kernel State Configuration Register 0x00C 32 0x00000000 0xFFFFFFFF MODEN Module Enable 0 0 read-write value1 The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). #0 value2 The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers. #1 BPMODEN Bit Protection for MODEN 1 1 write-only value1 MODEN is not changed. #0 value2 MODEN is updated with the written value. #1 NOMCFG Normal Operation Mode Configuration 4 5 read-write value1 Run mode 0 is selected. #00 value2 Run mode 1 is selected. #01 value3 Stop mode 0 is selected. #10 value4 Stop mode 1 is selected. #11 BPNOM Bit Protection for NOMCFG 7 7 write-only value1 NOMCFG is not changed. #0 value2 NOMCFG is updated with the written value. #1 SUMCFG Suspend Mode Configuration 8 9 read-write BPSUM Bit Protection for SUMCFG 11 11 write-only value1 SUMCFG is not changed. #0 value2 SUMCFG is updated with the written value. #1 FDR Fractional Divider Register 0x010 32 0x00000000 0xFFFFFFFF STEP Step Value 0 9 read-write DM Divider Mode 14 15 read-write value1 The divider is switched off, fFD = 0. #00 value2 Normal divider mode selected. #01 value3 Fractional divider mode selected. #10 value4 The divider is switched off, fFD = 0. #11 RESULT Result Value 16 25 read-only BRG Baud Rate Generator Register 0x014 32 0x00000000 0xFFFFFFFF CLKSEL Clock Selection 0 1 read-write value1 The fractional divider frequency fFD is selected. #00 value3 The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. #10 value4 Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. #11 TMEN Timing Measurement Enable 3 3 read-write value1 Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. #0 value2 Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. #1 PPPEN Enable 2:1 Divider for fPPP 4 4 read-write value1 The 2:1 divider for fPPP is disabled. fPPP = fPIN #0 value2 The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. #1 CTQSEL Input Selection for CTQ 6 7 read-write value1 fCTQIN = fPDIV #00 value2 fCTQIN = fPPP #01 value3 fCTQIN = fSCLK #10 value4 fCTQIN = fMCLK #11 PCTQ Pre-Divider for Time Quanta Counter 8 9 read-write DCTQ Denominator for Time Quanta Counter 10 14 read-write PDIV Divider Mode: Divider Factor to Generate fPDIV 16 25 read-write SCLKOSEL Shift Clock Output Select 28 28 read-write value1 SCLK from the baud rate generator is selected as the SCLKOUT input source. #0 value2 The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. #1 MCLKCFG Master Clock Configuration 29 29 read-write value1 The passive level is 0. #0 value2 The passive level is 1. #1 SCLKCFG Shift Clock Output Configuration 30 31 read-write value1 The passive level is 0 and the delay is disabled. #00 value2 The passive level is 1 and the delay is disabled. #01 value3 The passive level is 0 and the delay is enabled. #10 value4 The passive level is 1 and the delay is enabled. #11 INPR Interrupt Node Pointer Register 0x018 32 0x00000000 0xFFFFFFFF TSINP Transmit Shift Interrupt Node Pointer 0 2 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 TBINP Transmit Buffer Interrupt Node Pointer 4 6 read-write RINP Receive Interrupt Node Pointer 8 10 read-write AINP Alternative Receive Interrupt Node Pointer 12 14 read-write PINP Transmit Shift Interrupt Node Pointer 16 18 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 DX0CR Input Control Register 0 0x01C 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DXnA is selected. #000 value2 The data input DXnB is selected. #001 value3 The data input DXnC is selected. #010 value4 The data input DXnD is selected. #011 value5 The data input DXnE is selected. #100 value6 The data input DXnF is selected. #101 value7 The data input DXnG is selected. #110 value8 The data input is always 1. #111 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DXnT. #01 value3 A falling edge activates DXnT. #10 value4 Both edges activate DXnT. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DXnS is 0. #0 value2 The current value of DXnS is 1. #1 DX1CR Input Control Register 1 0x020 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DX1A is selected. #000 value2 The data input DX1B is selected. #001 value3 The data input DX1C is selected. #010 value4 The data input DX1D is selected. #011 value5 The data input DX1E is selected. #100 value6 The data input DX1F is selected. #101 value7 The data input DX1G is selected. #110 value8 The data input is always 1. #111 DCEN Delay Compensation Enable 3 3 read-write value1 The receive shift clock is dependent on INSW selection. #0 value2 The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. #1 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DX1T. #01 value3 A falling edge activates DX1T. #10 value4 Both edges activate DX1T. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DX1S is 0. #0 value2 The current value of DX1S is 1. #1 DX2CR Input Control Register 2 0x024 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DXnA is selected. #000 value2 The data input DXnB is selected. #001 value3 The data input DXnC is selected. #010 value4 The data input DXnD is selected. #011 value5 The data input DXnE is selected. #100 value6 The data input DXnF is selected. #101 value7 The data input DXnG is selected. #110 value8 The data input is always 1. #111 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DXnT. #01 value3 A falling edge activates DXnT. #10 value4 Both edges activate DXnT. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DXnS is 0. #0 value2 The current value of DXnS is 1. #1 DX3CR Input Control Register 3 0x028 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DXnA is selected. #000 value2 The data input DXnB is selected. #001 value3 The data input DXnC is selected. #010 value4 The data input DXnD is selected. #011 value5 The data input DXnE is selected. #100 value6 The data input DXnF is selected. #101 value7 The data input DXnG is selected. #110 value8 The data input is always 1. #111 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DXnT. #01 value3 A falling edge activates DXnT. #10 value4 Both edges activate DXnT. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DXnS is 0. #0 value2 The current value of DXnS is 1. #1 DX4CR Input Control Register 4 0x02C 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DXnA is selected. #000 value2 The data input DXnB is selected. #001 value3 The data input DXnC is selected. #010 value4 The data input DXnD is selected. #011 value5 The data input DXnE is selected. #100 value6 The data input DXnF is selected. #101 value7 The data input DXnG is selected. #110 value8 The data input is always 1. #111 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DXnT. #01 value3 A falling edge activates DXnT. #10 value4 Both edges activate DXnT. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DXnS is 0. #0 value2 The current value of DXnS is 1. #1 DX5CR Input Control Register 5 0x030 32 0x00000000 0xFFFFFFFF DSEL Data Selection for Input Signal 0 2 read-write value1 The data input DXnA is selected. #000 value2 The data input DXnB is selected. #001 value3 The data input DXnC is selected. #010 value4 The data input DXnD is selected. #011 value5 The data input DXnE is selected. #100 value6 The data input DXnF is selected. #101 value7 The data input DXnG is selected. #110 value8 The data input is always 1. #111 INSW Input Switch 4 4 read-write value1 The input of the data shift unit is controlled by the protocol pre-processor. #0 value2 The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. #1 DFEN Digital Filter Enable 5 5 read-write value1 The input signal is not digitally filtered. #0 value2 The input signal is digitally filtered. #1 DSEN Data Synchronization Enable 6 6 read-write value1 The un-synchronized signal can be taken as input for the data shift unit. #0 value2 The synchronized signal can be taken as input for the data shift unit. #1 DPOL Data Polarity for DXn 8 8 read-write value1 The input signal is not inverted. #0 value2 The input signal is inverted. #1 SFSEL Sampling Frequency Selection 9 9 read-write value1 The sampling frequency is fPERIPH. #0 value2 The sampling frequency is fFD. #1 CM Combination Mode 10 11 read-write value1 The trigger activation is disabled. #00 value2 A rising edge activates DXnT. #01 value3 A falling edge activates DXnT. #10 value4 Both edges activate DXnT. #11 DXS Synchronized Data Value 15 15 read-only value1 The current value of DXnS is 0. #0 value2 The current value of DXnS is 1. #1 SCTR Shift Control Register 0x034 32 0x00000000 0xFFFFFFFF SDIR Shift Direction 0 0 read-write value1 Shift LSB first. The first data bit of a data word is located at bit position 0. #0 value2 Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE. #1 PDL Passive Data Level 1 1 read-write value1 The passive data level is 0. #0 value2 The passive data level is 1. #1 DSM Data Shift Mode 2 3 read-write value1 Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. #00 value3 Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. #10 value4 Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. #11 HPCDIR Port Control Direction 4 4 read-write value1 The pin(s) with hardware pin control enabled are selected to be in input mode. #0 value2 The pin(s) with hardware pin control enabled are selected to be in output mode. #1 DOCFG Data Output Configuration 6 7 read-write value1 DOUTx = shift data value #00 value2 DOUTx = inverted shift data value #01 TRM Transmission Mode 8 9 read-write value1 The shift control signal is considered as inactive and data frame transfers are not possible. #00 value2 The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. #01 value3 The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. #10 value4 The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. #11 FLE Frame Length 16 21 read-write WLE Word Length 24 27 read-write value1 The data word contains 1 data bit located at bit position 0. 0x0 value2 The data word contains 2 data bits located at bit positions [1:0]. 0x1 value3 The data word contains 15 data bits located at bit positions [14:0]. 0xE value4 The data word contains 16 data bits located at bit positions [15:0]. 0xF TCSR Transmit Control/Status Register 0x038 32 0x00000000 0xFFFFFFFF WLEMD WLE Mode 0 0 read-write value1 The automatic update of SCTR.WLE and TCSR.EOF is disabled. #0 value2 The automatic update of SCTR.WLE and TCSR.EOF is enabled. #1 SELMD Select Mode 1 1 read-write value1 The automatic update of PCR.CTR[23:16] is disabled. #0 value2 The automatic update of PCR.CTR[23:16] is disabled. #1 FLEMD FLE Mode 2 2 read-write value1 The automatic update of FLE is disabled. #0 value2 The automatic update of FLE is enabled. #1 WAMD WA Mode 3 3 read-write value1 The automatic update of bit WA is disabled. #0 value2 The automatic update of bit WA is enabled. #1 HPCMD Hardware Port Control Mode 4 4 read-write value1 The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled. #0 value2 The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled. #1 SOF Start Of Frame 5 5 read-write value1 The data word in TBUF is not considered as first word of a frame. #0 value2 The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). #1 EOF End Of Frame 6 6 read-write value1 The data word in TBUF is not considered as last word of an SSC frame. #0 value2 The data word in TBUF is considered as last word of an SSC frame. #1 TDV Transmit Data Valid 7 7 read-only value1 The data word in TBUF is not valid for transmission. #0 value2 The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. #1 TDSSM TBUF Data Single Shot Mode 8 8 read-write value1 The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. #0 value2 The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. #1 TDEN TBUF Data Enable 10 11 read-write value1 A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. #00 value2 A transmission of the data word in TBUF can be started if TDV = 1. #01 value3 A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. #10 value4 A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. #11 TDVTR TBUF Data Valid Trigger 12 12 read-write value1 Bit TCSR.TE is permanently set. #0 value2 Bit TCSR.TE is set if DX2T becomes active while TDV = 1. #1 WA Word Address 13 13 read-write value1 The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA). #0 value2 The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA). #1 TSOF Transmitted Start Of Frame 24 24 read-only value1 The latest data word transmission has not been started for the first word of a data frame. #0 value2 The latest data word transmission has been started for the first word of a data frame. #1 TV Transmission Valid 26 26 read-only value1 The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. #0 value2 The latest start of a data word transmission has taken place with valid data from TBUF. #1 TVC Transmission Valid Cumulated 27 27 read-only value1 Since TVC has been set, at least one data buffer underflow condition has occurred. #0 value2 Since TVC has been set, no data buffer underflow condition has occurred. #1 TE Trigger Event 28 28 read-only value1 The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started. #0 value2 The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can be started. #1 PCR Protocol Control Register 0x03C 32 0x00000000 0xFFFFFFFF CTR0 Protocol Control Bit 0 0 0 read-write CTR1 Protocol Control Bit 1 1 1 read-write CTR2 Protocol Control Bit 2 2 2 read-write CTR3 Protocol Control Bit 3 3 3 read-write CTR4 Protocol Control Bit 4 4 4 read-write CTR5 Protocol Control Bit 5 5 5 read-write CTR6 Protocol Control Bit 6 6 6 read-write CTR7 Protocol Control Bit 7 7 7 read-write CTR8 Protocol Control Bit 8 8 8 read-write CTR9 Protocol Control Bit 9 9 9 read-write CTR10 Protocol Control Bit 10 10 10 read-write CTR11 Protocol Control Bit 11 11 11 read-write CTR12 Protocol Control Bit 12 12 12 read-write CTR13 Protocol Control Bit 13 13 13 read-write CTR14 Protocol Control Bit 14 14 14 read-write CTR15 Protocol Control Bit 15 15 15 read-write CTR16 Protocol Control Bit 16 16 16 read-write CTR17 Protocol Control Bit 17 17 17 read-write CTR18 Protocol Control Bit 18 18 18 read-write CTR19 Protocol Control Bit 19 19 19 read-write CTR20 Protocol Control Bit 20 20 20 read-write CTR21 Protocol Control Bit 21 21 21 read-write CTR22 Protocol Control Bit 22 22 22 read-write CTR23 Protocol Control Bit 23 23 23 read-write CTR24 Protocol Control Bit 24 24 24 read-write CTR25 Protocol Control Bit 25 25 25 read-write CTR26 Protocol Control Bit 26 26 26 read-write CTR27 Protocol Control Bit 27 27 27 read-write CTR28 Protocol Control Bit 28 28 28 read-write CTR29 Protocol Control Bit 29 29 29 read-write CTR30 Protocol Control Bit 30 30 30 read-write CTR31 Protocol Control Bit 31 31 31 read-write PCR_ASCMode Protocol Control Register [ASC Mode] PCR 0x03C 32 0x00000000 0xFFFFFFFF SMD Sample Mode 0 0 read-write value1 Only one sample is taken per bit time. The current input value is sampled. #0 value2 Three samples are taken per bit time and a majority decision is made. #1 STPB Stop Bits 1 1 read-write value1 The number of stop bits is 1. #0 value2 The number of stop bits is 2. #1 IDM Idle Detection Mode 2 2 read-write value1 The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. #0 value2 The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). #1 SBIEN Synchronization Break Interrupt Enable 3 3 read-write value1 The interrupt generation is disabled. #0 value2 The interrupt generation is enabled. #1 CDEN Collision Detection Enable 4 4 read-write value1 The collision detection is disabled. #0 value2 If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. #1 RNIEN Receiver Noise Detection Interrupt Enable 5 5 read-write value1 The interrupt generation is disabled. #0 value2 The interrupt generation is enabled. #1 FEIEN Format Error Interrupt Enable 6 6 read-write value1 The interrupt generation is disabled. #0 value2 The interrupt generation is enabled. #1 FFIEN Frame Finished Interrupt Enable 7 7 read-write value1 The interrupt generation is disabled. #0 value2 The interrupt generation is enabled. #1 SP Sample Point 8 12 read-write PL Pulse Length 13 15 read-write value1 The pulse length is equal to the bit length (no shortened 0). #000 value2 The pulse length of a 0 bit is 2 time quanta. #001 value3 The pulse length of a 0 bit is 3 time quanta. #010 value4 The pulse length of a 0 bit is 8 time quanta. #111 RSTEN Receiver Status Enable 16 16 read-write value1 Flag PSR[9] is not modified depending on the receiver status. #0 value2 Flag PSR[9] is set during the complete reception of a frame. #1 TSTEN Transmitter Status Enable 17 17 read-write value1 Flag PSR[9] is not modified depending on the transmitter status. #0 value2 Flag PSR[9] is set during the complete transmission of a frame. #1 MCLK Master Clock Enable 31 31 read-write value1 The MCLK generation is disabled and the MCLK signal is 0. #0 value2 The MCLK generation is enabled. #1 PCR_SSCMode Protocol Control Register [SSC Mode] PCR 0x03C 32 0x00000000 0xFFFFFFFF MSLSEN MSLS Enable 0 0 read-write value1 The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. #0 value2 The MSLS generation is enabled. This is the setting for SSC master mode. #1 SELCTR Select Control 1 1 read-write value1 The coded select mode is enabled. #0 value2 The direct select mode is enabled. #1 SELINV Select Inversion 2 2 read-write value1 The SELO outputs have the same polarity as the MSLS signal (active high). #0 value2 The SELO outputs have the inverted polarity to the MSLS signal (active low). #1 FEM Frame End Mode 3 3 read-write value1 The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). #0 value2 The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. #1 CTQSEL1 Input Frequency Selection 4 5 read-write value1 fCTQIN = fPDIV #00 value2 fCTQIN = fPPP #01 value3 fCTQIN = fSCLK #10 value4 fCTQIN = fMCLK #11 PCTQ1 Divider Factor PCTQ1 for Tiw and Tnf 6 7 read-write DCTQ1 Divider Factor DCTQ1 for Tiw and Tnf 8 12 read-write PARIEN Parity Error Interrupt Enable 13 13 read-write value1 A protocol interrupt is not generated with the detection of a parity error. #0 value2 A protocol interrupt is generated with the detection of a parity error. #1 MSLSIEN MSLS Interrupt Enable 14 14 read-write value1 A protocol interrupt is not generated if a change of signal MSLS is detected. #0 value2 A protocol interrupt is generated if a change of signal MSLS is detected. #1 DX2TIEN DX2T Interrupt Enable 15 15 read-write value1 A protocol interrupt is not generated if DX2T is activated. #0 value2 A protocol interrupt is generated if DX2T is activated. #1 SELO Select Output 16 23 read-write value1 The corresponding SELOx line cannot be activated. #0 value2 The corresponding SELOx line can be activated (according to the mode selected by SELCTR). #1 TIWEN Enable Inter-Word Delay Tiw 24 24 read-write value1 No delay between data words of the same frame. #0 value2 The inter-word delay Tiw is enabled and introduced between data words of the same frame. #1 SLPHSEL Slave Mode Clock Phase Select 25 25 read-write value1 Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. #0 value2 The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge. #1 MCLK Master Clock Enable 31 31 read-write value1 The MCLK generation is disabled and output MCLK = 0. #0 value2 The MCLK generation is enabled. #1 PCR_IICMode Protocol Control Register [IIC Mode] PCR 0x03C 32 0x00000000 0xFFFFFFFF SLAD Slave Address 0 15 read-write ACK00 Acknowledge 00H 16 16 read-write value1 The slave device is not sensitive to this address. #0 value2 The slave device is sensitive to this address. #1 STIM Symbol Timing 17 17 read-write value1 A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud). #0 value2 A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud). #1 SCRIEN Start Condition Received Interrupt Enable 18 18 read-write value1 The start condition interrupt is disabled. #0 value2 The start condition interrupt is enabled. #1 RSCRIEN Repeated Start Condition Received Interrupt Enable 19 19 read-write value1 The repeated start condition interrupt is disabled. #0 value2 The repeated start condition interrupt is enabled. #1 PCRIEN Stop Condition Received Interrupt Enable 20 20 read-write value1 The stop condition interrupt is disabled. #0 value2 The stop condition interrupt is enabled. #1 NACKIEN Non-Acknowledge Interrupt Enable 21 21 read-write value1 The non-acknowledge interrupt is disabled. #0 value2 The non-acknowledge interrupt is enabled. #1 ARLIEN Arbitration Lost Interrupt Enable 22 22 read-write value1 The arbitration lost interrupt is disabled. #0 value2 The arbitration lost interrupt is enabled. #1 SRRIEN Slave Read Request Interrupt Enable 23 23 read-write value1 The slave read request interrupt is disabled. #0 value2 The slave read request interrupt is enabled. #1 ERRIEN Error Interrupt Enable 24 24 read-write value1 The error interrupt is disabled. #0 value2 The error interrupt is enabled. #1 SACKDIS Slave Acknowledge Disable 25 25 read-write value1 The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received). #0 value2 The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped). #1 HDEL Hardware Delay 26 29 read-write ACKIEN Acknowledge Interrupt Enable 30 30 read-write value1 The acknowledge interrupt is disabled. #0 value2 The acknowledge interrupt is enabled. #1 MCLK Master Clock Enable 31 31 read-write value1 The MCLK generation is disabled and MCLK is 0. #0 value2 The MCLK generation is enabled. #1 PCR_IISMode Protocol Control Register [IIS Mode] PCR 0x03C 32 0x00000000 0xFFFFFFFF WAGEN WA Generation Enable 0 0 read-write value1 The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. #0 value2 The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. #1 DTEN Data Transfers Enable 1 1 read-write value1 The changes of the WA input signal are ignored and no transfers take place. #0 value2 Transfers are enabled. #1 SELINV Select Inversion 2 2 read-write value1 The SELOx outputs have the same polarity as the WA signal. #0 value2 The SELOx outputs have the inverted polarity to the WA signal. #1 WAFEIEN WA Falling Edge Interrupt Enable 4 4 read-write value1 A protocol interrupt is not activated if a falling edge of WA is generated. #0 value2 A protocol interrupt is activated if a falling edge of WA is generated. #1 WAREIEN WA Rising Edge Interrupt Enable 5 5 read-write value1 A protocol interrupt is not activated if a rising edge of WA is generated. #0 value2 A protocol interrupt is activated if a rising edge of WA is generated. #1 ENDIEN END Interrupt Enable 6 6 read-write value1 A protocol interrupt is not activated. #0 value2 A protocol interrupt is activated. #1 DX2TIEN DX2T Interrupt Enable 15 15 read-write value1 A protocol interrupt is not generated if DX2T is active. #0 value2 A protocol interrupt is generated if DX2T is active. #1 TDEL Transfer Delay 16 21 read-write MCLK Master Clock Enable 31 31 read-write value1 The MCLK generation is disabled and MCLK is 0. #0 value2 The MCLK generation is enabled. #1 CCR Channel Control Register 0x040 32 0x00000000 0xFFFFFFFF MODE Operating Mode 0 3 read-write value1 The USIC channel is disabled. All protocol-related state machines are set to an idle state. 0x0 value2 The SSC (SPI) protocol is selected. 0x1 value3 The ASC (SCI, UART) protocol is selected. 0x2 value4 The IIS protocol is selected. 0x3 value5 The IIC protocol is selected. 0x4 HPCEN Hardware Port Control Enable 6 7 read-write value1 The hardware port control is disabled. #00 value2 The hardware port control is enabled for DX0 and DOUT0. #01 value3 The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. #10 value4 The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. #11 PM Parity Mode 8 9 read-write value1 The parity generation is disabled. #00 value3 Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). #10 value4 Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). #11 RSIEN Receiver Start Interrupt Enable 10 10 read-write value1 The receiver start interrupt is disabled. #0 value2 The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. #1 DLIEN Data Lost Interrupt Enable 11 11 read-write value1 The data lost interrupt is disabled. #0 value2 The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated. #1 TSIEN Transmit Shift Interrupt Enable 12 12 read-write value1 The transmit shift interrupt is disabled. #0 value2 The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. #1 TBIEN Transmit Buffer Interrupt Enable 13 13 read-write value1 The transmit buffer interrupt is disabled. #0 value2 The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. #1 RIEN Receive Interrupt Enable 14 14 read-write value1 The receive interrupt is disabled. #0 value2 The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. #1 AIEN Alternative Receive Interrupt Enable 15 15 read-write value1 The alternative receive interrupt is disabled. #0 value2 The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. #1 BRGIEN Baud Rate Generator Interrupt Enable 16 16 read-write value1 The baud rate generator interrupt is disabled. #0 value2 The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. #1 CMTR Capture Mode Timer Register 0x044 32 0x00000000 0xFFFFFFFF CTV Captured Timer Value 0 9 read-write PSR Protocol Status Register 0x048 32 0x00000000 0xFFFFFFFF ST0 Protocol Status Flag 0 0 0 read-write ST1 Protocol Status Flag 1 1 1 read-write ST2 Protocol Status Flag 2 2 2 read-write ST3 Protocol Status Flag 3 3 3 read-write ST4 Protocol Status Flag 4 4 4 read-write ST5 Protocol Status Flag 5 5 5 read-write ST6 Protocol Status Flag 6 6 6 read-write ST7 Protocol Status Flag 7 7 7 read-write ST8 Protocol Status Flag 8 8 8 read-write ST9 Protocol Status Flag 9 9 9 read-write RSIF Receiver Start Indication Flag 10 10 read-write value1 A receiver start event has not occurred. #0 value2 A receiver start event has occurred. #1 DLIF Data Lost Indication Flag 11 11 read-write value1 A data lost event has not occurred. #0 value2 A data lost event has occurred. #1 TSIF Transmit Shift Indication Flag 12 12 read-write value1 A transmit shift event has not occurred. #0 value2 A transmit shift event has occurred. #1 TBIF Transmit Buffer Indication Flag 13 13 read-write value1 A transmit buffer event has not occurred. #0 value2 A transmit buffer event has occurred. #1 RIF Receive Indication Flag 14 14 read-write value1 A receive event has not occurred. #0 value2 A receive event has occurred. #1 AIF Alternative Receive Indication Flag 15 15 read-write value1 An alternative receive event has not occurred. #0 value2 An alternative receive event has occurred. #1 BRGIF Baud Rate Generator Indication Flag 16 16 read-write value1 A baud rate generator event has not occurred. #0 value2 A baud rate generator event has occurred. #1 PSR_ASCMode Protocol Status Register [ASC Mode] PSR 0x048 32 0x00000000 0xFFFFFFFF TXIDLE Transmission Idle 0 0 read-write value1 The transmitter line has not yet been idle. #0 value2 The transmitter line has been idle and frame transmission is possible. #1 RXIDLE Reception Idle 1 1 read-write value1 The receiver line has not yet been idle. #0 value2 The receiver line has been idle and frame reception is possible. #1 SBD Synchronization Break Detected 2 2 read-write value1 A synchronization break has not yet been detected. #0 value2 A synchronization break has been detected. #1 COL Collision Detected 3 3 read-write value1 A collision has not yet been detected and frame transmission is possible. #0 value2 A collision has been detected and frame transmission is not possible. #1 RNS Receiver Noise Detected 4 4 read-write value1 Receiver noise has not been detected. #0 value2 Receiver noise has been detected. #1 FER0 Format Error in Stop Bit 0 5 5 read-write value1 A format error 0 has not been detected. #0 value2 A format error 0 has been detected. #1 FER1 Format Error in Stop Bit 1 6 6 read-write value1 A format error 1 has not been detected. #0 value2 A format error 1 has been detected. #1 RFF Receive Frame Finished 7 7 read-write value1 The received frame is not yet finished. #0 value2 The received frame is finished. #1 TFF Transmitter Frame Finished 8 8 read-write value1 The transmitter frame is not yet finished. #0 value2 The transmitter frame is finished. #1 BUSY Transfer Status BUSY 9 9 read-only value1 A data transfer does not take place. #0 value2 A data transfer currently takes place. #1 RSIF Receiver Start Indication Flag 10 10 read-write value1 A receiver start event has not occurred. #0 value2 A receiver start event has occurred. #1 DLIF Data Lost Indication Flag 11 11 read-write value1 A data lost event has not occurred. #0 value2 A data lost event has occurred. #1 TSIF Transmit Shift Indication Flag 12 12 read-write value1 A transmit shift event has not occurred. #0 value2 A transmit shift event has occurred. #1 TBIF Transmit Buffer Indication Flag 13 13 read-write value1 A transmit buffer event has not occurred. #0 value2 A transmit buffer event has occurred. #1 RIF Receive Indication Flag 14 14 read-write value1 A receive event has not occurred. #0 value2 A receive event has occurred. #1 AIF Alternative Receive Indication Flag 15 15 read-write value1 An alternative receive event has not occurred. #0 value2 An alternative receive event has occurred. #1 BRGIF Baud Rate Generator Indication Flag 16 16 read-write value1 A baud rate generator event has not occurred. #0 value2 A baud rate generator event has occurred. #1 PSR_SSCMode Protocol Status Register [SSC Mode] PSR 0x048 32 0x00000000 0xFFFFFFFF MSLS MSLS Status 0 0 read-write value1 The internal signal MSLS is inactive (0). #0 value2 The internal signal MSLS is active (1). #1 DX2S DX2S Status 1 1 read-write value1 DX2S is 0. #0 value2 DX2S is 1. #1 MSLSEV MSLS Event Detected 2 2 read-write value1 The MSLS signal has not changed its state. #0 value2 The MSLS signal has changed its state. #1 DX2TEV DX2T Event Detected 3 3 read-write value1 The DX2T signal has not been activated. #0 value2 The DX2T signal has been activated. #1 PARERR Parity Error Event Detected 4 4 read-write value1 A parity error event has not been activated. #0 value2 A parity error event has been activated. #1 RSIF Receiver Start Indication Flag 10 10 read-write value1 A receiver start event has not occurred. #0 value2 A receiver start event has occurred. #1 DLIF Data Lost Indication Flag 11 11 read-write value1 A data lost event has not occurred. #0 value2 A data lost event has occurred. #1 TSIF Transmit Shift Indication Flag 12 12 read-write value1 A transmit shift event has not occurred. #0 value2 A transmit shift event has occurred. #1 TBIF Transmit Buffer Indication Flag 13 13 read-write value1 A transmit buffer event has not occurred. #0 value2 A transmit buffer event has occurred. #1 RIF Receive Indication Flag 14 14 read-write value1 A receive event has not occurred. #0 value2 A receive event has occurred. #1 AIF Alternative Receive Indication Flag 15 15 read-write value1 An alternative receive event has not occurred. #0 value2 An alternative receive event has occurred. #1 BRGIF Baud Rate Generator Indication Flag 16 16 read-write value1 A baud rate generator event has not occurred. #0 value2 A baud rate generator event has occurred. #1 PSR_IICMode Protocol Status Register [IIC Mode] PSR 0x048 32 0x00000000 0xFFFFFFFF SLSEL Slave Select 0 0 read-write value1 The device is not selected as slave. #0 value2 The device is selected as slave. #1 WTDF Wrong TDF Code Found 1 1 read-write value1 A wrong TDF code has not been found. #0 value2 A wrong TDF code has been found. #1 SCR Start Condition Received 2 2 read-write value1 A start condition has not yet been detected. #0 value2 A start condition has been detected. #1 RSCR Repeated Start Condition Received 3 3 read-write value1 A repeated start condition has not yet been detected. #0 value2 A repeated start condition has been detected. #1 PCR Stop Condition Received 4 4 read-write value1 A stop condition has not yet been detected. #0 value2 A stop condition has been detected. #1 NACK Non-Acknowledge Received 5 5 read-write value1 A non-acknowledge has not been received. #0 value2 A non-acknowledge has been received. #1 ARL Arbitration Lost 6 6 read-write value1 An arbitration has not been lost. #0 value2 An arbitration has been lost. #1 SRR Slave Read Request 7 7 read-write value1 A slave read request has not been detected. #0 value2 A slave read request has been detected. #1 ERR Error 8 8 read-write value1 An IIC error has not been detected. #0 value2 An IIC error has been detected. #1 ACK Acknowledge Received 9 9 read-write value1 An acknowledge has not been received. #0 value2 An acknowledge has been received. #1 RSIF Receiver Start Indication Flag 10 10 read-write value1 A receiver start event has not occurred. #0 value2 A receiver start event has occurred. #1 DLIF Data Lost Indication Flag 11 11 read-write value1 A data lost event has not occurred. #0 value2 A data lost event has occurred. #1 TSIF Transmit Shift Indication Flag 12 12 read-write value1 A transmit shift event has not occurred. #0 value2 A transmit shift event has occurred. #1 TBIF Transmit Buffer Indication Flag 13 13 read-write value1 A transmit buffer event has not occurred. #0 value2 A transmit buffer event has occurred. #1 RIF Receive Indication Flag 14 14 read-write value1 A receive event has not occurred. #0 value2 A receive event has occurred. #1 AIF Alternative Receive Indication Flag 15 15 read-write value1 An alternative receive event has not occurred. #0 value2 An alternative receive event has occurred. #1 BRGIF Baud Rate Generator Indication Flag 16 16 read-write value1 A baud rate generator event has not occurred. #0 value2 A baud rate generator event has occurred. #1 PSR_IISMode Protocol Status Register [IIS Mode] PSR 0x048 32 0x00000000 0xFFFFFFFF WA Word Address 0 0 read-write value1 WA has been sampled 0. #0 value2 WA has been sampled 1. #1 DX2S DX2S Status 1 1 read-write value1 DX2S is 0. #0 value2 DX2S is 1. #1 DX2TEV DX2T Event Detected 3 3 read-write value1 The DX2T signal has not been activated. #0 value2 The DX2T signal has been activated. #1 WAFE WA Falling Edge Event 4 4 read-write value1 A WA falling edge has not been generated. #0 value2 A WA falling edge has been generated. #1 WARE WA Rising Edge Event 5 5 read-write value1 A WA rising edge has not been generated. #0 value2 A WA rising edge has been generated. #1 END WA Generation End 6 6 read-write value1 The WA generation has not yet ended (if it is running and WAGEN has been cleared). #0 value2 The WA generation has ended (if it has been running). #1 RSIF Receiver Start Indication Flag 10 10 read-write value1 A receiver start event has not occurred. #0 value2 A receiver start event has occurred. #1 DLIF Data Lost Indication Flag 11 11 read-write value1 A data lost event has not occurred. #0 value2 A data lost event has occurred. #1 TSIF Transmit Shift Indication Flag 12 12 read-write value1 A transmit shift event has not occurred. #0 value2 A transmit shift event has occurred. #1 TBIF Transmit Buffer Indication Flag 13 13 read-write value1 A transmit buffer event has not occurred. #0 value2 A transmit buffer event has occurred. #1 RIF Receive Indication Flag 14 14 read-write value1 A receive event has not occurred. #0 value2 A receive event has occurred. #1 AIF Alternative Receive Indication Flag 15 15 read-write value1 An alternative receive event has not occurred. #0 value2 An alternative receive event has occurred. #1 BRGIF Baud Rate Generator Indication Flag 16 16 read-write value1 A baud rate generator event has not occurred. #0 value2 A baud rate generator event has occurred. #1 PSCR Protocol Status Clear Register 0x04C 32 0x00000000 0xFFFFFFFF CST0 Clear Status Flag 0 in PSR 0 0 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST1 Clear Status Flag 1 in PSR 1 1 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST2 Clear Status Flag 2 in PSR 2 2 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST3 Clear Status Flag 3 in PSR 3 3 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST4 Clear Status Flag 4 in PSR 4 4 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST5 Clear Status Flag 5 in PSR 5 5 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST6 Clear Status Flag 6 in PSR 6 6 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST7 Clear Status Flag 7 in PSR 7 7 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST8 Clear Status Flag 8 in PSR 8 8 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CST9 Clear Status Flag 9 in PSR 9 9 write-only value1 No action #0 value2 Flag PSR.STx is cleared. #1 CRSIF Clear Receiver Start Indication Flag 10 10 write-only value1 No action #0 value2 Flag PSR.RSIF is cleared. #1 CDLIF Clear Data Lost Indication Flag 11 11 write-only value1 No action #0 value2 Flag PSR.DLIF is cleared. #1 CTSIF Clear Transmit Shift Indication Flag 12 12 write-only value1 No action #0 value2 Flag PSR.TSIF is cleared. #1 CTBIF Clear Transmit Buffer Indication Flag 13 13 write-only value1 No action #0 value2 Flag PSR.TBIF is cleared. #1 CRIF Clear Receive Indication Flag 14 14 write-only value1 No action #0 value2 Flag PSR.RIF is cleared. #1 CAIF Clear Alternative Receive Indication Flag 15 15 write-only value1 No action #0 value2 Flag PSR.AIF is cleared. #1 CBRGIF Clear Baud Rate Generator Indication Flag 16 16 write-only value1 No action #0 value2 Flag PSR.BRGIF is cleared. #1 RBUFSR Receiver Buffer Status Register 0x050 32 0x00000000 0xFFFFFFFF WLEN Received Data Word Length in RBUF or RBUFD 0 3 read-only SOF Start of Frame in RBUF or RBUFD 6 6 read-only PAR Protocol-Related Argument in RBUF or RBUFD 8 8 read-only PERR Protocol-related Error in RBUF or RBUFD 9 9 read-only RDV0 Receive Data Valid in RBUF or RBUFD 13 13 read-only RDV1 Receive Data Valid in RBUF or RBUFD 14 14 read-only DS Data Source of RBUF or RBUFD 15 15 read-only RBUF Receiver Buffer Register 0x054 32 0x00000000 0xFFFFFFFF modifyExternal DSR Received Data 0 15 read-only RBUFD Receiver Buffer Register for Debugger 0x058 32 0x00000000 0xFFFFFFFF DSR Data from Shift Register 0 15 read-only RBUF0 Receiver Buffer Register 0 0x05C 32 0x00000000 0xFFFFFFFF DSR0 Data of Shift Registers 0[3:0] 0 15 read-only RBUF1 Receiver Buffer Register 1 0x060 32 0x00000000 0xFFFFFFFF DSR1 Data of Shift Registers 1[3:0] 0 15 read-only RBUF01SR Receiver Buffer 01 Status Register 0x064 32 0x00000000 0xFFFFFFFF WLEN0 Received Data Word Length in RBUF0 0 3 read-only SOF0 Start of Frame in RBUF0 6 6 read-only value1 The data in RBUF0 has not been the first data word of a data frame. #0 value2 The data in RBUF0 has been the first data word of a data frame. #1 PAR0 Protocol-Related Argument in RBUF0 8 8 read-only PERR0 Protocol-related Error in RBUF0 9 9 read-only value1 The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. #0 value2 The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. #1 RDV00 Receive Data Valid in RBUF0 13 13 read-only value1 Register RBUF0 does not contain data that has not yet been read out. #0 value2 Register RBUF0 contains data that has not yet been read out. #1 RDV01 Receive Data Valid in RBUF1 14 14 read-only value1 Register RBUF1 does not contain data that has not yet been read out. #0 value2 Register RBUF1 contains data that has not yet been read out. #1 DS0 Data Source 15 15 read-only value1 The register RBUF contains the data of RBUF0 (same for associated status information). #0 value2 The register RBUF contains the data of RBUF1 (same for associated status information). #1 WLEN1 Received Data Word Length in RBUF1 16 19 read-only SOF1 Start of Frame in RBUF1 22 22 read-only value1 The data in RBUF1 has not been the first data word of a data frame. #0 value2 The data in RBUF1 has been the first data word of a data frame. #1 PAR1 Protocol-Related Argument in RBUF1 24 24 read-only PERR1 Protocol-related Error in RBUF1 25 25 read-only value1 The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. #0 value2 The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. #1 RDV10 Receive Data Valid in RBUF0 29 29 read-only value1 Register RBUF0 does not contain data that has not yet been read out. #0 value2 Register RBUF0 contains data that has not yet been read out. #1 RDV11 Receive Data Valid in RBUF1 30 30 read-only value1 Register RBUF1 does not contain data that has not yet been read out. #0 value2 Register RBUF1 contains data that has not yet been read out. #1 DS1 Data Source 31 31 read-only value1 The register RBUF contains the data of RBUF0 (same for associated status information). #0 value2 The register RBUF contains the data of RBUF1 (same for associated status information). #1 FMR Flag Modification Register 0x068 32 0x00000000 0xFFFFFFFF MTDV Modify Transmit Data Valid 0 1 write-only value1 No action. #00 value2 Bit TDV is set, TE is unchanged. #01 value3 Bits TDV and TE are cleared. #10 ATVC Activate Bit TVC 4 4 write-only value1 No action. #0 value2 Bit TCSR.TVC is set. #1 CRDV0 Clear Bits RDV for RBUF0 14 14 write-only value1 No action. #0 value2 Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. #1 CRDV1 Clear Bit RDV for RBUF1 15 15 write-only value1 No action. #0 value2 Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. #1 SIO0 Set Interrupt Output SRx 16 16 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 SIO1 Set Interrupt Output SRx 17 17 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 SIO2 Set Interrupt Output SRx 18 18 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 SIO3 Set Interrupt Output SRx 19 19 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 SIO4 Set Interrupt Output SRx 20 20 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 SIO5 Set Interrupt Output SRx 21 21 write-only value1 No action. #0 value2 The service request output SRx is activated. #1 32 4 TBUF[%s] Transmit Buffer 0x080 32 0x00000000 0xFFFFFFFF TDATA Transmit Data 0 15 read-write BYP Bypass Data Register 0x100 32 0x00000000 0xFFFFFFFF BDATA Bypass Data 0 15 read-write BYPCR Bypass Control Register 0x104 32 0x00000000 0xFFFFFFFF BWLE Bypass Word Length 0 3 read-write BDSSM Bypass Data Single Shot Mode 8 8 read-write value1 The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. #0 value2 The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV. #1 BDEN Bypass Data Enable 10 11 read-write value1 The transfer of bypass data is disabled. #00 value2 The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. #01 value3 Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. #10 value4 Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. #11 BDVTR Bypass Data Valid Trigger 12 12 read-write value1 Bit BDV is not influenced by DX2T. #0 value2 Bit BDV is set if DX2T is active. #1 BPRIO Bypass Priority 13 13 read-write value1 The transmit FIFO data has a higher priority than the bypass data. #0 value2 The bypass data has a higher priority than the transmit FIFO data. #1 BDV Bypass Data Valid 15 15 read-only value1 The bypass data is not valid. #0 value2 The bypass data is valid. #1 BSELO Bypass Select Outputs 16 20 read-write BHPC Bypass Hardware Port Control 21 23 read-write TBCTR Transmitter Buffer Control Register 0x108 32 0x00000000 0xFFFFFFFF DPTR Data Pointer 0 5 write-only LIMIT Limit For Interrupt Generation 8 13 read-write STBTM Standard Transmit Buffer Trigger Mode 14 14 read-write value1 Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. #0 value2 Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. #1 STBTEN Standard Transmit Buffer Trigger Enable 15 15 read-write value1 The standard transmit buffer event trigger through bit TRBSR.STBT is disabled. #0 value2 The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. #1 STBINP Standard Transmit Buffer Interrupt Node Pointer 16 18 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 ATBINP Alternative Transmit Buffer Interrupt Node Pointer 19 21 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 SIZE Buffer Size 24 26 read-write value1 The FIFO mechanism is disabled. The buffer does not accept any request for data. #000 value2 The FIFO buffer contains 2 entries. #001 value3 The FIFO buffer contains 4 entries. #010 value4 The FIFO buffer contains 8 entries. #011 value5 The FIFO buffer contains 16 entries. #100 value6 The FIFO buffer contains 32 entries. #101 value7 The FIFO buffer contains 64 entries. #110 LOF Buffer Event on Limit Overflow 28 28 read-write value1 A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word. #0 value2 A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. #1 STBIEN Standard Transmit Buffer Interrupt Enable 30 30 read-write value1 The standard transmit buffer interrupt generation is disabled. #0 value2 The standard transmit buffer interrupt generation is enabled. #1 TBERIEN Transmit Buffer Error Interrupt Enable 31 31 read-write value1 The transmit buffer error interrupt generation is disabled. #0 value2 The transmit buffer error interrupt generation is enabled. #1 RBCTR Receiver Buffer Control Register 0x10C 32 0x00000000 0xFFFFFFFF DPTR Data Pointer 0 5 write-only LIMIT Limit For Interrupt Generation 8 13 read-write SRBTM Standard Receive Buffer Trigger Mode 14 14 read-write value1 Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. #0 value2 Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. #1 SRBTEN Standard Receive Buffer Trigger Enable 15 15 read-write value1 The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. #0 value2 The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. #1 SRBINP Standard Receive Buffer Interrupt Node Pointer 16 18 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 ARBINP Alternative Receive Buffer Interrupt Node Pointer 19 21 read-write value1 Output SR0 becomes activated. #000 value2 Output SR1 becomes activated. #001 value3 Output SR2 becomes activated. #010 value4 Output SR3 becomes activated. #011 value5 Output SR4 becomes activated. #100 value6 Output SR5 becomes activated. #101 RCIM Receiver Control Information Mode 22 23 read-write value1 RCI[4] = PERR, RCI[3:0] = WLEN #00 value2 RCI[4] = SOF, RCI[3:0] = WLEN #01 value3 RCI[4] = 0, RCI[3:0] = WLEN #10 value4 RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF #11 SIZE Buffer Size 24 26 read-write value1 The FIFO mechanism is disabled. The buffer does not accept any request for data. #000 value2 The FIFO buffer contains 2 entries. #001 value3 The FIFO buffer contains 4 entries. #010 value4 The FIFO buffer contains 8 entries. #011 value5 The FIFO buffer contains 16 entries. #100 value6 The FIFO buffer contains 32 entries. #101 value7 The FIFO buffer contains 64 entries. #110 RNM Receiver Notification Mode 27 27 read-write value1 Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). #0 value2 RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. #1 LOF Buffer Event on Limit Overflow 28 28 read-write value1 A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. #0 value2 A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. #1 ARBIEN Alternative Receive Buffer Interrupt Enable 29 29 read-write value1 The alternative receive buffer interrupt generation is disabled. #0 value2 The alternative receive buffer interrupt generation is enabled. #1 SRBIEN Standard Receive Buffer Interrupt Enable 30 30 read-write value1 The standard receive buffer interrupt generation is disabled. #0 value2 The standard receive buffer interrupt generation is enabled. #1 RBERIEN Receive Buffer Error Interrupt Enable 31 31 read-write value1 The receive buffer error interrupt generation is disabled. #0 value2 The receive buffer error interrupt generation is enabled. #1 TRBPTR Transmit/Receive Buffer Pointer Register 0x110 32 0x00000000 0xFFFFFFFF TDIPTR Transmitter Data Input Pointer 0 5 read-only TDOPTR Transmitter Data Output Pointer 8 13 read-only RDIPTR Receiver Data Input Pointer 16 21 read-only RDOPTR Receiver Data Output Pointer 24 29 read-only TRBSR Transmit/Receive Buffer Status Register 0x114 32 0x00000808 0xFFFFFFFF SRBI Standard Receive Buffer Event 0 0 read-write value1 A standard receive buffer event has not been detected. #0 value2 A standard receive buffer event has been detected. #1 RBERI Receive Buffer Error Event 1 1 read-write value1 A receive buffer error event has not been detected. #0 value2 A receive buffer error event has been detected. #1 ARBI Alternative Receive Buffer Event 2 2 read-write value1 An alternative receive buffer event has not been detected. #0 value2 An alternative receive buffer event has been detected. #1 REMPTY Receive Buffer Empty 3 3 read-only value1 The receive buffer is not empty. #0 value2 The receive buffer is empty. #1 RFULL Receive Buffer Full 4 4 read-only value1 The receive buffer is not full. #0 value2 The receive buffer is full. #1 RBUS Receive Buffer Busy 5 5 read-only value1 The receive buffer information has been completely updated. #0 value2 The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. #1 SRBT Standard Receive Buffer Event Trigger 6 6 read-only value1 A standard receive buffer event is not triggered using this bit. #0 value2 A standard receive buffer event is triggered using this bit. #1 STBI Standard Transmit Buffer Event 8 8 read-write value1 A standard transmit buffer event has not been detected. #0 value2 A standard transmit buffer event has been detected. #1 TBERI Transmit Buffer Error Event 9 9 read-write value1 A transmit buffer error event has not been detected. #0 value2 A transmit buffer error event has been detected. #1 TEMPTY Transmit Buffer Empty 11 11 read-only value1 The transmit buffer is not empty. #0 value2 The transmit buffer is empty. #1 TFULL Transmit Buffer Full 12 12 read-only value1 The transmit buffer is not full. #0 value2 The transmit buffer is full. #1 TBUS Transmit Buffer Busy 13 13 read-only value1 The transmit buffer information has been completely updated. #0 value2 The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. #1 STBT Standard Transmit Buffer Event Trigger 14 14 read-only value1 A standard transmit buffer event is not triggered using this bit. #0 value2 A standard transmit buffer event is triggered using this bit. #1 RBFLVL Receive Buffer Filling Level 16 22 read-only TBFLVL Transmit Buffer Filling Level 24 30 read-only TRBSCR Transmit/Receive Buffer Status Clear Register 0x118 32 0x00000000 0xFFFFFFFF CSRBI Clear Standard Receive Buffer Event 0 0 write-only value1 No effect. #0 value2 Clear TRBSR.SRBI. #1 CRBERI Clear Receive Buffer Error Event 1 1 write-only value1 No effect. #0 value2 Clear TRBSR.RBERI. #1 CARBI Clear Alternative Receive Buffer Event 2 2 write-only value1 No effect. #0 value2 Clear TRBSR.ARBI. #1 CSTBI Clear Standard Transmit Buffer Event 8 8 write-only value1 No effect. #0 value2 Clear TRBSR.STBI. #1 CTBERI Clear Transmit Buffer Error Event 9 9 write-only value1 No effect. #0 value2 Clear TRBSR.TBERI. #1 CBDV Clear Bypass Data Valid 10 10 write-only value1 No effect. #0 value2 Clear BYPCR.BDV. #1 FLUSHRB Flush Receive Buffer 14 14 write-only value1 No effect. #0 value2 The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. #1 FLUSHTB Flush Transmit Buffer 15 15 write-only value1 No effect. #0 value2 The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. #1 OUTR Receiver Buffer Output Register 0x11C 32 0x00000000 0xFFFFFFFF modifyExternal DSR Received Data 0 15 read-only RCI Receiver Control Information 16 20 read-only OUTDR Receiver Buffer Output Register L for Debugger 0x120 32 0x00000000 0xFFFFFFFF DSR Data from Shift Register 0 15 read-only RCI Receive Control Information from Shift Register 16 20 read-only 32 4 IN[%s] Transmit FIFO Buffer 0x180 32 0x00000000 0xFFFFFFFF TDATA Transmit Data 0 15 write-only USIC0_CH1 Universal Serial Interface Controller 0 USIC 0x48000200 0x0 0x0200 registers SCU_GENERAL System Control Unit 0x40010000 0x0 0x200 registers DBGROMID Debug System ROM ID Register 0x0000 32 0x201ED083 0xFFFFFFFF MANUFID Manufactory Identity 1 11 read-only PARTNO Part Number 12 27 read-only VERSION Product version 28 31 read-only IDCHIP Chip ID Register 0x0004 32 0x00000000 0xFFFFFFFF IDCHIP CHIP ID 0 31 read-only ID SCU Module ID Register 0x0008 32 0x00F1C000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only SSW0 SSW Register 0 0x0014 32 0x00000000 0xFFFFFFFF DAT SSW Data 0 31 read-write PASSWD Password Register 0x0024 32 0x00000007 0xFFFFFFFF MODE Bit Protection Scheme Control Bits 0 1 read-write value1 Scheme disabled - direct access to the protected bits is allowed. #00 value2 Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default) #11 PROTS Bit Protection Signal Status Bit 2 2 read-only value1 Software is able to write to all protected bits. #0 value2 Software is unable to write to any of the protected bits. #1 PASS Password Bits 3 7 write-only value1 Enables writing of the bit field MODE. #11000 value2 Opens access to writing of all protected bits. #10011 value3 Closes access to writing of all protected bits. #10101 CCUCON CCU Control Register 0x0030 32 0x00000000 0xFFFFFFFF GSC40 Global Start Control CCU40 0 0 read-write GSC80 Global Start Control CCU80 8 8 read-write MIRRSTS Mirror Update Status Register 0x0048 32 0x00000000 0xFFFFFFFF RTC_CTR RTC CTR Mirror Register Update Status 0 0 read-only RTC_ATIM0 RTC ATIM0 Mirror Register Update Status 1 1 read-only RTC_ATIM1 RTC ATIM1 Mirror Register Update Status 2 2 read-only RTC_TIM0 RTC TIM0 Mirror Register Update Status 3 3 read-only RTC_TIM1 RTC TIM1 Mirror Register Update Status 4 4 read-only PMTSR Parity Memory Test Select Register 0x0054 32 0x00000000 0xFFFFFFFF MTENS Parity Test Enable Control for 16kbytes SRAM 0 0 read-write value1 standard operation #0 value2 generate an inverted parity bit during a write operation #1 SCU_INTERRUPT System Control Unit 0x40010038 0x0 0x010 registers SCU_0 System Control 0 SCU_1 System Control 1 SCU_2 System Control 2 SRRAW SCU Raw Service Request Status 0x0000 32 0x00000000 0xFFFFFFFF PRWARN WDT pre-warning Event Status Before Masking 0 0 read-only PI RTC Raw Periodic Event Status Before Masking 1 1 read-only AI RTC Raw Alarm Event Status Before Masking 2 2 read-only VDDPI VDDP pre-warning Event Status Before Masking 3 3 read-only ACMP0I Analog Comparator 0 Event Status Before Masking 4 4 read-only ACMP1I Analog Comparator 1 Event Status Before Masking 5 5 read-only ACMP2I Analog Comparator 2 Event Status Before Masking 6 6 read-only VDROPI VDROP Event Status Before Masking 7 7 read-only ORC0I Out of Range Comparator X Event Status Before Masking 8 8 read-only ORC1I Out of Range Comparator X Event Status Before Masking 9 9 read-only ORC2I Out of Range Comparator X Event Status Before Masking 10 10 read-only ORC3I Out of Range Comparator X Event Status Before Masking 11 11 read-only ORC4I Out of Range Comparator X Event Status Before Masking 12 12 read-only ORC5I Out of Range Comparator X Event Status Before Masking 13 13 read-only ORC6I Out of Range Comparator X Event Status Before Masking 14 14 read-only ORC7I Out of Range Comparator X Event Status Before Masking 15 15 read-only LOCI Loss of Clock Event Status Before Masking 16 16 read-only PESRAMI 16kbytes SRAM Parity Error Event Status Before Masking 17 17 read-only PEU0I USIC0 SRAM Parity Error Event Status Before Masking 18 18 read-only FLECC2I Flash Double Bit ECC Event Status Before Masking 19 19 read-only FLCMPLTI Flash Operation Complete Event Status Before Masking 20 20 read-only VCLIPI VCLIP Event Status Before Masking 21 21 read-only SBYCLKFI Standby Clock Failure Event Status Before Masking 22 22 read-only RTC_CTR RTC CTR Mirror Register Update Status Before Masking 24 24 read-only RTC_ATIM0 RTC ATIM0 Mirror Register Update Status Before Masking 25 25 read-only RTC_ATIM1 RTC ATIM1 Mirror Register Update Status Before Masking 26 26 read-only RTC_TIM0 RTC TIM0 Mirror Register Update Before Masking 27 27 read-only RTC_TIM1 RTC TIM1 Mirror Register Update Status Before Masking 28 28 read-only TSE_DONE TSE Measurement Done Event Status Before Masking 29 29 read-only TSE_HIGH TSE Compare High Temperature Event Status Before Masking 30 30 read-only TSE_LOW TSE Compare Low Temperature Event Status Before Masking 31 31 read-only SRMSK SCU Service Request Mask 0x0004 32 0x00000000 0xFFFFFFFF PRWARN WDT pre-warning Interrupt Mask 0 0 read-write VDDPI VDDP pre-warning Interrupt Mask 3 3 read-write ACMP0I Analog Comparator 0 Interrupt Mask 4 4 read-write ACMP1I Analog Comparator 1 Interrupt Mask 5 5 read-write ACMP2I Analog Comparator 2 Interrupt Mask 6 6 read-write VDROPI VDROP Interrupt Mask 7 7 read-write ORC0I Out of Range Comparator X Interrupt Mask 8 8 read-write ORC1I Out of Range Comparator X Interrupt Mask 9 9 read-write ORC2I Out of Range Comparator X Interrupt Mask 10 10 read-write ORC3I Out of Range Comparator X Interrupt Mask 11 11 read-write ORC4I Out of Range Comparator X Interrupt Mask 12 12 read-write ORC5I Out of Range Comparator X Interrupt Mask 13 13 read-write ORC6I Out of Range Comparator X Interrupt Mask 14 14 read-write ORC7I Out of Range Comparator X Interrupt Mask 15 15 read-write LOCI Loss of Clock Interrupt Mask 16 16 read-write PESRAMI 16kbytes SRAM Parity Error Interrupt Mask 17 17 read-write PEU0I USIC0 SRAM Parity Error Interrupt Mask 18 18 read-write FLECC2I Flash Double Bit ECC Interrupt Mask 19 19 read-write VCLIPI VCLIP Interrupt Mask 21 21 read-write SBYCLKFI Standby Clock Failure Interrupt Mask 22 22 read-write RTC_CTR RTC CTR Mirror Register Update Mask 24 24 read-write RTC_ATIM0 RTC ATIM0 Mirror Register Update Mask 25 25 read-write RTC_ATIM1 RTC ATIM1 Mirror Register Update Mask 26 26 read-write RTC_TIM0 RTC TIM0 Mirror Register Update Mask 27 27 read-write RTC_TIM1 RTC TIM1 Mirror Register Update Mask 28 28 read-write TSE_DONE TSE Measurement Done Interrupt Mask 29 29 read-write TSE_HIGH TSE Compare High Temperature Interrupt Mask 30 30 read-write TSE_LOW TSE Compare Low Temperature Interrupt Mask 31 31 read-write SRCLR SCU Service Request Clear 0x0008 32 0x00000000 0xFFFFFFFF PRWARN WDT pre-warning Interrupt Clear 0 0 write-only PI RTC Periodic Interrupt Clear 1 1 write-only AI RTC Alarm Interrupt Clear 2 2 write-only VDDPI VDDP pre-warning Interrupt Clear 3 3 write-only ACMP0I Analog Comparator 0 Interrupt Clear 4 4 write-only ACMP1I Analog Comparator 1 Interrupt Clear 5 5 write-only ACMP2I Analog Comparator 2 Interrupt Clear 6 6 write-only VDROPI VDROP Interrupt Clear 7 7 write-only ORC0I Out of Range Comparator X Interrupt Clear 8 8 write-only ORC1I Out of Range Comparator X Interrupt Clear 9 9 write-only ORC2I Out of Range Comparator X Interrupt Clear 10 10 write-only ORC3I Out of Range Comparator X Interrupt Clear 11 11 write-only ORC4I Out of Range Comparator X Interrupt Clear 12 12 write-only ORC5I Out of Range Comparator X Interrupt Clear 13 13 write-only ORC6I Out of Range Comparator X Interrupt Clear 14 14 write-only ORC7I Out of Range Comparator X Interrupt Clear 15 15 write-only LOCI Loss of Clock Interrupt Clear 16 16 write-only PESRAMI 16kbytes SRAM Parity Error Interrupt Clear 17 17 write-only PEU0I USIC0 SRAM Parity Error Interrupt Clear 18 18 write-only FLECC2I Flash Double Bit ECC Interrupt Clear 19 19 write-only FLCMPLTI Flash Operation Complete Interrupt Clear 20 20 write-only VCLIPI VCLIP Interrupt Clear 21 21 write-only SBYCLKFI Standby Clock Failure Interrupt Clear 22 22 write-only RTC_CTR RTC CTR Mirror Register Update Clear 24 24 write-only RTC_ATIM0 RTC ATIM0 Mirror Register Update Clear 25 25 write-only RTC_ATIM1 RTC ATIM1 Mirror Register Update Clear 26 26 write-only RTC_TIM0 RTC TIM0 Mirror Register Update Clear 27 27 write-only RTC_TIM1 RTC TIM1 Mirror Register Update Clear 28 28 write-only TSE_DONE TSE Measurement Done Interrupt Clear 29 29 write-only TSE_HIGH TSE Compare High Temperature Interrupt Clear 30 30 write-only TSE_LOW TSE Compare Low Temperature Interrupt Clear 31 31 write-only SRSET SCU Service Request Set 0x000C 32 0x00000000 0xFFFFFFFF PRWARN WDT pre-warning Interrupt Set 0 0 write-only PI RTC Periodic Interrupt Set 1 1 write-only AI RTC Alarm Interrupt Set 2 2 write-only VDDPI VDDP pre-warning Interrupt Set 3 3 write-only ACMP0I Analog Comparator 0 Interrupt Set 4 4 write-only ACMP1I Analog Comparator 1 Interrupt Set 5 5 write-only ACMP2I Analog Comparator 2 Interrupt Set 6 6 write-only VDROPI VDROP Interrupt Set 7 7 write-only ORC0I Out of Range Comparator X Interrupt Set 8 8 write-only ORC1I Out of Range Comparator X Interrupt Set 9 9 write-only ORC2I Out of Range Comparator X Interrupt Set 10 10 write-only ORC3I Out of Range Comparator X Interrupt Set 11 11 write-only ORC4I Out of Range Comparator X Interrupt Set 12 12 write-only ORC5I Out of Range Comparator X Interrupt Set 13 13 write-only ORC6I Out of Range Comparator X Interrupt Set 14 14 write-only ORC7I Out of Range Comparator X Interrupt Set 15 15 write-only LOCI Loss of Clock Interrupt Set 16 16 write-only PESRAMI 16kbytes SRAM Parity Error Interrupt Set 17 17 write-only PEU0I USIC0 SRAM Parity Error Interrupt Set 18 18 write-only FLECC2I Flash Double Bit ECC Interrupt Set 19 19 write-only FLCMPLTI Flash Operation Complete Interrupt Set 20 20 write-only VCLIPI VCLIP Interrupt Set 21 21 write-only SBYCLKFI Standby Clock Failure Interrupt Set 22 22 write-only RTC_CTR RTC CTR Mirror Register Update Set 24 24 write-only RTC_ATIM0 RTC ATIM0 Mirror Register Update Set 25 25 write-only RTC_ATIM1 RTC ATIM1 Mirror Register Update Set 26 26 write-only RTC_TIM0 RTC TIM0 Mirror Register Update Set 27 27 write-only RTC_TIM1 RTC TIM1 Mirror Register Update Set 28 28 write-only TSE_DONE TSE Measurement Done Interrupt Set 29 29 write-only TSE_HIGH TSE Compare High Temperature Interrupt Set 30 30 write-only TSE_LOW TSE Compare Low Temperature Interrupt Set 31 31 write-only SCU_POWER System Control Unit 0x40010200 0x0 0x0100 registers VDESR Voltage Detector Status Register 0x0000 32 0x00000000 0xFFFFFFFF VCLIP VCLIP Indication 0 0 read-only value1 VCLIP is not active #0 value2 VCLIP is active #1 VDDPPW VDDPPW Indication 1 1 read-only value1 VDDP is above pre-warning threshold #0 value2 VDDP is below pre-warningthreshold #1 SCU_CLK System Control Unit 0x40010300 0x0 0x100 registers CLKCR Clock Control Register 0x00 32 0x3FF00400 0xFFFFFFFF FDIV Fractional Divider Selection 0 7 read-write IDIV Divider Selection 8 15 read-write value1 Divider is bypassed. 0x00 value2 1; MCLK = 32 MHz 0x01 value3 2; MCLK = 16 MHz 0x02 value4 3; MCLK = 10.67 MHz 0x03 value5 4; MCLK = 8 MHz 0x04 value6 254; MCLK = 126 kHz 0xFE value7 255; MCLK = 125.5 kHz 0xFF PCLKSEL PCLK Clock Select 16 16 read-write value1 PCLK = MCLK #0 value2 PCLK = 2 x MCLK #1 RTCCLKSEL RTC Clock Select 17 19 read-write CNTADJ Counter Adjustment 20 29 read-write value1 1 clock cycles of the DCO1, 64MHz clock 0x000 value2 2 clock cycles of the DCO1, 64MHz clock 0x001 value3 3 clock cycles of the DCO1, 64MHz clock 0x002 value4 4 clock cycles of the DCO1, 64MHz clock 0x003 value5 5 clock cycles of the DCO1, 64MHz clock 0x004 value6 1023 clock cycles of the DCO1, 64MHz clock 0x3FE value7 1024 clock cycles of the DCO1, 64MHz clock 0x3FF VDDC2LOW VDDC too low 30 30 read-only value1 VDDC is not too low and the fractional divider input clock is running at the targeted frequency #0 value2 VDDC is too low and the fractional divider input clock is not running at the targeted frequency #1 VDDC2HIGH VDDC too high 31 31 read-only value1 VDDC is not too high #0 value2 VDDC is too high #1 PWRSVCR Power Save Control Register 0x04 32 0x00000000 0xFFFFFFFF FPD Flash Power Down 0 0 read-write value1 no effect #0 value2 Flash power down when entering power save mode. Upon wake-up, CPU is able to fetch code from flash. #1 CGATSTAT0 Peripheral 0 Clock Gating Status 0x08 32 0x000007FF 0xFFFFFFFF VADC VADC and SHS Gating Status 0 0 read-only value1 gating de-asserted #0 value2 gating asserted #1 CCU80 CCU80 Gating Status 1 1 read-only value1 gating de-asserted #0 value2 gating asserted #1 CCU40 CCU40 Gating Status 2 2 read-only value1 gating de-asserted #0 value2 gating asserted #1 USIC0 USIC0 Gating Status 3 3 read-only value1 gating de-asserted #0 value2 gating asserted #1 BCCU0 BCCU0 Gating Status 4 4 read-only value1 gating de-asserted #0 value2 gating asserted #1 POSIF0 POSIF0 Gating Status 7 7 read-only value1 gating de-asserted #0 value2 gating asserted #1 MATH MATH Gating Status 8 8 read-only value1 gating de-asserted #0 value2 gating asserted #1 WDT WDT Gating Status 9 9 read-only value1 gating de-asserted #0 value2 gating asserted #1 RTC RTC Gating Status 10 10 read-only value1 gating de-asserted #0 value2 gating asserted #1 CGATSET0 Peripheral 0 Clock Gating Set 0x0C 32 0x00000000 0xFFFFFFFF VADC VADC and SHS Gating Set 0 0 write-only value1 no effect #0 value2 enable gating #1 CCU80 CCU80 Gating Set 1 1 write-only value1 no effect #0 value2 enable gating #1 CCU40 CCU40 Gating Set 2 2 write-only value1 no effect #0 value2 enable gating #1 USIC0 USIC0 Gating Set 3 3 write-only value1 no effect #0 value2 enable gating #1 BCCU0 BCCU0 Gating Set 4 4 write-only value1 no effect #0 value2 enable gating #1 POSIF0 POSIF0 Gating Set 7 7 write-only value1 no effect #0 value2 enable gating #1 MATH MATH Gating Set 8 8 write-only value1 no effect #0 value2 enable gating #1 WDT WDT Gating Set 9 9 write-only value1 no effect #0 value2 enable gating #1 RTC RTC Gating Set 10 10 write-only value1 no effect #0 value2 enable gating #1 CGATCLR0 Peripheral 0 Clock Gating Clear 0x10 32 0x00000000 0xFFFFFFFF VADC VADC and SHS Gating Clear 0 0 write-only value1 no effect #0 value2 disable gating #1 CCU80 CCU80 Gating Clear 1 1 write-only value1 no effect #0 value2 disble gating #1 CCU40 CCU40 Gating Clear 2 2 write-only value1 no effect #0 value2 disable gating #1 USIC0 USIC0 Gating Clear 3 3 write-only value1 no effect #0 value2 disable gating #1 BCCU0 BCCU0 Gating Clear 4 4 write-only value1 no effect #0 value2 disable gating #1 POSIF0 POSIF0 Gating Clear 7 7 write-only value1 no effect #0 value2 disable gating #1 MATH MATH Gating Clear 8 8 write-only value1 no effect #0 value2 disable gating #1 WDT WDT Gating Clear 9 9 write-only value1 no effect #0 value2 disable gating #1 RTC RTC Gating Clear 10 10 write-only value1 no effect #0 value2 disable gating #1 OSCCSR Oscillator Control and Status Register 0x14 32 0x00000000 0xFFFFFFF0 OSC2L Oscillator Valid Low Status Bit 0 0 read-only value1 The OSC frequency is usable #0 value2 The OSC frequency is not usable. Frequency is too low. #1 OSC2H Oscillator Valid High Status Bit 1 1 read-only value1 The OSC frequency is usable #0 value2 The OSC frequency is not usable. Frequency is too high. #1 OWDRES Oscillator Watchdog Reset 16 16 read-write value1 The Oscillator Watchdog is not cleared and remains active #0 value2 The Oscillator Watchdog is cleared and restarted. The OSC2L and OSC2H flag will be held in the last value until it is updated after 3 standby clock cycles. #1 OWDEN Oscillator Watchdog Enable 17 17 read-write value1 The Oscillator Watchdog is disabled #0 value2 The Oscillator Watchdog is enabled #1 SCU_RESET System Control Unit 0x40010400 0x0 0x100 registers RSTSTAT RCU Reset Status 0x00 32 0x00000000 0xFFFFF000 RSTSTAT Reset Status Information 0 9 read-only LCKEN Enable Lockup Status 10 10 read-only value1 Reset by Lockup disabled #0 value2 Reset by Lockup enabled #1 RSTSET RCU Reset Set Register 0x04 32 0x00000000 0xFFFFFFFF LCKEN Enable Lockup Reset 10 10 write-only value1 no effect #0 value2 Enable reset when Lockup gets asserted #1 RSTCLR RCU Reset Clear Register 0x08 32 0x00000000 0xFFFFFFFF RSCLR Clear Reset Status 0 0 write-only value1 no effect #0 value2 Clears field RSTSTAT.RSTSTAT #1 LCKEN Enable Lockup Reset 10 10 write-only value1 no effect #0 value2 Disable reset when Lockup gets asserted #1 RSTCON RCU Reset Control Register 0x0C 32 0x00000000 0xFFFFFFFF ECCRSTEN Enable ECC Error Reset 0 0 read-write value1 No reset when ECC double bit error occur #0 value2 Reset when ECC double bit error occur #1 LOCRSTEN Enable Loss of Clock Reset 1 1 read-write value1 No reset when loss of clock occur #0 value2 Reset when loss of clock occur #1 SPERSTEN Enable 16kbytes SRAM Parity Error Reset 2 2 read-write value1 No reset when SRAM parity error occur #0 value2 Reset when SRAM parity error occur #1 U0PERSTEN Enable USIC0 SRAM Parity Error Reset 3 3 read-write value1 No reset when USIC0 memory parity error occur #0 value2 Reset when USIC0 memory parity error occur #1 MRSTEN Enable Master Reset 16 16 write-only value1 No effect #0 value2 Triggered Master reset #1 COMPARATOR System Control Unit SCU 0x40010500 0x0 0xC00 registers ORCCTRL Out Of Range Comparator Control Register 0x00 32 0x00000000 0xFFFFFFFF ENORC0 Enable Out of Range Comparator 0 0 0 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC1 Enable Out of Range Comparator 1 1 1 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC2 Enable Out of Range Comparator 2 2 2 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC3 Enable Out of Range Comparator 3 3 3 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC4 Enable Out of Range Comparator 4 4 4 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC5 Enable Out of Range Comparator 5 5 5 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC6 Enable Out of Range Comparator 6 6 6 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 ENORC7 Enable Out of Range Comparator 7 7 7 read-write value1 Out of range comparator disabled. #0 value2 Out of range comparator enabled. #1 CNF0 Out of Range Comparator Flag 0 16 16 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF1 Out of Range Comparator Flag 1 17 17 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF2 Out of Range Comparator Flag 2 18 18 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF3 Out of Range Comparator Flag 3 19 19 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF4 Out of Range Comparator Flag 4 20 20 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF5 Out of Range Comparator Flag 5 21 21 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF6 Out of Range Comparator Flag 6 22 22 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 CNF7 Out of Range Comparator Flag 7 23 23 read-write value1 Falling edge trigger out of range event register. #0 value2 Rising edge trigger out of range event register. #1 ANACMP0 Analog Comparator 0 Control Register 0xB5C 16 0x0020 0xFFFF CMP_EN Comparator enable 0 0 read-write value1 Comparator is disabled #0 value2 Comparator is enabled #1 CMP_FLT_OFF Disables comparator filter 1 1 read-write value1 filter is active #0 value2 filter is switched off (to prevent a filter delay) #1 CMP_INV_OUT Inverted Comparator output 3 3 read-write value1 no inversion of comparator signal #0 value2 comparator signal is inverted #1 CMP_HYST_ADJ Comparator hysteresis adjust 4 5 read-write value1 Comparator hysteresis is switched off #00 value2 Hysteresis_typ = 10mV #01 value3 Hysteresis_typ = 15mV #10 value4 Hysteresis_typ = 20mV #11 ACMP0_SEL Connect ACMP0.INP to ACMP1.INP 6 6 read-write value1 ACMP0.INP is not connected #0 value2 ACMP0.INP is connected to ACMP1.INP #1 CMP_LPWR Low Power Mode 8 8 read-write value1 High Power Mode #0 value2 Low Power Mode #1 CMP_OUT Comparator output monitor bit 15 15 read-only value1 state "Vminus > Vplus" #0 value2 state "Vminus < Vplus" #1 ANACMP1 Analog Comparator 1 Control Register 0xB60 16 0x0020 0xFFFF CMP_EN Comparator enable 0 0 read-write value1 Comparator is disabled #0 value2 Comparator is enabled #1 CMP_FLT_OFF Disables comparator filter 1 1 read-write value1 filter is active #0 value2 filter is switched off (to prevent a filter delay) #1 CMP_INV_OUT Inverted Comparator output 3 3 read-write value1 no inversion of comparator signal #0 value2 comparator signal is inverted #1 CMP_HYST_ADJ Comparator hysteresis adjust 4 5 read-write value1 Comparator hysteresis is switched off #00 value2 Hysteresis_typ = 10mV #01 value3 Hysteresis_typ = 15mV #10 value4 Hysteresis_typ = 20mV #11 REF_DIV_EN Resistor Divider is enabled and Reference Voltage is applied to ACMP1 6 6 read-write value1 no resistor is connected #0 value2 the divider resistor is enabled and the voltage is applied to ACMP1.INP #1 CMP_OUT Comparator output monitor bit 15 15 read-only value1 state "Vminus > Vplus" #0 value2 state "Vminus < Vplus" #1 ANACMP2 Analog Comparator 2 Control Register 0xB64 16 0x0020 0xFFFF CMP_EN Comparator enable 0 0 read-write value1 Comparator is disabled #0 value2 Comparator is enabled #1 CMP_FLT_OFF Disables comparator filter 1 1 read-write value1 filter is active #0 value2 filter is switched off (to prevent a filter delay) #1 CMP_INV_OUT Inverted Comparator output 3 3 read-write value1 no inversion of comparator signal #0 value2 comparator signal is inverted #1 CMP_HYST_ADJ Comparator hysteresis adjust 4 5 read-write value1 Comparator hysteresis is switched off #00 value2 Hysteresis_typ = 10mV #01 value3 Hysteresis_typ = 15mV #10 value4 Hysteresis_typ = 20mV #11 ACMP2_SEL Connect ACMP2.INP to ACMP1.INP 6 6 read-write value1 ACMP2.INP is not connected #0 value2 ACMP2.INP is connected to ACMP1.INP #1 CMP_OUT Comparator output monitor bit 15 15 read-only value1 state "Vminus > Vplus" #0 value2 state "Vminus < Vplus" #1 SCU_ANALOG System Control Unit SCU 0x40011000 0x0 0x100 registers ANATSECTRL Temperature Sensor Control Register 0x24 16 0x0000 0xFFFF TSE_EN Temperature sensor enable 0 0 read-write value1 Temperature sensor is disabled #0 value2 Temperature sensor is switched on #1 ANATSEIH Temperature Sensor High Temperature Interrupt Register 0x30 16 0x0000 0xFFFF TSE_IH Counter value for high temperature interrupt 0 15 read-write ANATSEIL Temperature Sensor Low Temperature Interrupt Register 0x34 16 0xFFFF 0xFFFF TSE_IL Counter value for low temperature interrupt 0 15 read-write ANATSEMON Temperature Sensor Counter2 Monitor Register 0x40 16 0x0000 0xFFFF TSE_MON Monitor Counter2 value; loaded by TSE_DONE 0 15 read-only ANAVDEL Voltage Detector Control Register 0x50 16 0x001C 0xFFFF VDEL_SELECT VDEL Range Select 0 1 read-write value1 2.25V #00 value2 3.0V #01 value3 4.4V #10 VDEL_TIM_ADJ VDEL Timing Setting 2 3 read-write value1 typ 1us - slowest response time #00 value2 typ 500n #01 value3 typ 250n #10 value4 no delay - fastest response time. #11 VDEL_EN VDEL unit Enable 4 4 read-write value1 VDEL is disabled #0 value2 VDEL is active #1 ANAOFFSET DCO1 Offset Register 0x6C 16 0x0004 0xFFFF ADJL_OFFSET ADJL Offset register 0 3 read-write value1 - 3.75%, typ. 0x0 value2 - 2.85%, typ. 0x1 value3 0, default 0x4 value4 + 0.95%, typ. 0x5 value5 + 3.75%, typ. 0x8 CCU40 Capture Compare Unit 4 - Unit 0 CCU4 CCU4 0x48040000 0x0 0x010000 registers CCU40_0 Capture Compare Unit 4 (Module 0) 21 CCU40_1 Capture Compare Unit 4 (Module 0) 22 CCU40_2 Capture Compare Unit 4 (Module 0) 23 CCU40_3 Capture Compare Unit 4 (Module 0) 24 GCTRL Global Control Register 0x00 32 0x00000000 0xFFFFFFFF PRBC Prescaler Clear Configuration 0 2 read-write value1 SW only #000 value2 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. #001 value3 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. #010 value4 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. #011 value5 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. #100 PCIS Prescaler Input Clock Selection 4 5 read-write value1 Module clock #00 value2 CCU4x.ECLKA #01 value3 CCU4x.ECLKB #10 value4 CCU4x.ECLKC #11 SUSCFG Suspend Mode Configuration 8 9 read-write value1 Suspend request ignored. The module never enters in suspend #00 value2 Stops all the running slices immediately. Safe stop is not applied. #01 value3 Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. #10 value4 Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. #11 MSE0 Slice 0 Multi Channel shadow transfer enable 10 10 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU4x.MCSS input. #1 MSE1 Slice 1 Multi Channel shadow transfer enable 11 11 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU4x.MCSS input. #1 MSE2 Slice 2 Multi Channel shadow transfer enable 12 12 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU4x.MCSS input. #1 MSE3 Slice 3 Multi Channel shadow transfer enable 13 13 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU4x.MCSS input. #1 MSDE Multi Channel shadow transfer request configuration 14 15 read-write value1 Only the shadow transfer for period and compare values is requested #00 value2 Shadow transfer for the compare, period and prescaler compare values is requested #01 value4 Shadow transfer for the compare, period, prescaler and dither compare values is requested #11 GSTAT Global Status Register 0x04 32 0x0000000F 0xFFFFFFFF S0I CC40 IDLE status 0 0 read-only value1 Running #0 value2 Idle #1 S1I CC41 IDLE status 1 1 read-only value1 Running #0 value2 Idle #1 S2I CC42 IDLE status 2 2 read-only value1 Running #0 value2 Idle #1 S3I CC43 IDLE status 3 3 read-only value1 Running #0 value2 Idle #1 PRB Prescaler Run Bit 8 8 read-only value1 Prescaler is stopped #0 value2 Prescaler is running #1 GIDLS Global Idle Set 0x08 32 0x00000000 0xFFFFFFFF SS0I CC40 IDLE mode set 0 0 write-only SS1I CC41 IDLE mode set 1 1 write-only SS2I CC42 IDLE mode set 2 2 write-only SS3I CC43 IDLE mode set 3 3 write-only CPRB Prescaler Run Bit Clear 8 8 write-only PSIC Prescaler clear 9 9 write-only GIDLC Global Idle Clear 0x0C 32 0x00000000 0xFFFFFFFF CS0I CC40 IDLE mode clear 0 0 write-only CS1I CC41 IDLE mode clear 1 1 write-only CS2I CC42 IDLE mode clear 2 2 write-only CS3I CC43 IDLE mode clear 3 3 write-only SPRB Prescaler Run Bit Set 8 8 write-only GCSS Global Channel Set 0x10 32 0x00000000 0xFFFFFFFF S0SE Slice 0 shadow transfer set enable 0 0 write-only S0DSE Slice 0 Dither shadow transfer set enable 1 1 write-only S0PSE Slice 0 Prescaler shadow transfer set enable 2 2 write-only S1SE Slice 1 shadow transfer set enable 4 4 write-only S1DSE Slice 1 Dither shadow transfer set enable 5 5 write-only S1PSE Slice 1 Prescaler shadow transfer set enable 6 6 write-only S2SE Slice 2 shadow transfer set enable 8 8 write-only S2DSE Slice 2 Dither shadow transfer set enable 9 9 write-only S2PSE Slice 2 Prescaler shadow transfer set enable 10 10 write-only S3SE Slice 3 shadow transfer set enable 12 12 write-only S3DSE Slice 3 Dither shadow transfer set enable 13 13 write-only S3PSE Slice 3 Prescaler shadow transfer set enable 14 14 write-only S0STS Slice 0 status bit set 16 16 write-only S1STS Slice 1 status bit set 17 17 write-only S2STS Slice 2 status bit set 18 18 write-only S3STS Slice 3 status bit set 19 19 write-only GCSC Global Channel Clear 0x14 32 0x00000000 0xFFFFFFFF S0SC Slice 0 shadow transfer clear 0 0 write-only S0DSC Slice 0 Dither shadow transfer clear 1 1 write-only S0PSC Slice 0 Prescaler shadow transfer clear 2 2 write-only S1SC Slice 1 shadow transfer clear 4 4 write-only S1DSC Slice 1 Dither shadow transfer clear 5 5 write-only S1PSC Slice 1 Prescaler shadow transfer clear 6 6 write-only S2SC Slice 2 shadow transfer clear 8 8 write-only S2DSC Slice 2 Dither shadow transfer clear 9 9 write-only S2PSC Slice 2 Prescaler shadow transfer clear 10 10 write-only S3SC Slice 3 shadow transfer clear 12 12 write-only S3DSC Slice 3 Dither shadow transfer clear 13 13 write-only S3PSC Slice 3 Prescaler shadow transfer clear 14 14 write-only S0STC Slice 0 status bit clear 16 16 write-only S1STC Slice 1 status bit clear 17 17 write-only S2STC Slice 2 status bit clear 18 18 write-only S3STC Slice 3 status bit clear 19 19 write-only GCST Global Channel Status 0x18 32 0x00000000 0xFFFFFFFF S0SS Slice 0 shadow transfer status 0 0 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S0DSS Slice 0 Dither shadow transfer status 1 1 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S0PSS Slice 0 Prescaler shadow transfer status 2 2 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S1SS Slice 1 shadow transfer status 4 4 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S1DSS Slice 1 Dither shadow transfer status 5 5 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S1PSS Slice 1 Prescaler shadow transfer status 6 6 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S2SS Slice 2 shadow transfer status 8 8 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S2DSS Slice 2 Dither shadow transfer status 9 9 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S2PSS Slice 2 Prescaler shadow transfer status 10 10 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S3SS Slice 3 shadow transfer status 12 12 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S3DSS Slice 3 Dither shadow transfer status 13 13 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S3PSS Slice 3 Prescaler shadow transfer status 14 14 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 CC40ST Slice 0 status bit 16 16 read-only CC41ST Slice 1 status bit 17 17 read-only CC42ST Slice 2 status bit 18 18 read-only CC43ST Slice 3 status bit 19 19 read-only MIDR Module Identification 0x80 32 0x00A6C000 0xFFFFFF00 MODR Module Revision 0 7 read-only MODT Module Type 8 15 read-only MODN Module Number 16 31 read-only CCU40_CC40 Capture Compare Unit 4 - Unit 0 CCU4 CCU4_CC4 0x48040100 0x0 0x100 registers INS Input Selector Configuration 0x00 32 0x00000000 0xFFFFFFFF EV0IS Event 0 signal selection 0 3 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV1IS Event 1 signal selection 4 7 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV2IS Event 2 signal selection 8 11 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV0EM Event 0 Edge Selection 16 17 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV1EM Event 1 Edge Selection 18 19 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV2EM Event 2 Edge Selection 20 21 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV0LM Event 0 Level Selection 22 22 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV1LM Event 1 Level Selection 23 23 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV2LM Event 2 Level Selection 24 24 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 LPF0M Event 0 Low Pass Filter Configuration 25 26 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 LPF1M Event 1 Low Pass Filter Configuration 27 28 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 LPF2M Event 2 Low Pass Filter Configuration 29 30 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 CMC Connection Matrix Control 0x04 32 0x00000000 0xFFFFFFFF STRTS External Start Functionality Selector 0 1 read-write value1 External Start Function deactivated #00 value2 External Start Function triggered by Event 0 #01 value3 External Start Function triggered by Event 1 #10 value4 External Start Function triggered by Event 2 #11 ENDS External Stop Functionality Selector 2 3 read-write value1 External Stop Function deactivated #00 value2 External Stop Function triggered by Event 0 #01 value3 External Stop Function triggered by Event 1 #10 value4 External Stop Function triggered by Event 2 #11 CAP0S External Capture 0 Functionality Selector 4 5 read-write value1 External Capture 0 Function deactivated #00 value2 External Capture 0 Function triggered by Event 0 #01 value3 External Capture 0 Function triggered by Event 1 #10 value4 External Capture 0 Function triggered by Event 2 #11 CAP1S External Capture 1 Functionality Selector 6 7 read-write value1 External Capture 1 Function deactivated #00 value2 External Capture 1 Function triggered by Event 0 #01 value3 External Capture 1 Function triggered by Event 1 #10 value4 External Capture 1 Function triggered by Event 2 #11 GATES External Gate Functionality Selector 8 9 read-write value1 External Gating Function deactivated #00 value2 External Gating Function triggered by Event 0 #01 value3 External Gating Function triggered by Event 1 #10 value4 External Gating Function triggered by Event 2 #11 UDS External Up/Down Functionality Selector 10 11 read-write value1 External Up/Down Function deactivated #00 value2 External Up/Down Function triggered by Event 0 #01 value3 External Up/Down Function triggered by Event 1 #10 value4 External Up/Down Function triggered by Event 2 #11 LDS External Timer Load Functionality Selector 12 13 read-write CNTS External Count Selector 14 15 read-write value1 External Count Function deactivated #00 value2 External Count Function triggered by Event 0 #01 value3 External Count Function triggered by Event 1 #10 value4 External Count Function triggered by Event 2 #11 OFS Override Function Selector 16 16 read-write value1 Override functionality disabled #0 value2 Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 #1 TS Trap Function Selector 17 17 read-write value1 Trap function disabled #0 value2 TRAP function connected to Event 2 #1 MOS External Modulation Functionality Selector 18 19 read-write TCE Timer Concatenation Enable 20 20 read-write value1 Timer concatenation is disabled #0 value2 Timer concatenation is enabled #1 TCST Slice Timer Status 0x08 32 0x00000000 0xFFFFFFFF TRB Timer Run Bit 0 0 read-only value1 Timer is stopped #0 value2 Timer is running #1 CDIR Timer Counting Direction 1 1 read-only value1 Timer is counting up #0 value2 Timer is counting down #1 TCSET Slice Timer Run Set 0x0C 32 0x00000000 0xFFFFFFFF TRBS Timer Run Bit set 0 0 write-only TCCLR Slice Timer Clear 0x10 32 0x00000000 0xFFFFFFFF TRBC Timer Run Bit Clear 0 0 write-only TCC Timer Clear 1 1 write-only DITC Dither Counter Clear 2 2 write-only TC Slice Timer Control 0x14 32 0x00000000 0xFFFFFFFF TCM Timer Counting Mode 0 0 read-write value1 Edge aligned mode #0 value2 Center aligned mode #1 TSSM Timer Single Shot Mode 1 1 read-write value1 Single shot mode is disabled #0 value2 Single shot mode is enabled #1 CLST Shadow Transfer on Clear 2 2 read-write CMOD Capture Compare Mode 3 3 read-only value1 Compare Mode #0 value2 Capture Mode #1 ECM Extended Capture Mode 4 4 read-write value1 Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. #0 value2 Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. #1 CAPC Clear on Capture Control 5 6 read-write value1 Timer is never cleared on a capture event #00 value2 Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) #01 value3 Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) #10 value4 Timer is always cleared in a capture event. #11 ENDM Extended Stop Function Control 8 9 read-write value1 Clears the timer run bit only (default stop) #00 value2 Clears the timer only (flush) #01 value3 Clears the timer and run bit (flush/stop) #10 STRM Extended Start Function Control 10 10 read-write value1 Sets run bit only (default start) #0 value2 Clears the timer and sets run bit (flush/start) #1 SCE Equal Capture Event enable 11 11 read-write value1 Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #0 value2 Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #1 CCS Continuous Capture Enable 12 12 read-write value1 The capture into a specific capture register is done with the rules linked with the full flags, described at . #0 value2 The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). #1 DITHE Dither Enable 13 14 read-write value1 Dither is disabled #00 value2 Dither is applied to the Period #01 value3 Dither is applied to the Compare #10 value4 Dither is applied to the Period and Compare #11 DIM Dither input selector 15 15 read-write value1 Slice is using its own dither unit #0 value2 Slice is connected to the dither unit of slice 0. #1 FPE Floating Prescaler enable 16 16 read-write value1 Floating prescaler mode is disabled #0 value2 Floating prescaler mode is enabled #1 TRAPE TRAP enable 17 17 read-write value1 TRAP functionality has no effect on the output #0 value2 TRAP functionality affects the output #1 TRPSE TRAP Synchronization Enable 21 21 read-write value1 Exiting from TRAP state isn't synchronized with the PWM signal #0 value2 Exiting from TRAP state is synchronized with the PWM signal #1 TRPSW TRAP State Clear Control 22 22 read-write value1 The slice exits the TRAP state automatically when the TRAP condition is not present #0 value2 The TRAP state can only be exited by a SW request. #1 EMS External Modulation Synchronization 23 23 read-write value1 External Modulation functionality is not synchronized with the PWM signal #0 value2 External Modulation functionality is synchronized with the PWM signal #1 EMT External Modulation Type 24 24 read-write value1 External Modulation functionality is clearing the CC4yST bit. #0 value2 External Modulation functionality is gating the outputs. #1 MCME Multi Channel Mode Enable 25 25 read-write value1 Multi Channel Mode is disabled #0 value2 Multi Channel Mode is enabled #1 PSL Passive Level Config 0x18 32 0x00000000 0xFFFFFFFF PSL Output Passive Level 0 0 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 DIT Dither Config 0x1C 32 0x00000000 0xFFFFFFFF DCV Dither compare Value 0 3 read-only DCNT Dither counter actual value 8 11 read-only DITS Dither Shadow Register 0x20 32 0x00000000 0xFFFFFFFF DCVS Dither Shadow Compare Value 0 3 read-write PSC Prescaler Control 0x24 32 0x00000000 0xFFFFFFFF PSIV Prescaler Initial Value 0 3 read-write FPC Floating Prescaler Control 0x28 32 0x00000000 0xFFFFFFFF PCMP Floating Prescaler Compare Value 0 3 read-only PVAL Actual Prescaler Value 8 11 read-write FPCS Floating Prescaler Shadow 0x2C 32 0x00000000 0xFFFFFFFF PCMP Floating Prescaler Shadow Compare Value 0 3 read-write PR Timer Period Value 0x30 32 0x00000000 0xFFFFFFFF PR Period Register 0 15 read-only PRS Timer Shadow Period Value 0x34 32 0x00000000 0xFFFFFFFF PRS Period Register 0 15 read-write CR Timer Compare Value 0x38 32 0x00000000 0xFFFFFFFF CR Compare Register 0 15 read-only CRS Timer Shadow Compare Value 0x3C 32 0x00000000 0xFFFFFFFF CRS Compare Register 0 15 read-write TIMER Timer Value 0x70 32 0x00000000 0xFFFFFFFF TVAL Timer Value 0 15 read-write C0V Capture Register 0 0x74 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C1V Capture Register 1 0x78 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C2V Capture Register 2 0x7C 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C3V Capture Register 3 0x80 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 INTS Interrupt Status 0xA0 32 0x00000000 0xFFFFFFFF PMUS Period Match while Counting Up 0 0 read-only value1 Period match while counting up not detected #0 value2 Period match while counting up detected #1 OMDS One Match while Counting Down 1 1 read-only value1 One match while counting down not detected #0 value2 One match while counting down detected #1 CMUS Compare Match while Counting Up 2 2 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 CMDS Compare Match while Counting Down 3 3 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 E0AS Event 0 Detection Status 8 8 read-only value1 Event 0 not detected #0 value2 Event 0 detected #1 E1AS Event 1 Detection Status 9 9 read-only value1 Event 1 not detected #0 value2 Event 1 detected #1 E2AS Event 2 Detection Status 10 10 read-only value1 Event 2 not detected #0 value2 Event 2 detected #1 TRPF Trap Flag Status 11 11 read-only INTE Interrupt Enable Control 0xA4 32 0x00000000 0xFFFFFFFF PME Period match while counting up enable 0 0 read-write value1 Period Match interrupt is disabled #0 value2 Period Match interrupt is enabled #1 OME One match while counting down enable 1 1 read-write value1 One Match interrupt is disabled #0 value2 One Match interrupt is enabled #1 CMUE Compare match while counting up enable 2 2 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 CMDE Compare match while counting down enable 3 3 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 E0AE Event 0 interrupt enable 8 8 read-write value1 Event 0 detection interrupt is disabled #0 value2 Event 0 detection interrupt is enabled #1 E1AE Event 1 interrupt enable 9 9 read-write value1 Event 1 detection interrupt is disabled #0 value2 Event 1 detection interrupt is enabled #1 E2AE Event 2 interrupt enable 10 10 read-write value1 Event 2 detection interrupt is disabled #0 value2 Event 2 detection interrupt is enabled #1 SRS Service Request Selector 0xA8 32 0x00000000 0xFFFFFFFF POSR Period/One match Service request selector 0 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 CMSR Compare match Service request selector 2 3 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E0SR Event 0 Service request selector 8 9 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E1SR Event 1 Service request selector 10 11 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E2SR Event 2 Service request selector 12 13 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 SWS Interrupt Status Set 0xAC 32 0x00000000 0xFFFFFFFF SPM Period match while counting up set 0 0 write-only SOM One match while counting down set 1 1 write-only SCMU Compare match while counting up set 2 2 write-only SCMD Compare match while counting down set 3 3 write-only SE0A Event 0 detection set 8 8 write-only SE1A Event 1 detection set 9 9 write-only SE2A Event 2 detection set 10 10 write-only STRPF Trap Flag status set 11 11 write-only SWR Interrupt Status Clear 0xB0 32 0x00000000 0xFFFFFFFF RPM Period match while counting up clear 0 0 write-only ROM One match while counting down clear 1 1 write-only RCMU Compare match while counting up clear 2 2 write-only RCMD Compare match while counting down clear 3 3 write-only RE0A Event 0 detection clear 8 8 write-only RE1A Event 1 detection clear 9 9 write-only RE2A Event 2 detection clear 10 10 write-only RTRPF Trap Flag status clear 11 11 write-only ECRD0 Extended Read Back 0 0xB8 32 0x00000000 0xFFFFFFFF modifyExternal CAPV Timer Capture Value 0 15 read-only FPCV Prescaler Capture value 16 19 read-only SPTR Slice pointer 20 21 read-only value1 CC40 #00 value2 CC41 #01 value3 CC42 #10 value4 CC43 #11 VPTR Capture register pointer 22 23 read-only value1 Capture register 0 #00 value2 Capture register 1 #01 value3 Capture register 2 #10 value4 Capture register 3 #11 FFL Full Flag 24 24 read-only value1 No new value was captured into this register #0 value2 A new value has been captured into this register #1 LCV Lost Capture Value 25 25 read-only value1 No capture was lost #0 value2 A capture was lost #1 ECRD1 Extended Read Back 1 0xBC 32 0x00000000 0xFFFFFFFF modifyExternal CAPV Timer Capture Value 0 15 read-only FPCV Prescaler Capture value 16 19 read-only SPTR Slice pointer 20 21 read-only value1 CC40 #00 value2 CC41 #01 value3 CC42 #10 value4 CC43 #11 VPTR Capture register pointer 22 23 read-only value1 Capture register 0 #00 value2 Capture register 1 #01 value3 Capture register 2 #10 value4 Capture register 3 #11 FFL Full Flag 24 24 read-only value1 No new value was captured into this register #0 value2 A new value has been captured into this register #1 LCV Lost Capture Value 25 25 read-only value1 No capture was lost #0 value2 A capture was lost #1 CCU40_CC41 Capture Compare Unit 4 - Unit 0 CCU4 0x48040200 0x0 0x100 registers CCU40_CC42 Capture Compare Unit 4 - Unit 0 CCU4 0x48040300 0x0 0x100 registers CCU40_CC43 Capture Compare Unit 4 - Unit 0 CCU4 0x48040400 0x0 0x100 registers CCU80 Capture Compare Unit 8 - Unit 0 CCU8 CCU8 0x50000000 0x0 0x010000 registers CCU80_0 Capture Compare Unit 8 (Module 0) 25 CCU80_1 Capture Compare Unit 8 (Module 0) 26 GCTRL Global Control Register 0x00 32 0x00000000 0xFFFFFFFF PRBC Prescaler Clear Configuration 0 2 read-write value1 SW only #000 value2 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. #001 value3 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. #010 value4 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. #011 value5 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. #100 PCIS Prescaler Input Clock Selection 4 5 read-write value1 Module clock #00 value2 CCU8x.ECLKA #01 value3 CCU8x.ECLKB #10 value4 CCU8x.ECLKC #11 SUSCFG Suspend Mode Configuration 8 9 read-write value1 Suspend request ignored. The module never enters in suspend #00 value2 Stops all the running slices immediately. Safe stop is not applied. #01 value3 Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. #10 value4 Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. #11 MSE0 Slice 0 Multi Channel shadow transfer enable 10 10 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 MSE1 Slice 1 Multi Channel shadow transfer enable 11 11 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 MSE2 Slice 2 Multi Channel shadow transfer enable 12 12 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8xMCSS input. #1 MSE3 Slice 3 Multi Channel shadow transfer enable 13 13 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 MSDE Multi Channel shadow transfer request configuration 14 15 read-write value1 Only the shadow transfer for period and compare values is requested #00 value2 Shadow transfer for the compare, period and prescaler compare values is requested #01 value4 Shadow transfer for the compare, period, prescaler and dither compare values is requested #11 GSTAT Global Status Register 0x04 32 0x0000000F 0xFFFFFFFF S0I CC80 IDLE status 0 0 read-only value1 Running #0 value2 Idle #1 S1I CC81 IDLE status 1 1 read-only value1 Running #0 value2 Idle #1 S2I CC82 IDLE status 2 2 read-only value1 Running #0 value2 Idle #1 S3I CC83 IDLE status 3 3 read-only value1 Running #0 value2 Idle #1 PRB Prescaler Run Bit 8 8 read-only value1 Prescaler is stopped #0 value2 Prescaler is running #1 PCRB Parity Checker Run Bit 10 10 read-only value1 Parity Checker is stopped #0 value2 Parity Checker is running #1 GIDLS Global Idle Set 0x08 32 0x00000000 0xFFFFFFFF SS0I CC80 IDLE mode set 0 0 write-only SS1I CC81 IDLE mode set 1 1 write-only SS2I CC82 IDLE mode set 2 2 write-only SS3I CC83 IDLE mode set 3 3 write-only CPRB Prescaler# Run Bit Clear 8 8 write-only PSIC Prescaler clear 9 9 write-only CPCH Parity Checker Run bit clear 10 10 write-only GIDLC Global Idle Clear 0x0C 32 0x00000000 0xFFFFFFFF CS0I CC80 IDLE mode clear 0 0 write-only CS1I CC81 IDLE mode clear 1 1 write-only CS2I CC82 IDLE mode clear 2 2 write-only CS3I CC83 IDLE mode clear 3 3 write-only SPRB Prescaler Run Bit Set 8 8 write-only SPCH Parity Checker run bit set 10 10 write-only GCSS Global Channel Set 0x10 32 0x00000000 0xFFFFFFFF S0SE Slice 0 shadow transfer set enable 0 0 write-only S0DSE Slice 0 Dither shadow transfer set enable 1 1 write-only S0PSE Slice 0 Prescaler shadow transfer set enable 2 2 write-only S1SE Slice 1 shadow transfer set enable 4 4 write-only S1DSE Slice 1 Dither shadow transfer set enable 5 5 write-only S1PSE Slice 1 Prescaler shadow transfer set enable 6 6 write-only S2SE Slice 2 shadow transfer set enable 8 8 write-only S2DSE Slice 2 Dither shadow transfer set enable 9 9 write-only S2PSE Slice 2 Prescaler shadow transfer set enable 10 10 write-only S3SE Slice 3 shadow transfer set enable 12 12 write-only S3DSE Slice 3 Dither shadow transfer set enable 13 13 write-only S3PSE Slice 3 Prescaler shadow transfer set enable 14 14 write-only S0ST1S Slice 0 status bit 1 set 16 16 write-only S1ST1S Slice 1 status bit 1 set 17 17 write-only S2ST1S Slice 2 status bit 1 set 18 18 write-only S3ST1S Slice 3 status bit 1 set 19 19 write-only S0ST2S Slice 0 status bit 2 set 20 20 write-only S1ST2S Slice 1 status bit 2 set 21 21 write-only S2ST2S Slice 2 status bit 2 set 22 22 write-only S3ST2S Slice 3 status bit 2 set 23 23 write-only GCSC Global Channel Clear 0x14 32 0x00000000 0xFFFFFFFF S0SC Slice 0 shadow transfer request clear 0 0 write-only S0DSC Slice 0 Dither shadow transfer clear 1 1 write-only S0PSC Slice 0 Prescaler shadow transfer clear 2 2 write-only S1SC Slice 1 shadow transfer clear 4 4 write-only S1DSC Slice 1 Dither shadow transfer clear 5 5 write-only S1PSC Slice 1 Prescaler shadow transfer clear 6 6 write-only S2SC Slice 2 shadow transfer clear 8 8 write-only S2DSC Slice 2 Dither shadow transfer clear 9 9 write-only S2PSC Slice 2 Prescaler shadow transfer clear 10 10 write-only S3SC Slice 3 shadow transfer clear 12 12 write-only S3DSC Slice 3 Dither shadow transfer clear 13 13 write-only S3PSC Slice 3 Prescaler shadow transfer clear 14 14 write-only S0ST1C Slice 0 status bit 1 clear 16 16 write-only S1ST1C Slice 1 status bit 1 clear 17 17 write-only S2ST1C Slice 2 status bit 1 clear 18 18 write-only S3ST1C Slice 3 status bit 1 clear 19 19 write-only S0ST2C Slice 0 status bit 2 clear 20 20 write-only S1ST2C Slice 1 status bit 2 clear 21 21 write-only S2ST2C Slice 2 status bit 2 clear 22 22 write-only S3ST2C Slice 3 status bit 2 clear 23 23 write-only GCST Global Channel status 0x18 32 0x00000000 0xFFFFFFFF S0SS Slice 0 shadow transfer status 0 0 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S0DSS Slice 0 Dither shadow transfer status 1 1 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S0PSS Slice 0 Prescaler shadow transfer status 2 2 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S1SS Slice 1 shadow transfer status 4 4 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S1DSS Slice 1 Dither shadow transfer status 5 5 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S1PSS Slice 1 Prescaler shadow transfer status 6 6 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S2SS Slice 2 shadow transfer status 8 8 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S2DSS Slice 2 Dither shadow transfer status 9 9 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S2PSS Slice 2 Prescaler shadow transfer status 10 10 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S3SS Slice 3 shadow transfer status 12 12 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S3DSS Slice 3 Dither shadow transfer status 13 13 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S3PSS Slice 3 Prescaler shadow transfer status 14 14 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 CC80ST1 Slice 0 compare channel 1 status bit 16 16 read-only CC81ST1 Slice 1 compare channel 1 status bit 17 17 read-only CC82ST1 Slice 2 compare channel 1 status bit 18 18 read-only CC83ST1 Slice 3 compare channel 1 status bit 19 19 read-only CC80ST2 Slice 0 compare channel 2 status bit 20 20 read-only CC81ST2 Slice 1 compare channel 2 status bit 21 21 read-only CC82ST2 Slice 2 compare channel 2 status bit 22 22 read-only CC83ST2 Slice 3 compare channel 2 status bit 23 23 read-only GPCHK Parity Checker Configuration 0x1C 32 0x00000000 0xFFFFFFFF PASE Parity Checker Automatic start/stop 0 0 read-write PACS Parity Checker Automatic start/stop selector 1 2 read-write value1 CC80 #00 value2 CC81 #01 value3 CC82 #10 value4 CC83 #11 PISEL Driver Input signal selector 3 4 read-write value1 CC8x.GP01 - driver output is connected to event 1 of slice 0 #00 value2 CC8x.GP11 - drive output is connected to event 1 of slice 1 #01 value3 CC8x.GP21 - driver output is connected to event 1 of slice 2 #10 value4 CC8x.GP31 - driver output is connected to event 1 of slice 3 #11 PCDS Parity Checker Delay Input Selector 5 6 read-write value1 CCU8x.IGBTA #00 value2 CCU8x.IGBTB #01 value3 CCU8x.IGBTC #10 value4 CCU8x.IGBTD #11 PCTS Parity Checker type selector 7 7 read-write value1 Even parity enabled #0 value2 Odd parity enabled #1 PCST Parity Checker XOR status 15 15 read-only PCSEL0 Parity Checker Slice 0 output selection 16 19 read-write PCSEL1 Parity Checker Slice 1 output selection 20 23 read-write PCSEL2 Parity Checker Slice 2 output selection 24 27 read-write PCSEL3 Parity Checker Slice 3 output selection 28 31 read-write MIDR Module Identification 0x80 32 0x00A7C000 0xFFFFFF00 MODR Module Revision 0 7 read-only MODT Module Type 8 15 read-only MODN Module Number 16 31 read-only CCU80_CC80 Capture Compare Unit 8 - Unit 0 CCU8 CCU8_CC8 0x50000100 0x0 0x100 registers INS Input Selector Configuration 0x00 32 0x00000000 0xFFFFFFFF EV0IS Event 0 signal selection 0 3 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV1IS Event 1 signal selection 4 7 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV2IS Event 2 signal selection 8 11 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV0EM Event 0 Edge Selection 16 17 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV1EM Event 1 Edge Selection 18 19 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV2EM Event 2 Edge Selection 20 21 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV0LM Event 0 Level Selection 22 22 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV1LM Event 1 Level Selection 23 23 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV2LM Event 2 Level Selection 24 24 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 LPF0M Event 0 Low Pass Filter Configuration 25 26 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 LPF1M Event 1 Low Pass Filter Configuration 27 28 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 LPF2M Event 2 Low Pass Filter Configuration 29 30 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 CMC Connection Matrix Control 0x04 32 0x00000000 0xFFFFFFFF STRTS External Start Functionality Selector 0 1 read-write value1 External Start Function deactivated #00 value2 External Start Function triggered by Event 0 #01 value3 External Start Function triggered by Event 1 #10 value4 External Start Function triggered by Event 2 #11 ENDS External Stop Functionality Selector 2 3 read-write value1 External Stop Function deactivated #00 value2 External Stop Function triggered by Event 0 #01 value3 External Stop Function triggered by Event 1 #10 value4 External Stop Function triggered by Event 2 #11 CAP0S External Capture 0 Functionality Selector 4 5 read-write value1 External Capture 0 Function deactivated #00 value2 External Capture 0 Function triggered by Event 0 #01 value3 External Capture 0 Function triggered by Event 1 #10 value4 External Capture 0 Function triggered by Event 2 #11 CAP1S External Capture 1 Functionality Selector 6 7 read-write value1 External Capture 1 Function deactivated #00 value2 External Capture 1 Function triggered by Event 0 #01 value3 External Capture 1 Function triggered by Event 1 #10 value4 External Capture 1 Function triggered by Event 2 #11 GATES External Gate Functionality Selector 8 9 read-write value1 External Gating Function deactivated #00 value2 External Gating Function triggered by Event 0 #01 value3 External Gating Function triggered by Event 1 #10 value4 External Gating Function triggered by Event 2 #11 UDS External Up/Down Functionality Selector 10 11 read-write value1 External Up/Down Function deactivated #00 value2 External Up/Down Function triggered by Event 0 #01 value3 External Up/Down Function triggered by Event 1 #10 value4 External Up/Down Function triggered by Event 2 #11 LDS External Timer Load Functionality Selector 12 13 read-write CNTS External Count Selector 14 15 read-write value1 External Count Function deactivated #00 value2 External Count Function triggered by Event 0 #01 value3 External Count Function triggered by Event 1 #10 value4 External Count Function triggered by Event 2 #11 OFS Override Function Selector 16 16 read-write value1 Override functionality disabled #0 value2 Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 #1 TS Trap Function Selector 17 17 read-write value1 Trap function disabled #0 value2 TRAP function connected to Event 2 #1 MOS External Modulation Functionality Selector 18 19 read-write TCE Timer Concatenation Enable 20 20 read-write value1 Timer concatenation is disabled #0 value2 Timer concatenation is enabled #1 TCST Slice Timer Status 0x08 32 0x00000000 0xFFFFFFFF TRB Timer Run Bit 0 0 read-only value1 Timer is stopped #0 value2 Timer is running #1 CDIR Timer Counting Direction 1 1 read-only value1 Timer is counting up #0 value2 Timer is counting down #1 DTR1 Dead Time Counter 1 Run bit 3 3 read-only value1 Dead Time counter is idle #0 value2 Dead Time counter is running #1 DTR2 Dead Time Counter 2 Run bit 4 4 read-only value1 Dead Time counter is idle #0 value2 Dead Time counter is running #1 TCSET Slice Timer Run Set 0x0C 32 0x00000000 0xFFFFFFFF TRBS Timer Run Bit set 0 0 write-only TCCLR Slice Timer Clear 0x10 32 0x00000000 0xFFFFFFFF TRBC Timer Run Bit Clear 0 0 write-only TCC Timer Clear 1 1 write-only DITC Dither Counter Clear 2 2 write-only DTC1C Dead Time Counter 1 Clear 3 3 write-only DTC2C Dead Time Counter 2 Clear 4 4 write-only TC Slice Timer Control 0x14 32 0x18000000 0xFFFFFFFF TCM Timer Counting Mode 0 0 read-write value1 Edge aligned mode #0 value2 Center aligned mode #1 TSSM Timer Single Shot Mode 1 1 read-write value1 Single shot mode is disabled #0 value2 Single shot mode is enabled #1 CLST Shadow Transfer on Clear 2 2 read-write CMOD Capture Compare Mode 3 3 read-only value1 Compare Mode #0 value2 Capture Mode #1 ECM Extended Capture Mode 4 4 read-write value1 Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. #0 value2 Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared #1 CAPC Clear on Capture Control 5 6 read-write value1 Timer is never cleared on a capture event #00 value2 Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) #01 value3 Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) #10 value4 Timer is always cleared in a capture event. #11 TLS Timer Load selector 7 7 read-write value1 Timer is loaded with the value of CR1 #0 value2 Timer is loaded with the value of CR2 #1 ENDM Extended Stop Function Control 8 9 read-write value1 Clears the timer run bit only (default stop) #00 value2 Clears the timer only (flush) #01 value3 Clears the timer and run bit (flush/stop) #10 STRM Extended Start Function Control 10 10 read-write value1 Sets run bit only (default start) #0 value2 Clears the timer and sets run bit, if not set (flush/start) #1 SCE Equal Capture Event enable 11 11 read-write value1 Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #0 value2 Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #1 CCS Continuous Capture Enable 12 12 read-write value1 The capture into a specific capture register is done with the rules linked with the full flags, described at . #0 value2 The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). #1 DITHE Dither Enable 13 14 read-write value1 Dither is disabled #00 value2 Dither is applied to the Period #01 value3 Dither is applied to the Compare #10 value4 Dither is applied to the Period and Compare #11 DIM Dither input selector 15 15 read-write value1 Slice is using it own dither unit #0 value2 Slice is connected to the dither unit of slice 0. #1 FPE Floating Prescaler enable 16 16 read-write value1 Floating prescaler mode is disabled #0 value2 Floating prescaler mode is enabled #1 TRAPE0 TRAP enable for CCU8x.OUTy0 17 17 read-write value1 TRAP functionality has no effect on the CCU8x.OUTy0 output #0 value2 TRAP functionality affects the CCU8x.OUTy0 output #1 TRAPE1 TRAP enable for CCU8x.OUTy1 18 18 read-write TRAPE2 TRAP enable for CCU8x.OUTy2 19 19 read-write TRAPE3 TRAP enable for CCU8x.OUTy3 20 20 read-write TRPSE TRAP Synchronization Enable 21 21 read-write value1 Exiting from TRAP state isn't synchronized with the PWM signal #0 value2 Exiting from TRAP state is synchronized with the PWM signal #1 TRPSW TRAP State Clear Control 22 22 read-write value1 The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) #0 value2 The TRAP state can only be exited by a SW request. #1 EMS External Modulation Synchronization 23 23 read-write value1 External Modulation functionality is not synchronized with the PWM signal #0 value2 External Modulation functionality is synchronized with the PWM signal #1 EMT External Modulation Type 24 24 read-write value1 External Modulation functionality is clearing the CC8ySTx bits. #0 value2 External Modulation functionality is gating the outputs. #1 MCME1 Multi Channel Mode Enable for Channel 1 25 25 read-write value1 Multi Channel Mode in Channel 1 is disabled #0 value2 Multi Channel Mode in Channel 1 is enabled #1 MCME2 Multi Channel Mode Enable for Channel 2 26 26 read-write value1 Multi Channel Mode in Channel 2 is disabled #0 value2 Multi Channel Mode in Channel 2 is enabled #1 EME External Modulation Channel enable 27 28 read-write value1 External Modulation functionality doesn't affect any channel #00 value2 External Modulation only applied on channel 1 #01 value3 External Modulation only applied on channel 2 #10 value4 External Modulation applied on both channels #11 STOS Status bit output selector 29 30 read-write value1 CC8yST1 forward to CCU8x.STy #00 value2 CC8yST2 forward to CCU8x.STy #01 value3 CC8yST1 AND CC8yST2 forward to CCU8x.STy #10 value4 CC8yST1 OR CC8yST2 forward to CCU8x.STy #11 PSL Passive Level Config 0x18 32 0x00000000 0xFFFFFFFF PSL11 Output Passive Level for CCU8x.OUTy0 0 0 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL12 Output Passive Level for CCU8x.OUTy1 1 1 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL21 Output Passive Level for CCU8x.OUTy2 2 2 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL22 Output Passive Level for CCU8x.OUTy3 3 3 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 DIT Dither Config 0x1C 32 0x00000000 0xFFFFFFFF DCV Dither compare Value 0 3 read-only DCNT Dither counter actual value 8 11 read-only DITS Dither Shadow Register 0x20 32 0x00000000 0xFFFFFFFF DCVS Dither Shadow Compare Value 0 3 read-write PSC Prescaler Control 0x24 32 0x00000000 0xFFFFFFFF PSIV Prescaler Initial Value 0 3 read-write FPC Floating Prescaler Control 0x28 32 0x00000000 0xFFFFFFFF PCMP Floating Prescaler Compare Value 0 3 read-only PVAL Actual Prescaler Value 8 11 read-write FPCS Floating Prescaler Shadow 0x2C 32 0x00000000 0xFFFFFFFF PCMP Floating Prescaler Shadow Compare Value 0 3 read-write PR Timer Period Value 0x30 32 0x00000000 0xFFFFFFFF PR Period Register 0 15 read-only PRS Timer Shadow Period Value 0x34 32 0x00000000 0xFFFFFFFF PRS Period Register 0 15 read-write CR1 Channel 1 Compare Value 0x38 32 0x00000000 0xFFFFFFFF CR1 Compare Register for Channel 1 0 15 read-only CR1S Channel 1 Compare Shadow Value 0x3C 32 0x00000000 0xFFFFFFFF CR1S Shadow Compare Register for Channel 1 0 15 read-write CR2 Channel 2 Compare Value 0x40 32 0x00000000 0xFFFFFFFF CR2 Compare Register for Channel 2 0 15 read-only CR2S Channel 2 Compare Shadow Value 0x44 32 0x00000000 0xFFFFFFFF CR2S Shadow Compare Register for Channel 2 0 15 read-write CHC Channel Control 0x48 32 0x00000000 0xFFFFFFFF ASE Asymmetric PWM mode Enable 0 0 read-write value1 Asymmetric PWM is disabled #0 value2 Asymmetric PWM is enabled #1 OCS1 Output selector for CCU8x.OUTy0 1 1 read-write value1 CC8yST1 signal path is connected to the CCU8x.OUTy0 #0 value2 Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 #1 OCS2 Output selector for CCU8x.OUTy1 2 2 read-write value1 Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 #0 value2 CC8yST1 signal path is connected to the CCU8x.OUTy1 #1 OCS3 Output selector for CCU8x.OUTy2 3 3 read-write value1 CC8yST2 signal path is connected to the CCU8x.OUTy2 #0 value2 Inverted CCST2 signal path is connected to the CCU8x.OUTy2 #1 OCS4 Output selector for CCU8x.OUTy3 4 4 read-write value1 Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 #0 value2 CC8yST2 signal path is connected to the CCU8x.OUTy3 #1 DTC Dead Time Control 0x4C 32 0x00000000 0xFFFFFFFF DTE1 Dead Time Enable for Channel 1 0 0 read-write value1 Dead Time for channel 1 is disabled #0 value2 Dead Time for channel 1 is enabled #1 DTE2 Dead Time Enable for Channel 2 1 1 read-write value1 Dead Time for channel 2 is disabled #0 value2 Dead Time for channel 2 is enabled #1 DCEN1 Dead Time Enable for CC8yST1 2 2 read-write value1 Dead Time for CC8yST1 path is disabled #0 value2 Dead Time for CC8yST1 path is enabled #1 DCEN2 Dead Time Enable for inverted CC8yST1 3 3 read-write value1 Dead Time for inverted CC8yST1 path is disabled #0 value2 Dead Time for inverted CC8yST1 path is enabled #1 DCEN3 Dead Time Enable for CC8yST2 4 4 read-write value1 Dead Time for CC8yST2 path is disabled #0 value2 Dead Time for CC8yST2 path is enabled #1 DCEN4 Dead Time Enable for inverted CC8yST2 5 5 read-write value1 Dead Time for inverted CC8yST2 path is disabled #0 value2 Dead Time for inverted CC8yST2 path is enabled #1 DTCC Dead Time clock control 6 7 read-write value1 ftclk #00 value2 ftclk/2 #01 value3 ftclk/4 #10 value4 ftclk/8 #11 DC1R Channel 1 Dead Time Values 0x50 32 0x00000000 0xFFFFFFFF DT1R Rise Value for Dead Time of Channel 1 0 7 read-write DT1F Fall Value for Dead Time of Channel 1 8 15 read-write DC2R Channel 2 Dead Time Values 0x54 32 0x00000000 0xFFFFFFFF DT2R Rise Value for Dead Time of Channel 2 0 7 read-write DT2F Fall Value for Dead Time of Channel 2 8 15 read-write TIMER Timer Value 0x70 32 0x00000000 0xFFFFFFFF TVAL Timer Value 0 15 read-write C0V Capture Register 0 0x74 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C1V Capture Register 1 0x78 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C2V Capture Register 2 0x7C 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 C3V Capture Register 3 0x80 32 0x00000000 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FPCV Prescaler Value 16 19 read-only FFL Full Flag 20 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 INTS Interrupt Status 0xA0 32 0x00000000 0xFFFFFFFF PMUS Period Match while Counting Up 0 0 read-only value1 Period match while counting up not detected #0 value2 Period match while counting up detected #1 OMDS One Match while Counting Down 1 1 read-only value1 One match while counting down not detected #0 value2 One match while counting down detected #1 CMU1S Channel 1 Compare Match while Counting Up 2 2 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 CMD1S Channel 1 Compare Match while Counting Down 3 3 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 CMU2S Channel 2 Compare Match while Counting Up 4 4 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 CMD2S Channel 2 Compare Match while Counting Down 5 5 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 E0AS Event 0 Detection Status 8 8 read-only value1 Event 0 not detected #0 value2 Event 0 detected #1 E1AS Event 1 Detection Status 9 9 read-only value1 Event 1 not detected #0 value2 Event 1 detected #1 E2AS Event 2 Detection Status 10 10 read-only value1 Event 2 not detected #0 value2 Event 2 detected #1 TRPF Trap Flag Status 11 11 read-only INTE Interrupt Enable Control 0xA4 32 0x00000000 0xFFFFFFFF PME Period match while counting up enable 0 0 read-write value1 Period Match interrupt is disabled #0 value2 Period Match interrupt is enabled #1 OME One match while counting down enable 1 1 read-write value1 One Match interrupt is disabled #0 value2 One Match interrupt is enabled #1 CMU1E Channel 1 Compare match while counting up enable 2 2 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 CMD1E Channel 1 Compare match while counting down enable 3 3 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 CMU2E Channel 2 Compare match while counting up enable 4 4 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 CMD2E Channel 2 Compare match while counting down enable 5 5 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 E0AE Event 0 interrupt enable 8 8 read-write value1 Event 0 detection interrupt is disabled #0 value2 Event 0 detection interrupt is enabled #1 E1AE Event 1 interrupt enable 9 9 read-write value1 Event 1 detection interrupt is disabled #0 value2 Event 1 detection interrupt is enabled #1 E2AE Event 2 interrupt enable 10 10 read-write value1 Event 2 detection interrupt is disabled #0 value2 Event 2 detection interrupt is enabled #1 SRS Service Request Selector 0xA8 32 0x00000000 0xFFFFFFFF POSR Period/One match Service request selector 0 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 CM1SR Channel 1 Compare match Service request selector 2 3 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 CM2SR Channel 2 Compare match Service request selector 4 5 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E0SR Event 0 Service request selector 8 9 read-write value1 Forward to CCvySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E1SR Event 1 Service request selector 10 11 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E2SR Event 2 Service request selector 12 13 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CCvySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 SWS Interrupt Status Set 0xAC 32 0x00000000 0xFFFFFFFF SPM Period match while counting up set 0 0 write-only SOM One match while counting down set 1 1 write-only SCM1U Channel 1 Compare match while counting up set 2 2 write-only SCM1D Channel 1 Compare match while counting down set 3 3 write-only SCM2U Compare match while counting up set 4 4 write-only SCM2D Compare match while counting down set 5 5 write-only SE0A Event 0 detection set 8 8 write-only SE1A Event 1 detection set 9 9 write-only SE2A Event 2 detection set 10 10 write-only STRPF Trap Flag status set 11 11 write-only SWR Interrupt Status Clear 0xB0 32 0x00000000 0xFFFFFFFF RPM Period match while counting up clear 0 0 write-only ROM One match while counting down clear 1 1 write-only RCM1U Channel 1 Compare match while counting up clear 2 2 write-only RCM1D Channel 1 Compare match while counting down clear 3 3 write-only RCM2U Channel 2 Compare match while counting up clear 4 4 write-only RCM2D Channel 2 Compare match while counting down clear 5 5 write-only RE0A Event 0 detection clear 8 8 write-only RE1A Event 1 detection clear 9 9 write-only RE2A Event 2 detection clear 10 10 write-only RTRPF Trap Flag status clear 11 11 write-only STC Shadow transfer control 0xB4 32 0x00000000 0xFFFFFFFF CSE Cascaded shadow transfer enable 0 0 read-write value1 Cascaded shadow transfer disabled #0 value2 Cascaded shadow transfer enabled #1 STM Shadow transfer mode 1 2 read-write value1 Shadow transfer is done in Period Match and One match. #00 value2 Shadow transfer is done only in Period Match. #01 value3 Shadow transfer is done only in One Match. #10 ECRD0 Extended Read Back 0 0xB8 32 0x00000000 0xFFFFFFFF modifyExternal CAPV Timer Capture Value 0 15 read-only FPCV Prescaler Capture value 16 19 read-only SPTR Slice pointer 20 21 read-only value1 CC80 #00 value2 CC81 #01 value3 CC82 #10 value4 CC83 #11 VPTR Capture register pointer 22 23 read-only value1 Capture register 0 #00 value2 Capture register 1 #01 value3 Capture register 2 #10 value4 Capture register 3 #11 FFL Full Flag 24 24 read-only value1 No new value was captured into this register #0 value2 A new value has been captured into this register #1 LCV Lost Capture Value 25 25 read-only value1 No capture was lost #0 value2 A capture was lost #1 ECRD1 Extended Read Back 1 0xBC 32 0x00000000 0xFFFFFFFF modifyExternal CAPV Timer Capture Value 0 15 read-only FPCV Prescaler Capture value 16 19 read-only SPTR Slice pointer 20 21 read-only value1 CC80 #00 value2 CC81 #01 value3 CC82 #10 value4 CC83 #11 VPTR Capture register pointer 22 23 read-only value1 Capture register 0 #00 value2 Capture register 1 #01 value3 Capture register 2 #10 value4 Capture register 3 #11 FFL Full Flag 24 24 read-only value1 No new value was captured into this register #0 value2 A new value has been captured into this register #1 LCV Lost Capture Value 25 25 read-only value1 No capture was lost #0 value2 A capture was lost #1 CCU80_CC81 Capture Compare Unit 8 - Unit 0 CCU8 0x50000200 0x0 0x100 registers CCU80_CC82 Capture Compare Unit 8 - Unit 0 CCU8 0x50000300 0x0 0x100 registers CCU80_CC83 Capture Compare Unit 8 - Unit 0 CCU8 0x50000400 0x0 0x100 registers POSIF0 Position Interface 0 POSIF 0x50010000 0x0 0x010000 registers POSIF0_0 Position Interface (Module 0) 27 POSIF0_1 Position Interface (Module 0) 28 PCONF CORDIC Coprocessor configuration 0x0000 32 0x00000000 0xFFFFFFFF FSEL Function Selector 0 1 read-write value1 Hall Sensor Mode enabled #00 value2 Quadrature Decoder Mode enabled #01 value3 stand-alone Multi-Channel Mode enabled #10 value4 Quadrature Decoder and stand-alone Multi-Channel Mode enabled #11 QDCM Position Decoder Mode selection 2 2 read-write value1 Position encoder is in Quadrature Mode #0 value2 Position encoder is in Direction Count Mode. #1 HIDG Idle generation enable 4 4 read-write MCUE Multi-Channel Pattern SW update enable 5 5 read-write value1 Multi-Channel pattern update is controlled via HW #0 value2 Multi-Channel pattern update is controlled via SW #1 INSEL0 PhaseA/Hal input 1 selector 8 9 read-write value1 POSIFx.IN0A #00 value2 POSIFx.IN0B #01 value3 POSIFx.IN0C #10 value4 POSIFx.IN0D #11 INSEL1 PhaseB/Hall input 2 selector 10 11 read-write value1 POSIFx.IN1A #00 value2 POSIFx.IN1B #01 value3 POSIFx.IN1C #10 value4 POSIFx.IN1D #11 INSEL2 Index/Hall input 3 selector 12 13 read-write value1 POSIFx.IN2A #00 value2 POSIFx.IN2B #01 value3 POSIFx.IN2C #10 value4 POSIFx.IN2D #11 DSEL Delay Pin selector 16 16 read-write value1 POSIFx.HSDA #0 value2 POSIFx.HSDB #1 SPES Edge selector for the sampling trigger 17 17 read-write value1 Rising edge #0 value2 Falling edge #1 MSETS Pattern update signal select 18 20 read-write value1 POSIFx.MSETA #000 value2 POSIFx.MSETB #001 value3 POSIFx.MSETC #010 value4 POSIFx.MSETD #011 value5 POSIFx.MSETE #100 value6 POSIFx.MSETF #101 value7 POSIFx.MSETG #110 value8 POSIFx.MSETH #111 MSES Multi-Channel pattern update trigger edge 21 21 read-write value1 The signal used to enable a pattern update is active on the rising edge #0 value2 The signal used to enable a pattern update is active on the falling edge #1 MSYNS PWM synchronization signal selector 22 23 read-write value1 POSIFx.MSYNCA #00 value2 POSIFx.MSYNCB #01 value3 POSIFx.MSYNCC #10 value4 POSIFx.MSYNCD #11 EWIS Wrong Hall Event selection 24 25 read-write value1 POSIFx.EWHEA #00 value2 POSIFx.EWHEB #01 value3 POSIFx.EWHEC #10 value4 POSIFx.EWHED #11 EWIE External Wrong Hall Event enable 26 26 read-write value1 External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled #0 value2 External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. #1 EWIL External Wrong Hall Event active level 27 27 read-write value1 POSIFx.EWHE[D...A] signal is active HIGH #0 value2 POSIFx.EWHE[D...A] signal is active LOW #1 LPC Low Pass Filters Configuration 28 30 read-write value1 Low pass filter disabled #000 value2 Low pass of 1 clock cycle #001 value3 Low pass of 2 clock cycles #010 value4 Low pass of 4 clock cycles #011 value5 Low pass of 8 clock cycles #100 value6 Low pass of 16 clock cycles #101 value7 Low pass of 32 clock cycles #110 value8 Low pass of 64 clock cycles #111 PSUS CORDIC Coprocessor Suspend Config 0x0004 32 0x00000000 0xFFFFFFFF QSUS Quadrature Mode Suspend Config 0 1 read-write value1 Suspend request ignored #00 value2 Stop immediately #01 value3 Suspend in the next index occurrence #10 value4 Suspend in the next phase (PhaseA or PhaseB) occurrence #11 MSUS Multi-Channel Mode Suspend Config 2 3 read-write value1 Suspend request ignored #00 value2 Stop immediately. Multi-Channel pattern is not set to the reset value. #01 value3 Stop immediately. Multi-Channel pattern is set to the reset value. #10 value4 Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. #11 PRUNS CORDIC Coprocessor Run Bit Set 0x0008 32 0x00000000 0xFFFFFFFF SRB Set Run bit 0 0 write-only PRUNC CORDIC Coprocessor Run Bit Clear 0x000C 32 0x00000000 0xFFFFFFFF CRB Clear Run bit 0 0 write-only CSM Clear Current internal status 1 1 write-only PRUN CORDIC Coprocessor Run Bit Status 0x0010 32 0x00000000 0xFFFFFFFF RB Run Bit 0 0 read-only value1 IDLE #0 value2 Running #1 MIDR Module Identification register 0x0020 32 0x00A8C000 0xFFFFFF00 MODR Module Revision 0 7 read-only MODT Module Type 8 15 read-only MODN Module Number 16 31 read-only HALP Hall Sensor Patterns 0x0030 32 0x00000000 0xFFFFFFFF HCP Hall Current Pattern 0 2 read-only HEP Hall Expected Pattern 3 5 read-only HALPS Hall Sensor Shadow Patterns 0x0034 32 0x00000000 0xFFFFFFFF HCPS Shadow Hall Current Pattern 0 2 read-write HEPS Shadow Hall expected Pattern 3 5 read-write MCM Multi-Channel Pattern 0x0040 32 0x00000000 0xFFFFFFFF MCMP Multi-Channel Pattern 0 15 read-only MCSM Multi-Channel Shadow Pattern 0x0044 32 0x00000000 0xFFFFFFFF MCMPS Shadow Multi-Channel Pattern 0 15 read-write MCMS Multi-Channel Pattern Control set 0x0048 32 0x00000000 0xFFFFFFFF MNPS Multi-Channel Pattern Update Enable Set 0 0 write-only STHR Hall Pattern Shadow Transfer Request 1 1 write-only STMR Multi-Channel Shadow Transfer Request 2 2 write-only MCMC Multi-Channel Pattern Control clear 0x004C 32 0x00000000 0xFFFFFFFF MNPC Multi-Channel Pattern Update Enable Clear 0 0 write-only MPC Multi-Channel Pattern clear 1 1 write-only MCMF Multi-Channel Pattern Control flag 0x0050 32 0x00000000 0xFFFFFFFF MSS Multi-Channel Pattern update status 0 0 read-only value1 Update of the Multi-Channel pattern is set #0 value2 Update of the Multi-Channel pattern is not set #1 QDC Quadrature Decoder Control 0x0060 32 0x00000000 0xFFFFFFFF PALS Phase A Level selector 0 0 read-write value1 Phase A is active HIGH #0 value2 Phase A is active LOW #1 PBLS Phase B Level selector 1 1 read-write value1 Phase B is active HIGH #0 value2 Phase B is active LOW #1 PHS Phase signals swap 2 2 read-write value1 Phase A is the leading signal for clockwise rotation #0 value2 Phase B is the leading signal for clockwise rotation #1 ICM Index Marker generations control 4 5 read-write value1 No index marker generation on POSIFx.OUT3 #00 value2 Only first index occurrence generated on POSIFx.OUT3 #01 value3 All index occurrences generated on POSIFx.OUT3 #10 DVAL Current rotation direction 8 8 read-only value1 Counterclockwise rotation #0 value2 Clockwise rotation #1 PFLG CORDIC Coprocessor Interrupt Flags 0x0070 32 0x00000000 0xFFFFFFFF CHES Correct Hall Event Status 0 0 read-only value1 Correct Hall Event not detected #0 value2 Correct Hall Event detected #1 WHES Wrong Hall Event Status 1 1 read-only value1 Wrong Hall Event not detected #0 value2 Wrong Hall Event detected #1 HIES Hall Inputs Update Status 2 2 read-only value1 Transition on the Hall Inputs not detected #0 value2 Transition on the Hall Inputs detected #1 MSTS Multi-Channel pattern shadow transfer status 4 4 read-only value1 Shadow transfer not done #0 value2 Shadow transfer done #1 INDXS Quadrature Index Status 8 8 read-only value1 Index event not detected #0 value2 Index event detected #1 ERRS Quadrature Phase Error Status 9 9 read-only value1 Phase Error event not detected #0 value2 Phase Error event detected #1 CNTS Quadrature CLK Status 10 10 read-only value1 Quadrature clock not generated #0 value2 Quadrature clock generated #1 DIRS Quadrature Direction Change 11 11 read-only value1 Change on direction not detected #0 value2 Change on direction detected #1 PCLKS Quadrature Period Clk Status 12 12 read-only value1 Period clock not generated #0 value2 Period clock generated #1 PFLGE CORDIC Coprocessor Interrupt Enable 0x0074 32 0x00000000 0xFFFFFFFF ECHE Correct Hall Event Enable 0 0 read-write value1 Correct Hall Event interrupt disabled #0 value2 Correct Hall Event interrupt enabled #1 EWHE Wrong Hall Event Enable 1 1 read-write value1 Wrong Hall Event interrupt disabled #0 value2 Wrong Hall Event interrupt enabled #1 EHIE Hall Input Update Enable 2 2 read-write value1 Update of the Hall Inputs interrupt is disabled #0 value2 Update of the Hall Inputs interrupt is enabled #1 EMST Multi-Channel pattern shadow transfer enable 4 4 read-write value1 Shadow transfer event interrupt disabled #0 value2 Shadow transfer event interrupt enabled #1 EINDX Quadrature Index Event Enable 8 8 read-write value1 Index event interrupt disabled #0 value2 Index event interrupt enabled #1 EERR Quadrature Phase Error Enable 9 9 read-write value1 Phase error event interrupt disabled #0 value2 Phase error event interrupt enabled #1 ECNT Quadrature CLK interrupt Enable 10 10 read-write value1 Quadrature CLK event interrupt disabled #0 value2 Quadrature CLK event interrupt enabled #1 EDIR Quadrature direction change interrupt Enable 11 11 read-write value1 Direction change event interrupt disabled #0 value2 Direction change event interrupt enabled #1 EPCLK Quadrature Period CLK interrupt Enable 12 12 read-write value1 Quadrature Period CLK event interrupt disabled #0 value2 Quadrature Period CLK event interrupt enabled #1 CHESEL Correct Hall Event Service Request Selector 16 16 read-write value1 Correct Hall Event interrupt forward to POSIFx.SR0 #0 value2 Correct Hall Event interrupt forward to POSIFx.SR1 #1 WHESEL Wrong Hall Event Service Request Selector 17 17 read-write value1 Wrong Hall Event interrupt forward to POSIFx.SR0 #0 value2 Wrong Hall Event interrupt forward to POSIFx.SR1 #1 HIESEL Hall Inputs Update Event Service Request Selector 18 18 read-write value1 Hall Inputs Update Event interrupt forward to POSIFx.SR0 #0 value2 Hall Inputs Update Event interrupt forward to POSIFx.SR1 #1 MSTSEL Multi-Channel pattern Update Event Service Request Selector 20 20 read-write value1 Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 #0 value2 Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 #1 INDSEL Quadrature Index Event Service Request Selector 24 24 read-write value1 Quadrature Index Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Index Event interrupt forward to POSIFx.SR1 #1 ERRSEL Quadrature Phase Error Event Service Request Selector 25 25 read-write value1 Quadrature Phase error Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Phase error Event interrupt forward to POSIFx.SR1 #1 CNTSEL Quadrature Clock Event Service Request Selector 26 26 read-write value1 Quadrature Clock Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Clock Event interrupt forward to POSIFx.SR1 #1 DIRSEL Quadrature Direction Update Event Service Request Selector 27 27 read-write value1 Quadrature Direction Update Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Direction Update Event interrupt forward to POSIFx.SR1 #1 PCLSEL Quadrature Period clock Event Service Request Selector 28 28 read-write value1 Quadrature Period clock Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Period clock Event interrupt forward to POSIFx.SR1 #1 SPFLG CORDIC Coprocessor Interrupt Set 0x0078 32 0x00000000 0xFFFFFFFF SCHE Correct Hall Event flag set 0 0 write-only SWHE Wrong Hall Event flag set 1 1 write-only SHIE Hall Inputs Update Event flag set 2 2 write-only SMST Multi-Channel Pattern shadow transfer flag set 4 4 write-only SINDX Quadrature Index flag set 8 8 write-only SERR Quadrature Phase Error flag set 9 9 write-only SCNT Quadrature CLK flag set 10 10 write-only SDIR Quadrature Direction flag set 11 11 write-only SPCLK Quadrature period clock flag set 12 12 write-only RPFLG CORDIC Coprocessor Interrupt Clear 0x007C 32 0x00000000 0xFFFFFFFF RCHE Correct Hall Event flag clear 0 0 write-only RWHE Wrong Hall Event flag clear 1 1 write-only RHIE Hall Inputs Update Event flag clear 2 2 write-only RMST Multi-Channel Pattern shadow transfer flag clear 4 4 write-only RINDX Quadrature Index flag clear 8 8 write-only RERR Quadrature Phase Error flag clear 9 9 write-only RCNT Quadrature CLK flag clear 10 10 write-only RDIR Quadrature Direction flag clear 11 11 write-only RPCLK Quadrature period clock flag clear 12 12 write-only PDBG CORDIC Coprocessor Debug register 0x0100 32 0x00000000 0xFFFFFFFF QCSV Quadrature Decoder Current state 0 1 read-only QPSV Quadrature Decoder Previous state 2 3 read-only IVAL Current Index Value 4 4 read-only HSP Hall Current Sampled Pattern 5 7 read-only LPP0 Actual count of the Low Pass Filter for POSI0 8 13 read-only LPP1 Actual count of the Low Pass Filter for POSI1 16 21 read-only LPP2 Actual count of the Low Pass Filter for POSI2 22 27 read-only VADC Analog to Digital Converter VADC VADC 0x48030000 0x0 0x0400 registers VADC0_C0_0 Analog to Digital Converter Common Block 0 15 VADC0_C0_1 Analog to Digital Converter Common Block 0 16 CLC Clock Control Register 0x0000 32 0x00000003 0xFFFFFFFF DISR Module Disable Request Bit 0 0 read-write value1 On request: enable the module clock #0 value2 Off request: stop the module clock #1 DISS Module Disable Status Bit 1 1 read-only value1 Module clock is enabled #0 value2 Off: module is not clocked #1 EDIS Sleep Mode Enable Control 3 3 read-write value1 Sleep mode request is enabled and functional #0 value2 Module disregards the sleep mode control signal #1 ID Module Identification Register 0x0008 32 0x00C5C000 0xFFFFFF00 MOD_REV Module Revision 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number 16 31 read-only OCS OCDS Control and Status Register 0x0028 32 0x00000000 0xFFFFFFFF TGS Trigger Set for OTGB0/1 0 1 read-write value1 No Trigger Set output #00 value2 Trigger Set 1: TS16_SSIG, input sample signals #01 TGB OTGB0/1 Bus Select 2 2 read-write value1 Trigger Set is output on OTGB0 #0 value2 Trigger Set is output on OTGB1 #1 TG_P TGS, TGB Write Protection 3 3 write-only SUS OCDS Suspend Control 24 27 read-write value1 Will not suspend #0000 value2 Hard suspend: Clock is switched off immediately. #0001 value3 Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. #0010 value4 Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. #0011 SUS_P SUS Write Protection 28 28 write-only SUSSTA Suspend State 29 29 read-only value1 Module is not (yet) suspended #0 value2 Module is suspended #1 GLOBCFG Global Configuration Register 0x0080 32 0x0000000F 0xFFFFFFFF DIVA Divider Factor for the Analog Internal Clock 0 4 read-write value1 fADCI = fADC / 2 0x00 value2 fADCI = fADC / 2 0x01 value3 fADCI = fADC / 3 0x02 value4 fADCI = fADC / 32 0x1F DCMSB Double Clock for the MSB Conversion 7 7 read-write value1 1 clock cycles for the MSB (standard) #0 value2 2 clock cycles for the MSB (fADCI > 20 MHz) #1 DIVD Divider Factor for the Arbiter Clock 8 9 read-write value1 fADCD = fADC #00 value2 fADCD = fADC / 2 #01 value3 fADCD = fADC / 3 #10 value4 fADCD = fADC / 4 #11 DIVWC Write Control for Divider Parameters 15 15 write-only value1 No write access to divider parameters #0 value2 Bitfields DIVA, DCMSB, DIVD can be written #1 DPCAL0 Disable Post-Calibration 16 16 read-write value1 Automatic post-calibration after each conversion of group x #0 value2 No post-calibration #1 DPCAL1 Disable Post-Calibration 17 17 read-write value1 Automatic post-calibration after each conversion of group x #0 value2 No post-calibration #1 SUCAL Start-Up Calibration 31 31 write-only value1 No action #0 value2 Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL) #1 ACCPROT0 Access Protection Register 0x0088 32 0x00000000 0xFFFFFFFF APC0 Access Protection Channel Control, Group 0 - 1 0 0 read-write value1 Full access to registers #0 value2 Write access to channel control registers is blocked #1 APC1 Access Protection Channel Control, Group 0 - 1 1 1 read-write value1 Full access to registers #0 value2 Write access to channel control registers is blocked #1 APEM Access Protection External Multiplexer 15 15 read-write value1 Full access to registers #0 value2 Write access to external multiplexer registers is blocked #1 API0 Access Protection Initialization, Group 0 - 1 16 16 read-write value1 Full access to registers #0 value2 Write access to initialization registers is blocked #1 API1 Access Protection Initialization, Group 0 - 1 17 17 read-write value1 Full access to registers #0 value2 Write access to initialization registers is blocked #1 APGC Access Protection Global Configuration 31 31 read-write value1 Full access to register #0 value2 Write access to global configuration register is blocked #1 ACCPROT1 Access Protection Register 0x008C 32 0x00000000 0xFFFFFFFF APS0 Access Protection Service Request, Group 0 - 1 0 0 read-write value1 Full access to registers #0 value2 Write access to service request registers is blocked #1 APS1 Access Protection Service Request, Group 0 - 1 1 1 read-write value1 Full access to registers #0 value2 Write access to service request registers is blocked #1 APTF Access Protection Test Function 15 15 read-write value1 Full access to register #0 value2 Write access to test function register is blocked #1 APR0 Access Protection Result Registers, Group 0 - 1 16 16 read-write value1 Full access to registers #0 value2 Write access to result registers is blocked #1 APR1 Access Protection Result Registers, Group 0 - 1 17 17 read-write value1 Full access to registers #0 value2 Write access to result registers is blocked #1 2 4 GLOBICLASS[%s] Input Class Register, Global 0x00A0 32 0x00000000 0xFFFFFFFF STCS Sample Time Control for Standard Conversions 0 4 read-write CMS Conversion Mode for Standard Conversions 8 10 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 STCE Sample Time Control for EMUX Conversions 16 20 read-write CME Conversion Mode for EMUX Conversions 24 26 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 GLOBBOUND Global Boundary Select Register 0x00B8 32 0x00000000 0xFFFFFFFF BOUNDARY0 Boundary Value 0 for Limit Checking 0 11 read-write BOUNDARY1 Boundary Value 1 for Limit Checking 16 27 read-write GLOBEFLAG Global Event Flag Register 0x00E0 32 0x00000000 0xFFFFFFFF SEVGLB Source Event (Background) 0 0 read-write value1 No source event #0 value2 A source event has occurred #1 REVGLB Global Result Event 8 8 read-write value1 No result event #0 value2 New result was stored in register GLOBRES #1 SEVGLBCLR Clear Source Event (Background) 16 16 write-only value1 No action #0 value2 Clear the source event flag SEVGLB #1 REVGLBCLR Clear Global Result Event 24 24 write-only value1 No action #0 value2 Clear the result event flag REVGLB #1 GLOBEVNP Global Event Node Pointer Register 0x0140 32 0x00000000 0xFFFFFFFF SEV0NP Service Request Node Pointer Backgr. Source 0 3 read-write value1 Select shared service request line 0 of common service request group 0 #0000 value2 Select shared service request line 3 of common service request group 0 #0011 REV0NP Service Request Node Pointer Global Result 16 19 read-write value1 Select shared service request line 0 of common service request group 0 #0000 value2 Select shared service request line 3 of common service request group 0 #0011 2 4 BRSSEL[%s] Background Request Source Channel Select Register 0x0180 32 0x00000000 0xFFFFFFFF CHSELG0 Channel Selection Group x 0 0 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG1 Channel Selection Group x 1 1 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG2 Channel Selection Group x 2 2 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG3 Channel Selection Group x 3 3 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG4 Channel Selection Group x 4 4 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG5 Channel Selection Group x 5 5 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG6 Channel Selection Group x 6 6 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSELG7 Channel Selection Group x 7 7 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 2 4 BRSPND[%s] Background Request Source Pending Register 0x01C0 32 0x00000000 0xFFFFFFFF CHPNDG0 Channels Pending Group x 0 0 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG1 Channels Pending Group x 1 1 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG2 Channels Pending Group x 2 2 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG3 Channels Pending Group x 3 3 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG4 Channels Pending Group x 4 4 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG5 Channels Pending Group x 5 5 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG6 Channels Pending Group x 6 6 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPNDG7 Channels Pending Group x 7 7 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 BRSCTRL Background Request Source Control Register 0x0200 32 0x00000000 0xFFFFFFFF SRCRESREG Source-specific Result Register 0 3 read-write value1 Use GxCHCTRy.RESREG to select a group result register #0000 value2 Store result in group result register GxRES1 #0001 value3 Store result in group result register GxRES15 #1111 XTSEL External Trigger Input Selection 8 11 read-write XTLVL External Trigger Level 12 12 read-only XTMODE Trigger Operating Mode 13 14 read-write value1 No external trigger #00 value2 Trigger event upon a falling edge #01 value3 Trigger event upon a rising edge #10 value4 Trigger event upon any edge #11 XTWC Write Control for Trigger Configuration 15 15 write-only value1 No write access to trigger configuration #0 value2 Bitfields XTMODE and XTSEL can be written #1 GTSEL Gate Input Selection 16 19 read-write GTLVL Gate Input Level 20 20 read-only GTWC Write Control for Gate Configuration 23 23 write-only value1 No write access to gate configuration #0 value2 Bitfield GTSEL can be written #1 BRSMR Background Request Source Mode Register 0x0204 32 0x00000000 0xFFFFFFFF ENGT Enable Gate 0 1 read-write value1 No conversion requests are issued #00 value2 Conversion requests are issued if at least one pending bit is set #01 value3 Conversion requests are issued if at least one pending bit is set and REQGTx = 1. #10 value4 Conversion requests are issued if at least one pending bit is set and REQGTx = 0. #11 ENTR Enable External Trigger 2 2 read-write value1 External trigger disabled #0 value2 The selected edge at the selected trigger input signal REQTR generates the load event #1 ENSI Enable Source Interrupt 3 3 read-write value1 No request source interrupt #0 value2 A request source interrupt is generated upon a request source event (last pending conversion is finished) #1 SCAN Autoscan Enable 4 4 read-write value1 No autoscan #0 value2 Autoscan functionality enabled: a request source event automatically generates a load event #1 LDM Autoscan Source Load Event Mode 5 5 read-write value1 Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event #0 value2 Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) #1 REQGT Request Gate Level 7 7 read-only value1 The gate input is low #0 value2 The gate input is high #1 CLRPND Clear Pending Bits 8 8 write-only value1 No action #0 value2 The bits in registers BRSPNDx are cleared #1 LDEV Generate Load Event 9 9 write-only value1 No action #0 value2 A load event is generated #1 RPTDIS Repeat Disable 16 16 read-write value1 A cancelled conversion is repeated #0 value2 A cancelled conversion is discarded #1 GLOBRCR Global Result Control Register 0x0280 32 0x00000000 0xFFFFFFFF DRCTR Data Reduction Control 16 19 read-write value1 Data reduction disabled #0000 WFR Wait-for-Read Mode Enable 24 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 SRGEN Service Request Generation Enable 31 31 read-write value1 No service request #0 value2 Service request after a result event #1 GLOBRES Global Result Register 0x0300 32 0x00000000 0xFFFFFFFF modifyExternal RESULT Result of most recent conversion 0 15 read-write GNR Group Number 16 19 read-only CHNR Channel Number 20 24 read-only EMUX External Multiplexer Setting 25 27 read-only CRS Converted Request Source 28 29 read-only FCR Fast Compare Result 30 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 VF Valid Flag 31 31 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) #1 GLOBRESD Global Result Register, Debug 0x0380 32 0x00000000 0xFFFFFFFF RESULT Result of most recent conversion 0 15 read-write GNR Group Number 16 19 read-only CHNR Channel Number 20 24 read-only EMUX External Multiplexer Setting 25 27 read-only CRS Converted Request Source 28 29 read-only FCR Fast Compare Result 30 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 VF Valid Flag 31 31 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action) #1 EMUXSEL External Multiplexer Select Register 0x03F0 32 0x00000000 0xFFFFFFFF EMUXGRP0 External Multiplexer Group for Interface x 0 3 read-write EMUXGRP1 External Multiplexer Group for Interface x 4 7 read-write VADC_G0 Analog to Digital Converter VADC VADC_G 0x48030400 0x0 0x0400 registers VADC0_G0_0 Analog to Digital Converter Group 0 17 VADC0_G0_1 Analog to Digital Converter Group 0 18 ARBCFG Arbitration Configuration Register 0x0080 32 0x00000000 0xFFFFFFFF ANONC Analog Converter Control 0 1 read-write ARBRND Arbitration Round Length 4 5 read-write value1 4 arbitration slots per round (tARB = 4 / fADCD) #00 value2 8 arbitration slots per round (tARB = 8 / fADCD) #01 value3 16 arbitration slots per round (tARB = 16 / fADCD) #10 value4 20 arbitration slots per round (tARB = 20 / fADCD) #11 ARBM Arbitration Mode 7 7 read-write value1 The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). #0 value2 The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. #1 ANONS Analog Converter Control Status 16 17 read-only value1 Analog converter off #00 value3 Slow standby mode #10 value4 Normal operation (permanently on) #11 CSRC Currently Converted Request Source 18 19 read-only value1 Current/last conversion for request source 0 #00 value2 Current/last conversion for request source 1 #01 value3 Current/last conversion for background source #10 value4 Current/last conversion for synchronization request (slave converter) #11 CHNR Channel Number 20 24 read-only SYNRUN Synchronous Conversion Running 25 25 read-only value1 Normal conversion or no conversion running #0 value2 A synchronized conversion is running (cannot be cancelled by higher priority requests!) #1 CAL Start-Up Calibration Active Indication 28 28 read-only value1 Completed or not yet started #0 value2 Start-up calibration phase is active (set one clock cycle after setting bit SUCAL) #1 CALS Start-Up Calibration Started 29 29 read-only value1 Requested but not yet started #0 value2 Start-up calibration has begun #1 BUSY Converter Busy Flag 30 30 read-only value1 Not busy #0 value2 Converter is busy with a conversion #1 SAMPLE Sample Phase Flag 31 31 read-only value1 Converting or idle #0 value2 Input signal is currently sampled #1 ARBPR Arbitration Priority Register 0x0084 32 0x00000000 0xFFFFFFFF PRIO0 Priority of Request Source x 0 1 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 PRIO1 Priority of Request Source x 4 5 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 PRIO2 Priority of Request Source x 8 9 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 CSM0 Conversion Start Mode of Request Source x 3 3 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 CSM1 Conversion Start Mode of Request Source x 7 7 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 CSM2 Conversion Start Mode of Request Source x 11 11 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 ASEN0 Arbitration Slot 0 Enable 24 24 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 ASEN1 Arbitration Slot 1 Enable 25 25 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 ASEN2 Arbitration Slot 2 Enable 26 26 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 CHASS Channel Assignment Register 0x0088 32 0x00000000 0xFFFFFFFF ASSCH0 Assignment for Channel 0 0 0 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH1 Assignment for Channel 1 1 1 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH2 Assignment for Channel 2 2 2 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH3 Assignment for Channel 3 3 3 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH4 Assignment for Channel 4 4 4 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH5 Assignment for Channel 5 5 5 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH6 Assignment for Channel 6 6 6 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH7 Assignment for Channel 7 7 7 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 RRASS Result Assignment Register 0x008C 32 0x00000000 0xFFFFFFFF ASSRR0 Assignment for Result Register 0 0 0 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR1 Assignment for Result Register 1 1 1 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR2 Assignment for Result Register 2 2 2 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR3 Assignment for Result Register 3 3 3 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR4 Assignment for Result Register 4 4 4 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR5 Assignment for Result Register 5 5 5 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR6 Assignment for Result Register 6 6 6 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR7 Assignment for Result Register 7 7 7 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR8 Assignment for Result Register 8 8 8 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR9 Assignment for Result Register 9 9 9 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR10 Assignment for Result Register 10 10 10 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR11 Assignment for Result Register 11 11 11 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR12 Assignment for Result Register 12 12 12 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR13 Assignment for Result Register 13 13 13 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR14 Assignment for Result Register 14 14 14 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 ASSRR15 Assignment for Result Register 15 15 15 read-write value1 Result register y can also be written by the background source #0 value2 Result register y can only be written by sources within group x #1 2 4 ICLASS[%s] Input Class Register 0 0x00A0 32 0x00000000 0xFFFFFFFF STCS Sample Time Control for Standard Conversions 0 4 read-write CMS Conversion Mode for Standard Conversions 8 10 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 STCE Sample Time Control for EMUX Conversions 16 20 read-write CME Conversion Mode for EMUX Conversions 24 26 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 ALIAS Alias Register 0x00B0 32 0x00000100 0xFFFFFFFF ALIAS0 Alias Value for CH0 Conversion Requests 0 4 read-write ALIAS1 Alias Value for CH1 Conversion Requests 8 12 read-write BOUND Boundary Select Register 0x00B8 32 0x00000000 0xFFFFFFFF BOUNDARY0 Boundary Value 0 for Limit Checking 0 11 read-write BOUNDARY1 Boundary Value 1 for Limit Checking 16 27 read-write SYNCTR Synchronization Control Register 0x00C0 32 0x00000000 0xFFFFFFFF STSEL Start Selection 0 1 read-write value1 Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC #00 value2 Kernel is synchronization slave: Control information from input CI1 #01 EVALR1 Evaluate Ready Input R1 4 4 read-write value1 No ready input control #0 value2 Ready input R1 is considered for the start of a parallel conversion of this conversion group #1 BFL Boundary Flag Register 0x00C8 32 0x00000000 0xFFFFFFFF BFL0 Boundar0 Flag y 0 0 read-only value1 Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL1 Boundar1 Flag y 1 1 read-only value1 Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL2 Boundar2 Flag y 2 2 read-only value1 Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL3 Boundar3 Flag y 3 3 read-only value1 Passive state: result has not yet crossed the activation boundary (see bitfield BFAy), or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFA0 Boundar0 Flag y Activation Select 8 8 read-write value1 Set boundary flag BFLy if result is above the defined band or compare value, clear if below #0 value2 Set boundary flag BFLy if result is below the defined band or compare value, clear if above #1 BFA1 Boundar1 Flag y Activation Select 9 9 read-write value1 Set boundary flag BFLy if result is above the defined band or compare value, clear if below #0 value2 Set boundary flag BFLy if result is below the defined band or compare value, clear if above #1 BFA2 Boundar2 Flag y Activation Select 10 10 read-write value1 Set boundary flag BFLy if result is above the defined band or compare value, clear if below #0 value2 Set boundary flag BFLy if result is below the defined band or compare value, clear if above #1 BFA3 Boundar3 Flag y Activation Select 11 11 read-write value1 Set boundary flag BFLy if result is above the defined band or compare value, clear if below #0 value2 Set boundary flag BFLy if result is below the defined band or compare value, clear if above #1 BFI0 Boundar0 Flag y Inversion Control 16 16 read-write value1 Use BFLy directly #0 value2 Invert value and use BFLy #1 BFI1 Boundar1 Flag y Inversion Control 17 17 read-write value1 Use BFLy directly #0 value2 Invert value and use BFLy #1 BFI2 Boundar2 Flag y Inversion Control 18 18 read-write value1 Use BFLy directly #0 value2 Invert value and use BFLy #1 BFI3 Boundar3 Flag y Inversion Control 19 19 read-write value1 Use BFLy directly #0 value2 Invert value and use BFLy #1 BFLS Boundary Flag Software Register 0x00CC 32 0x00000000 0xFFFFFFFF BFC0 Boundar0 Flag y Clear 0 0 write-only value1 No action #0 value2 Clear bit BFLy #1 BFC1 Boundar1 Flag y Clear 1 1 write-only value1 No action #0 value2 Clear bit BFLy #1 BFC2 Boundar2 Flag y Clear 2 2 write-only value1 No action #0 value2 Clear bit BFLy #1 BFC3 Boundar3 Flag y Clear 3 3 write-only value1 No action #0 value2 Clear bit BFLy #1 BFS0 Boundar0 Flag y Set 16 16 write-only value1 No action #0 value2 Set bit BFLy #1 BFS1 Boundar1 Flag y Set 17 17 write-only value1 No action #0 value2 Set bit BFLy #1 BFS2 Boundar2 Flag y Set 18 18 write-only value1 No action #0 value2 Set bit BFLy #1 BFS3 Boundar3 Flag y Set 19 19 write-only value1 No action #0 value2 Set bit BFLy #1 BFLC Boundary Flag Control Register 0x00D0 32 0x00000000 0xFFFFFFFF BFM0 Boundary Flag y Mode Control 0 3 read-write value1 Disable boundary flag, BFLy is not changed #0000 value2 Always enable boundary flag (follow compare results) #0001 value3 Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive #0010 value4 Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive #0011 BFM1 Boundary Flag y Mode Control 4 7 read-write value1 Disable boundary flag, BFLy is not changed #0000 value2 Always enable boundary flag (follow compare results) #0001 value3 Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive #0010 value4 Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive #0011 BFM2 Boundary Flag y Mode Control 8 11 read-write value1 Disable boundary flag, BFLy is not changed #0000 value2 Always enable boundary flag (follow compare results) #0001 value3 Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive #0010 value4 Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive #0011 BFM3 Boundary Flag y Mode Control 12 15 read-write value1 Disable boundary flag, BFLy is not changed #0000 value2 Always enable boundary flag (follow compare results) #0001 value3 Enable boundary flag while gate of source 0 is active, clear BFLy while gate is inactive #0010 value4 Enable boundary flag while gate of source 1 is active, clear BFLy while gate is inactive #0011 BFLNP Boundary Flag Node Pointer Register 0x00D4 32 0x0000FFFF 0xFFFFFFFF BFL0NP Boundary Flag y Node Pointer 0 3 read-write value1 Select common bondary flag output 0 #0000 value2 Select common bondary flag output 3 #0011 value3 Select common service request line C0SR0 #0100 value4 Select common service request line C0SR3 #0111 value5 Disabled, no common output signal #1111 BFL1NP Boundary Flag y Node Pointer 4 7 read-write value1 Select common bondary flag output 0 #0000 value2 Select common bondary flag output 3 #0011 value3 Select common service request line C0SR0 #0100 value4 Select common service request line C0SR3 #0111 value5 Disabled, no common output signal #1111 BFL2NP Boundary Flag y Node Pointer 8 11 read-write value1 Select common bondary flag output 0 #0000 value2 Select common bondary flag output 3 #0011 value3 Select common service request line C0SR0 #0100 value4 Select common service request line C0SR3 #0111 value5 Disabled, no common output signal #1111 BFL3NP Boundary Flag y Node Pointer 12 15 read-write value1 Select common bondary flag output 0 #0000 value2 Select common bondary flag output 3 #0011 value3 Select common service request line C0SR0 #0100 value4 Select common service request line C0SR3 #0111 value5 Disabled, no common output signal #1111 QCTRL0 Queue 0 Source Control Register 0x0100 32 0x00000000 0xFFFFFFFF SRCRESREG Source-specific Result Register 0 3 read-write value1 Use GxCHCTRy.RESREG to select a group result register #0000 value2 Store result in group result register GxRES1 #0001 value3 Store result in group result register GxRES15 #1111 XTSEL External Trigger Input Selection 8 11 read-write XTLVL External Trigger Level 12 12 read-only XTMODE Trigger Operating Mode 13 14 read-write value1 No external trigger #00 value2 Trigger event upon a falling edge #01 value3 Trigger event upon a rising edge #10 value4 Trigger event upon any edge #11 XTWC Write Control for Trigger Configuration 15 15 write-only value1 No write access to trigger configuration #0 value2 Bitfields XTMODE and XTSEL can be written #1 GTSEL Gate Input Selection 16 19 read-write GTLVL Gate Input Level 20 20 read-only GTWC Write Control for Gate Configuration 23 23 write-only value1 No write access to gate configuration #0 value2 Bitfield GTSEL can be written #1 TMEN Timer Mode Enable 28 28 read-write value1 No timer mode: standard gating mechanism can be used #0 value2 Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled #1 TMWC Write Control for Timer Mode 31 31 write-only value1 No write access to timer mode #0 value2 Bitfield TMEN can be written #1 QMR0 Queue 0 Mode Register 0x0104 32 0x00000000 0xFFFFFFFF ENGT Enable Gate 0 1 read-write value1 No conversion requests are issued #00 value2 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register #01 value3 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 #10 value4 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 #11 ENTR Enable External Trigger 2 2 read-write value1 External trigger disabled #0 value2 The selected edge at the selected trigger input signal REQTR generates the trigger event #1 CLRV Clear Valid Bit 8 8 write-only value1 No action #0 value2 The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. #1 TREV Trigger Event 9 9 write-only value1 No action #0 value2 Generate a trigger event by software #1 FLUSH Flush Queue 10 10 write-only value1 No action #0 value2 Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. #1 CEV Clear Event Flag 11 11 write-only value1 No action #0 value2 Clear bit EV #1 RPTDIS Repeat Disable 16 16 read-write value1 A cancelled conversion is repeated #0 value2 A cancelled conversion is discarded #1 QSR0 Queue 0 Status Register 0x0108 32 0x00000020 0xFFFFFFFF FILL Filling Level for Queue 2 0 3 read-only value1 There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue #0000 value2 There are 2 valid entries in the queue #0001 value3 There are 3 valid entries in the queue #0010 value4 There are 8 valid entries in the queue #0111 EMPTY Queue Empty 5 5 read-only value1 There are valid entries in the queue (see FILL) #0 value2 No valid entries (queue is empty) #1 REQGT Request Gate Level 7 7 read-only value1 The gate input is low #0 value2 The gate input is high #1 EV Event Detected 8 8 read-only value1 No trigger event #0 value2 A trigger event has been detected #1 Q0R0 Queue 0 Register 0 0x010C 32 0x00000000 0xFFFFFFFF REQCHNR Request Channel Number 0 4 read-only RF Refill 5 5 read-only value1 The request is discarded after the conversion start. #0 value2 The request is automatically refilled into the queue after the conversion start. #1 ENSI Enable Source Interrupt 6 6 read-only value1 No request source interrupt #0 value2 A request source event interrupt is generated upon a request source event (related conversion is finished) #1 EXTR External Trigger 7 7 read-only value1 A valid queue entry immediately leads to a conversion request #0 value2 The request handler waits for a trigger event #1 V Request Channel Number Valid 8 8 read-only value1 No valid queue entry #0 value2 The queue entry is valid and leads to a conversion request #1 QINR0 Queue 0 Input Register 0x0110 32 0x00000000 0xFFFFFFFF REQCHNR Request Channel Number 0 4 write-only RF Refill 5 5 write-only value1 No refill: this queue entry is converted once and then invalidated #0 value2 Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started #1 ENSI Enable Source Interrupt 6 6 write-only value1 No request source interrupt #0 value2 A request source event interrupt is generated upon a request source event (related conversion is finished) #1 EXTR External Trigger 7 7 write-only value1 A valid queue entry immediately leads to a conversion request. #0 value2 A valid queue entry waits for a trigger event to occur before issuing a conversion request. #1 QBUR0 Queue 0 Backup Register QINR0 0x0110 32 0x00000000 0xFFFFFFFF REQCHNR Request Channel Number 0 4 read-only RF Refill 5 5 read-only ENSI Enable Source Interrupt 6 6 read-only EXTR External Trigger 7 7 read-only V Request Channel Number Valid 8 8 read-only value1 Backup register not valid #0 value2 Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. #1 ASCTRL Autoscan Source Control Register 0x0120 32 0x00000000 0xFFFFFFFF SRCRESREG Source-specific Result Register 0 3 read-write value1 Use GxCHCTRy.RESREG to select a group result register #0000 value2 Store result in group result register GxRES1 #0001 value3 Store result in group result register GxRES15 #1111 XTSEL External Trigger Input Selection 8 11 read-write XTLVL External Trigger Level 12 12 read-only XTMODE Trigger Operating Mode 13 14 read-write value1 No external trigger #00 value2 Trigger event upon a falling edge #01 value3 Trigger event upon a rising edge #10 value4 Trigger event upon any edge #11 XTWC Write Control for Trigger Configuration 15 15 write-only value1 No write access to trigger configuration #0 value2 Bitfields XTMODE and XTSEL can be written #1 GTSEL Gate Input Selection 16 19 read-write GTLVL Gate Input Level 20 20 read-only GTWC Write Control for Gate Configuration 23 23 write-only value1 No write access to gate configuration #0 value2 Bitfield GTSEL can be written #1 TMEN Timer Mode Enable 28 28 read-write value1 No timer mode: standard gating mechanism can be used #0 value2 Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled #1 TMWC Write Control for Timer Mode 31 31 write-only value1 No write access to timer mode #0 value2 Bitfield TMEN can be written #1 ASMR Autoscan Source Mode Register 0x0124 32 0x00000000 0xFFFFFFFF ENGT Enable Gate 0 1 read-write value1 No conversion requests are issued #00 value2 Conversion requests are issued if at least one pending bit is set #01 value3 Conversion requests are issued if at least one pending bit is set and REQGTx = 1. #10 value4 Conversion requests are issued if at least one pending bit is set and REQGTx = 0. #11 ENTR Enable External Trigger 2 2 read-write value1 External trigger disabled #0 value2 The selected edge at the selected trigger input signal REQTR generates the load event #1 ENSI Enable Source Interrupt 3 3 read-write value1 No request source interrupt #0 value2 A request source interrupt is generated upon a request source event (last pending conversion is finished) #1 SCAN Autoscan Enable 4 4 read-write value1 No autoscan #0 value2 Autoscan functionality enabled: a request source event automatically generates a load event #1 LDM Autoscan Source Load Event Mode 5 5 read-write value1 Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event #0 value2 Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) #1 REQGT Request Gate Level 7 7 read-only value1 The gate input is low #0 value2 The gate input is high #1 CLRPND Clear Pending Bits 8 8 write-only value1 No action #0 value2 The bits in register GxASPNDx are cleared #1 LDEV Generate Load Event 9 9 write-only value1 No action #0 value2 A load event is generated #1 RPTDIS Repeat Disable 16 16 read-write value1 A cancelled conversion is repeated #0 value2 A cancelled conversion is discarded #1 ASSEL Autoscan Source Channel Select Register 0x0128 32 0x00000000 0xFFFFFFFF CHSEL0 Channel Selection 0 0 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL1 Channel Selection 1 1 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL2 Channel Selection 2 2 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL3 Channel Selection 3 3 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL4 Channel Selection 4 4 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL5 Channel Selection 5 5 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL6 Channel Selection 6 6 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL7 Channel Selection 7 7 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 ASPND Autoscan Source Pending Register 0x012C 32 0x00000000 0xFFFFFFFF CHPND0 Channels Pending 0 0 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND1 Channels Pending 1 1 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND2 Channels Pending 2 2 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND3 Channels Pending 3 3 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND4 Channels Pending 4 4 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND5 Channels Pending 5 5 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND6 Channels Pending 6 6 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND7 Channels Pending 7 7 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CEFLAG Channel Event Flag Register 0x0180 32 0x00000000 0xFFFFFFFF CEV0 Channel Event for Channel 0 0 0 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV1 Channel Event for Channel 1 1 1 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV2 Channel Event for Channel 2 2 2 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV3 Channel Event for Channel 3 3 3 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV4 Channel Event for Channel 4 4 4 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV5 Channel Event for Channel 5 5 5 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV6 Channel Event for Channel 6 6 6 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV7 Channel Event for Channel 7 7 7 read-write value1 No channel event #0 value2 A channel event has occurred #1 REFLAG Result Event Flag Register 0x0184 32 0x00000000 0xFFFFFFFF REV0 Result Event for Result Register 0 0 0 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV1 Result Event for Result Register 1 1 1 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV2 Result Event for Result Register 2 2 2 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV3 Result Event for Result Register 3 3 3 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV4 Result Event for Result Register 4 4 4 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV5 Result Event for Result Register 5 5 5 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV6 Result Event for Result Register 6 6 6 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV7 Result Event for Result Register 7 7 7 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV8 Result Event for Result Register 8 8 8 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV9 Result Event for Result Register 9 9 9 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV10 Result Event for Result Register 10 10 10 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV11 Result Event for Result Register 11 11 11 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV12 Result Event for Result Register 12 12 12 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV13 Result Event for Result Register 13 13 13 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV14 Result Event for Result Register 14 14 14 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV15 Result Event for Result Register 15 15 15 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 SEFLAG Source Event Flag Register 0x0188 32 0x00000000 0xFFFFFFFF SEV0 Source Event 0/1 0 0 read-write value1 No source event #0 value2 A source event has occurred #1 SEV1 Source Event 0/1 1 1 read-write value1 No source event #0 value2 A source event has occurred #1 CEFCLR Channel Event Flag Clear Register 0x0190 32 0x00000000 0xFFFFFFFF CEV0 Clear Channel Event for Channel 0 0 0 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV1 Clear Channel Event for Channel 1 1 1 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV2 Clear Channel Event for Channel 2 2 2 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV3 Clear Channel Event for Channel 3 3 3 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV4 Clear Channel Event for Channel 4 4 4 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV5 Clear Channel Event for Channel 5 5 5 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV6 Clear Channel Event for Channel 6 6 6 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV7 Clear Channel Event for Channel 7 7 7 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 REFCLR Result Event Flag Clear Register 0x0194 32 0x00000000 0xFFFFFFFF REV0 Clear Result Event for Result Register 0 0 0 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV1 Clear Result Event for Result Register 1 1 1 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV2 Clear Result Event for Result Register 2 2 2 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV3 Clear Result Event for Result Register 3 3 3 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV4 Clear Result Event for Result Register 4 4 4 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV5 Clear Result Event for Result Register 5 5 5 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV6 Clear Result Event for Result Register 6 6 6 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV7 Clear Result Event for Result Register 7 7 7 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV8 Clear Result Event for Result Register 8 8 8 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV9 Clear Result Event for Result Register 9 9 9 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV10 Clear Result Event for Result Register 10 10 10 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV11 Clear Result Event for Result Register 11 11 11 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV12 Clear Result Event for Result Register 12 12 12 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV13 Clear Result Event for Result Register 13 13 13 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV14 Clear Result Event for Result Register 14 14 14 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV15 Clear Result Event for Result Register 15 15 15 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 SEFCLR Source Event Flag Clear Register 0x0198 32 0x00000000 0xFFFFFFFF SEV0 Clear Source Event 0/1 0 0 write-only value1 No action #0 value2 Clear the source event flag in GxSEFLAG #1 SEV1 Clear Source Event 0/1 1 1 write-only value1 No action #0 value2 Clear the source event flag in GxSEFLAG #1 CEVNP0 Channel Event Node Pointer Register 0 0x01A0 32 0x00000000 0xFFFFFFFF CEV0NP Service Request Node Pointer Channel Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV1NP Service Request Node Pointer Channel Event i 4 7 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV2NP Service Request Node Pointer Channel Event i 8 11 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV3NP Service Request Node Pointer Channel Event i 12 15 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV4NP Service Request Node Pointer Channel Event i 16 19 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV5NP Service Request Node Pointer Channel Event i 20 23 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV6NP Service Request Node Pointer Channel Event i 24 27 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV7NP Service Request Node Pointer Channel Event i 28 31 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REVNP0 Result Event Node Pointer Register 0 0x01B0 32 0x00000000 0xFFFFFFFF REV0NP Service Request Node Pointer Result Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV1NP Service Request Node Pointer Result Event i 4 7 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV2NP Service Request Node Pointer Result Event i 8 11 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV3NP Service Request Node Pointer Result Event i 12 15 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV4NP Service Request Node Pointer Result Event i 16 19 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV5NP Service Request Node Pointer Result Event i 20 23 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV6NP Service Request Node Pointer Result Event i 24 27 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV7NP Service Request Node Pointer Result Event i 28 31 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REVNP1 Result Event Node Pointer Register 1 0x01B4 32 0x00000000 0xFFFFFFFF REV8NP Service Request Node Pointer Result Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV9NP Service Request Node Pointer Result Event i 4 7 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV10NP Service Request Node Pointer Result Event i 8 11 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV11NP Service Request Node Pointer Result Event i 12 15 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV12NP Service Request Node Pointer Result Event i 16 19 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV13NP Service Request Node Pointer Result Event i 20 23 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV14NP Service Request Node Pointer Result Event i 24 27 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV15NP Service Request Node Pointer Result Event i 28 31 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SEVNP Source Event Node Pointer Register 0x01C0 32 0x00000000 0xFFFFFFFF SEV0NP Service Request Node Pointer Source Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SEV1NP Service Request Node Pointer Source Event i 4 7 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SRACT Service Request Software Activation Trigger 0x01C8 32 0x00000000 0xFFFFFFFF AGSR0 Activate Group Service Request Node 0 0 0 write-only value1 No action #0 value2 Activate the associated service request line #1 AGSR1 Activate Group Service Request Node 1 1 1 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR0 Activate Shared Service Request Node 0 8 8 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR1 Activate Shared Service Request Node 1 9 9 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR2 Activate Shared Service Request Node 2 10 10 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR3 Activate Shared Service Request Node 3 11 11 write-only value1 No action #0 value2 Activate the associated service request line #1 EMUXCTR E0ternal Multiplexer Control Register, Group x 0x01F0 32 0x00000000 0xFFFFFFFF EMUXSET External Multiplexer Start Selection 0 2 read-write EMUXACT External Multiplexer Actual Selection 8 10 read-only EMUXCH External Multiplexer Channel Select 16 25 read-write EMUXMODE External Multiplexer Mode 26 27 read-write value1 Software control (no hardware action) #00 value2 Steady mode (use EMUXSET value) #01 value3 Single-step mode #10 value4 Sequence mode #11 EMXCOD External Multiplexer Coding Scheme 28 28 read-write value1 Output the channel number in binary code #0 value2 Output the channel number in Gray code #1 EMXST External Multiplexer Sample Time Control 29 29 read-write value1 Use STCE whenever the setting changes #0 value2 Use STCE for each conversion of an external channel #1 EMXCSS External Multiplexer Channel Selection Style 30 30 read-write value1 Channel number: Bitfield EMUXCH selects an arbitrary channel #0 value2 Channel enable: Each bit of bitfield EMUXCH selects the associated channel for EMUX control #1 EMXWC Write Control for EMUX Configuration 31 31 write-only value1 No write access to EMUX cfg. #0 value2 Bitfields EMXMODE, EMXCOD, EMXST, EMXCSS can be written #1 VFR Valid Flag Register, Group 0 0x01F8 32 0x00000000 0xFFFFFFFF VF0 Valid Flag of Result Register x 0 0 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF1 Valid Flag of Result Register x 1 1 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF2 Valid Flag of Result Register x 2 2 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF3 Valid Flag of Result Register x 3 3 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF4 Valid Flag of Result Register x 4 4 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF5 Valid Flag of Result Register x 5 5 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF6 Valid Flag of Result Register x 6 6 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF7 Valid Flag of Result Register x 7 7 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF8 Valid Flag of Result Register x 8 8 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF9 Valid Flag of Result Register x 9 9 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF10 Valid Flag of Result Register x 10 10 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF11 Valid Flag of Result Register x 11 11 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF12 Valid Flag of Result Register x 12 12 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF13 Valid Flag of Result Register x 13 13 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF14 Valid Flag of Result Register x 14 14 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF15 Valid Flag of Result Register x 15 15 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 8 4 CHCTR[%s] Channel Ctrl. Reg. 0x0200 32 0x00000000 0xFFFFFFFF ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 BNDSELL Lower Boundary Select 4 5 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 7 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 CHEVMODE Channel Event Mode 8 9 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 SYNC Synchronization Request 10 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 REFSEL Reference Input Selection 11 11 read-write value1 Standard reference Ground VSS #0 value2 Alternate reference Ground from CH0 #1 BNDSELX BoundaryExtension 12 15 read-write value1 Standard mode: select boundaries via BNDSELU/BNDSELL #0000 value2 Use result reg. GxRES1 as upper boundary #0001 value3 Use result reg. GxRES15 as upper boundary #1111 RESREG Result Register 16 19 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 RESPOS Result Position 21 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 BWDCH Broken Wire Detection Channel 28 29 read-write value1 Select VAREF #00 value2 Select VAGND #01 BWDEN Broken Wire Detection Enable 30 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 16 4 RCR[%s] Result Control Reg. 0x0280 32 0x00000000 0xFFFFFFFF DRCTR Data Reduction Control 16 19 read-write DMM Data Modification Mode 20 21 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 WFR Wait-for-Read Mode Enable 24 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 FEN FIFO Mode Enable 25 26 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 value3 Maximum mode: copy new result if bigger #10 value4 Minimum mode: copy new result if smaller #11 SRGEN Service Request Generation Enable 31 31 read-write value1 No service request #0 value2 Service request after a result event #1 16 4 RES[%s] Result Register 0x0300 32 0x00000000 0xFFFFFFFF modifyExternal RESULT Result of Most Recent Conversion 0 15 read-write DRC Data Reduction Counter 16 19 read-only CHNR Channel Number 20 24 read-only EMUX External Multiplexer Setting 25 27 read-only CRS Converted Request Source 28 29 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 FCR Fast Compare Result 30 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 VF Valid Flag 31 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 16 4 RESD[%s] Result Register, Debug 0x0380 32 0x00000000 0xFFFFFFFF RESULT Result of Most Recent Conversion 0 15 read-only DRC Data Reduction Counter 16 19 read-only CHNR Channel Number 20 24 read-only EMUX External Multiplexer Setting 25 27 read-only CRS Converted Request Source 28 29 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 FCR Fast Compare Result 30 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 VF Valid Flag 31 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 VADC_G1 Analog to Digital Converter VADC 0x48030800 0x0 0x0400 registers VADC0_G1_0 Analog to Digital Converter Group 1 19 VADC0_G1_1 Analog to Digital Converter Group 1 20 SHS0 Sample and Hold ADC Sequencer SHS 0x48034000 0x0 0x0200 registers ID Module Identification Register 0x0008 32 0x0099C000 0xFFFFFF00 MOD_REV Module Revision 0 7 read-only MOD_TYPE Module Type 8 15 read-only MOD_NUMBER Module Number 16 31 read-only SHSCFG SHS Configuration Register 0x0040 32 0x00000000 0xFFFFFFFF DIVS Divider Factor for the SHS Clock 0 3 read-write value1 fSH = fCONV / 1 #0000 value2 fSH = fCONV / 2 #0001 value3 fSH = fCONV / 16 #1111 AREF Analog Reference Voltage Selection 10 11 read-write value1 External reference, upper supply range #00 value3 Internal reference, upper supply range #10 value4 Internal reference, lower supply range #11 ANOFF Analog Converter Power Down Force 12 12 read-write value1 Converter controlled by bitfields ANONS (digital control block) #0 value2 Converter is permanently off #1 ANRDY Analog Converter Ready 14 14 read-only value1 Converter is in power-down mode #0 value2 Converter is operable #1 SCWC Write Control for SHS Configuration 15 15 write-only value1 No write access to SHS configuration #0 value2 Bitfields ANOFF, AREF, DIVS can be written #1 SP0 Sample Pending on S&H Unit x 16 16 read-only value1 No sample pending #0 value2 S&H unit x has finished the sample phase #1 SP1 Sample Pending on S&H Unit x 17 17 read-only value1 No sample pending #0 value2 S&H unit x has finished the sample phase #1 TC Test Control 24 27 read-write value1 Internal test functions enabled #1011 STATE Current State of Sequencer 28 31 read-only value1 Idle #0000 value2 Offset calibration active #0001 value3 Gain calibration active #0010 value4 Startup calibration active #0011 value5 Stepper process active for S&H unit 0 #1000 value6 Stepper process active for S&H unit 1 #1001 STEPCFG Stepper Configuration Register 0x0044 32 0x00000098 0xFFFFFFFF KSEL0 Kernel Select 0 2 read-write KSEL1 Kernel Select 4 6 read-write KSEL2 Kernel Select 8 10 read-write KSEL3 Kernel Select 12 14 read-write KSEL4 Kernel Select 16 18 read-write KSEL5 Kernel Select 20 22 read-write KSEL6 Kernel Select 24 26 read-write KSEL7 Kernel Select 28 30 read-write SEN0 Step x Enable 3 3 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN1 Step x Enable 7 7 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN2 Step x Enable 11 11 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN3 Step x Enable 15 15 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN4 Step x Enable 19 19 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN5 Step x Enable 23 23 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN6 Step x Enable 27 27 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 SEN7 Step x Enable 31 31 read-write value1 Off: This step is not part of the stepper sequence #0 value2 Active: This step is executed during the sequence #1 TIMCFG0 Timing Configuration Register 0 0x80 32 0x00000001 0xFFFFFFFF AT Accelerated Timing 0 0 read-write value1 Compatible timing: Result available after standard conversion time #0 value2 Accelerated timing: Result available as soon as converted #1 FCRT Fast Compare Mode Response Time 4 7 read-write value1 Result after tADCI * 2 0x0 value2 Result after tADCI * 32 0xF SST Short Sample Time 8 13 read-write value1 Compatible timing: Sample time is defined by DIVA and STC. 0x00 value2 Sample time is tADC * 1 0x01 value3 Sample time is tADC * 63 0x3F TGEN Timing Generator 16 29 read-only TIMCFG1 Timing Configuration Register 1 0x84 32 0x00000001 0xFFFFFFFF AT Accelerated Timing 0 0 read-write value1 Compatible timing: Result available after standard conversion time #0 value2 Accelerated timing: Result available as soon as converted #1 FCRT Fast Compare Mode Response Time 4 7 read-write value1 Result after tADCI * 2 0x0 value2 Result after tADCI * 32 0xF SST Short Sample Time 8 13 read-write value1 Compatible timing: Sample time is defined by DIVA and STC. 0x00 value2 Sample time is tADC * 1 0x01 value3 Sample time is tADC * 63 0x3F TGEN Timing Generator 16 29 read-only CALCTR Calibration Control Register 0x00BC 32 0x00100400 0xFFFFFFFF CALORD Calibration Order 0 0 read-write value1 Do conversions then calibration #0 value2 Do calibration then conversions #1 CALGNSTC Gain Calibration Sample Time Control 8 13 read-write SUCALVAL Startup Calibration Cycles 16 22 read-write CALMAX Calibration Maximum Timing 24 29 read-write SUCAL Start-Up Calibration 31 31 write-only value1 No action #0 value2 Initiate the start-up calibration phase (indication in bitfield SHSCFG.STATE) #1 CALGC0 Gain Calibration Control Register 0 0xC0 32 0x20002000 0xFFFFFFFF CALGNVALS Gain Calibration Value, Standard Reference 0 13 read-write GNSWC Gain Calibration Write Control, Standard 15 15 write-only value1 No write access to gain calibration parameter #0 value2 CALGNVALS can be written #1 CALGNVALA Gain Calibration Value, Alternate Reference 16 29 read-write GNAWC Gain Calibration Write Control, Alternate 31 31 write-only value1 No write access to gain calibration parameter #0 value2 CALGNVALA can be written #1 CALGC1 Gain Calibration Control Register 1 0xC4 32 0x20002000 0xFFFFFFFF CALGNVALS Gain Calibration Value, Standard Reference 0 13 read-write GNSWC Gain Calibration Write Control, Standard 15 15 write-only value1 No write access to gain calibration parameter #0 value2 CALGNVALS can be written #1 CALGNVALA Gain Calibration Value, Alternate Reference 16 29 read-write GNAWC Gain Calibration Write Control, Alternate 31 31 write-only value1 No write access to gain calibration parameter #0 value2 CALGNVALA can be written #1 CALOC0 Offset Calibration Control Register 0 0xE0 32 0x00000000 0xFFFFFFFF CALOFFVAL0 Offset Calibration Value for Gain Level z 0 6 read-write CALOFFVAL1 Offset Calibration Value for Gain Level z 8 14 read-write CALOFFVAL2 Offset Calibration Value for Gain Level z 16 22 read-write CALOFFVAL3 Offset Calibration Value for Gain Level z 24 30 read-write OFFWC Offset Calibration Write Control 15 15 write-only value1 No write access to offset cal. parameters #0 value2 CALOFFVALz can be written #1 DISCAL Disable Calibration 31 31 read-write value1 Calibration enabled (offset and gain) #0 value2 No calibration #1 CALOC1 Offset Calibration Control Register 1 0xE4 32 0x00000000 0xFFFFFFFF CALOFFVAL0 Offset Calibration Value for Gain Level z 0 6 read-write CALOFFVAL1 Offset Calibration Value for Gain Level z 8 14 read-write CALOFFVAL2 Offset Calibration Value for Gain Level z 16 22 read-write CALOFFVAL3 Offset Calibration Value for Gain Level z 24 30 read-write OFFWC Offset Calibration Write Control 15 15 write-only value1 No write access to offset cal. parameters #0 value2 CALOFFVALz can be written #1 DISCAL Disable Calibration 31 31 read-write value1 Calibration enabled (offset and gain) #0 value2 No calibration #1 GNCTR00 Gain Control Register 00 0x0180 32 0x00000000 0xFFFFFFFF GAIN0 Gain Control 0 0 3 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN1 Gain Control 1 4 7 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN2 Gain Control 2 8 11 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN3 Gain Control 3 12 15 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN4 Gain Control 4 16 19 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN5 Gain Control 5 20 23 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN6 Gain Control 6 24 27 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN7 Gain Control 7 28 31 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GNCTR10 Gain Control Register 10 0x0190 32 0x00000000 0xFFFFFFFF GAIN0 Gain Control 0 0 3 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN1 Gain Control 1 4 7 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN2 Gain Control 2 8 11 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN3 Gain Control 3 12 15 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN4 Gain Control 4 16 19 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN5 Gain Control 5 20 23 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN6 Gain Control 6 24 27 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 GAIN7 Gain Control 7 28 31 read-write value1 Gain factor = 1 #0000 value2 Gain factor = 3 #0001 value3 Gain factor = 6 #0010 value4 Gain factor = 12 #0011 LOOP Loop Control Register 0x0050 32 0x00000000 0xFFFFFFFF LPCH0 Loop y Channel 0 4 read-write LPCH1 Loop y Channel 16 20 read-write LPSH0 Loop y Sample&Hold Unit 8 8 read-write LPSH1 Loop y Sample&Hold Unit 24 24 read-write LPEN0 Loop y Enable 15 15 read-write value1 Off: standard operation 0x0 value2 ON: sigma-delta-loop is active 0x1 LPEN1 Loop y Enable 31 31 read-write value1 Off: standard operation 0x0 value2 ON: sigma-delta-loop is active 0x1 BCCU0 BCCU Unit 0 BCCU BCCU 0x50030000 0x0 0x3C registers BCCU0_0 Brightness and Color Control Unit 0 31 GLOBCON Global Control 0x00 32 0x03200000 0xFFFFFFFF TM Trigger Mode 0 0 read-write value1 Mode 0: BCCU trigger occurs if there is any channel trigger (OR logic) #0 value2 Mode 1: BCCU trigger occurs if there is a channel trigger event on the active channel. When this happens, the next trigger-enabled channel will be active following the round robin. #1 TRDEL Trigger Delay 2 3 read-write value1 No delay #00 value2 BCCU trigger occurs a quarter bit time after the channel trigger that caused it; only to be used if BCCU_GLOBCLK.BCS is 0 #01 value3 BCCU trigger occurs half a bit time after the channel trigger that caused it; only to be used if BCCU_GLOBCLK.BCS is 0 #10 value4 No delay #11 SUSCFG Suspend Mode Configuration 4 5 read-write value1 Suspend request is ignored and the module cannot get suspended #00 value2 All channels stop running immediately and freeze in the last state without any safe stop #01 value3 All channels stop running immediately and freeze in the last state; all outputs go to passive state to achieve safe stop #10 TRAPIS Trap Input Pin Selector 6 9 read-write value1 BCCU.TRAPINA #0000 value2 BCCU.TRAPINB #0001 value3 BCCU.TRAPINC #0010 value4 BCCU.TRAPIND #0011 value5 BCCU.TRAPINE #0100 value6 BCCU.TRAPINF #0101 value7 BCCU.TRAPING #0110 value8 BCCU.TRAPINH #0111 value9 BCCU.TRAPINI #1000 value10 BCCU.TRAPING #1001 value11 BCCU.TRAPINK #1010 value12 BCCU.TRAPINL #1011 value13 BCCU.TRAPINM #1100 value14 BCCU.TRAPINN #1101 value15 BCCU.TRAPINO #1110 value16 BCCU.TRAPINP #1111 TRAPED Trap Edge 10 10 read-write value1 Trap occurs (trap flag is set) on rising edge of the BCCU.TRAPL signal #0 value2 Trap occurs (trap flag is set) on falling edge of the BCCU.TRAPL signal #1 LTRS Last Trigger Source 12 15 read-only value1 The last trigger occurred in channel turn 0 #0000 value2 The last trigger occurred in channel turn 1 #0001 value3 The last trigger occurred in channel turn 2 #0010 value4 The last trigger occurred in channel turn 3 #0011 value5 The last trigger occurred in channel turn 4 #0100 value6 The last trigger occurred in channel turn 5 #0101 value7 The last trigger occurred in channel turn 6 #0110 value8 The last trigger occurred in channel turn 7 #0111 value9 The last trigger occurred in channel turn 8 #1000 WDMBN Watchdog Maximum Bitnumber 16 27 read-write GLOBCLK Global Clock 0x04 32 0x00DB0190 0xFFFFFFFF FCLK_PS Fast Clock Prescaler Factor 0 11 read-write value1 No clock 0 value2 Divide by 1 1 value3 Divide by 4095 4095 BCS Bit-Clock Selector 15 15 read-write value1 Normal Mode: BCCU_bclk is generated from BCCU_fclk by a division of 4 #0 value2 Fast Mode: BCCU_bclk is the same as BCCU_fclk #1 DCLK_PS Dimmer Clock Prescaler Factor 16 27 read-write value1 No clock 0 value2 Divide by 1 1 value3 Divide by 4095 4095 ID Module Identification 0x08 32 0x00F3C000 0xFFFFFF00 MOD_REV Module Revision Number 0 7 read-only MOD_TYPE0 Module Type 8 15 read-only MOD_NUMBER Module Number Value 16 31 read-only CHEN Channel Enable 0x0C 32 0x00000000 0xFFFFFFFF ECH0 Channel 0 Enable 0 0 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH1 Channel 1 Enable 1 1 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH2 Channel 2 Enable 2 2 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH3 Channel 3 Enable 3 3 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH4 Channel 4 Enable 4 4 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH5 Channel 5 Enable 5 5 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH6 Channel 6 Enable 6 6 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH7 Channel 7 Enable 7 7 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 ECH8 Channel 8 Enable 8 8 read-write value1 Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled #0 value2 Channel is enabled #1 CHOCON Channel Output Control 0x10 32 0x00000000 0xFFFFFFFF CH0OP Channel 0 Output Passive Level 0 0 read-write value1 Active high #0 value2 Active low #1 CH1OP Channel 1 Output Passive Level 1 1 read-write value1 Active high #0 value2 Active low #1 CH2OP Channel 2 Output Passive Level 2 2 read-write value1 Active high #0 value2 Active low #1 CH3OP Channel 3 Output Passive Level 3 3 read-write value1 Active high #0 value2 Active low #1 CH4OP Channel 4 Output Passive Level 4 4 read-write value1 Active high #0 value2 Active low #1 CH5OP Channel 5 Output Passive Level 5 5 read-write value1 Active high #0 value2 Active low #1 CH6OP Channel 6 Output Passive Level 6 6 read-write value1 Active high #0 value2 Active low #1 CH7OP Channel 7 Output Passive Level 7 7 read-write value1 Active high #0 value2 Active low #1 CH8OP Channel 8 Output Passive Level 8 8 read-write value1 Active high #0 value2 Active low #1 CH0TPE Channel 0 Trap Enable 16 16 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH1TPE Channel 1 Trap Enable 17 17 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH2TPE Channel 2 Trap Enable 18 18 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH3TPE Channel 3 Trap Enable 19 19 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH4TPE Channel 4 Trap Enable 20 20 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH5TPE Channel 5 Trap Enable 21 21 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH6TPE Channel 6 Trap Enable 22 22 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH7TPE Channel 7 Trap Enable 23 23 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CH8TPE Channel 8 Trap Enable 24 24 read-write value1 Trap function on channel is disabled #0 value2 Trap function on channel is enabled, the output goes to passive level when trap occurs #1 CHTRIG Channel Trigger 0x14 32 0x00000000 0xFFFFFFFF ET0 Channel 0 Trigger Enable 0 0 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET1 Channel 1 Trigger Enable 1 1 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET2 Channel 2 Trigger Enable 2 2 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET3 Channel 3 Trigger Enable 3 3 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET4 Channel 4 Trigger Enable 4 4 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET5 Channel 5 Trigger Enable 5 5 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET6 Channel 6 Trigger Enable 6 6 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET7 Channel 7 Trigger Enable 7 7 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 ET8 Channel 8 Trigger Enable 8 8 read-write value1 Channel trigger is disabled #0 value2 Channel trigger is enabled #1 TOS0 Channel 0 Trigger Output Select 16 16 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS1 Channel 1 Trigger Output Select 17 17 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS2 Channel 2 Trigger Output Select 18 18 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS3 Channel 3 Trigger Output Select 19 19 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS4 Channel 4 Trigger Output Select 20 20 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS5 Channel 5 Trigger Output Select 21 21 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS6 Channel 6 Trigger Output Select 22 22 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS7 Channel 7 Trigger Output Select 23 23 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 TOS8 Channel 8 Trigger Output Select 24 24 read-write value1 The channel trigger pulse will appear on BCCU_TRIGOUT0 #0 value2 The channel trigger pulse will appear on BCCU_TRIGOUT1 #1 CHSTRCON Channel Shadow Transfer 0x18 32 0x00000000 0xFFFFFFFF CH0S Channel 0 Shadow Transfer 0 0 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH1S Channel 1 Shadow Transfer 1 1 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH2S Channel 2 Shadow Transfer 2 2 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH3S Channel 3 Shadow Transfer 3 3 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH4S Channel 4 Shadow Transfer 4 4 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH5S Channel 5 Shadow Transfer 5 5 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH6S Channel 6 Shadow Transfer 6 6 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH7S Channel 7 Shadow Transfer 7 7 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH8S Channel 8 Shadow Transfer 8 8 read-write value1 No action #0 value2 Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached. #1 CH0A Channel 0 Linear Walk Abort 16 16 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH1A Channel 1 Linear Walk Abort 17 17 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH2A Channel 2 Linear Walk Abort 18 18 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH3A Channel 3 Linear Walk Abort 19 19 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH4A Channel 4 Linear Walk Abort 20 20 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH5A Channel 5 Linear Walk Abort 21 21 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH6A Channel 6 Linear Walk Abort 22 22 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH7A Channel 7 Linear Walk Abort 23 23 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 CH8A Channel 8 Linear Walk Abort 24 24 write-only value1 No action #0 value2 Abort linear walk; CHyS is cleared, channel y intensity stops changing #1 LTCHOL Last Trigger Channel Output Level 0x1C 32 0x00000000 0xFFFFFFFF LTOL0 Last Trigger Channel Output 0 0 read-only value1 Passive #0 value2 Active #1 LTOL1 Last Trigger Channel Output 1 1 read-only value1 Passive #0 value2 Active #1 LTOL2 Last Trigger Channel Output 2 2 read-only value1 Passive #0 value2 Active #1 LTOL3 Last Trigger Channel Output 3 3 read-only value1 Passive #0 value2 Active #1 LTOL4 Last Trigger Channel Output 4 4 read-only value1 Passive #0 value2 Active #1 LTOL5 Last Trigger Channel Output 5 5 read-only value1 Passive #0 value2 Active #1 LTOL6 Last Trigger Channel Output 6 6 read-only value1 Passive #0 value2 Active #1 LTOL7 Last Trigger Channel Output 7 7 read-only value1 Passive #0 value2 Active #1 LTOL8 Last Trigger Channel Output 8 8 read-only value1 Passive #0 value2 Active #1 DEEN Dimming Engine Enable 0x20 32 0x00000000 0xFFFFFFFF EDE0 Dimming Engine 0 Enable 0 0 read-write value1 Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled #0 value2 Dimming Engine is enabled #1 EDE1 Dimming Engine 1 Enable 1 1 read-write value1 Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled #0 value2 Dimming Engine is enabled #1 EDE2 Dimming Engine 2 Enable 2 2 read-write value1 Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled #0 value2 Dimming Engine is enabled #1 DESTRCON Dimming Shadow Transfer 0x24 32 0x00000000 0xFFFFFFFF DE0S Dimming Engine 0 Shadow Transfer 0 0 read-write value1 No action #0 value2 Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached. #1 DE1S Dimming Engine 1 Shadow Transfer 1 1 read-write value1 No action #0 value2 Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached. #1 DE2S Dimming Engine 2 Shadow Transfer 2 2 read-write value1 No action #0 value2 Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached. #1 DE0A Dimming Engine 0 Dimming Abort 16 16 write-only value1 No action #0 value2 Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing #1 DE1A Dimming Engine 1 Dimming Abort 17 17 write-only value1 No action #0 value2 Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing #1 DE2A Dimming Engine 2 Dimming Abort 18 18 write-only value1 No action #0 value2 Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing #1 GLOBDIM Global Dimming Level 0x28 32 0x00000000 0xFFFFFFFF GLOBDIM Global Dimming Level 0 11 read-write EVIER Event Interrupt Enable 0x2C 32 0x00000000 0xFFFFFFFF T0IEN Trigger 0 Interrupt Enable 0 0 read-write value1 Trigger 0 interrupt generation is disabled #0 value2 BCCU trigger 0 (BCCU_TRIGOUT0) generates an interrupt on SR0 #1 T1IEN Trigger 1 Interrupt Enable 1 1 read-write value1 Trigger 1 interrupt generation is disabled #0 value2 BCCU trigger 1 (BCCU_TRIGOUT1) generates an interrupt on SR0 #1 FIEN FIFO Full Interrupt Enable 2 2 read-write value1 FIFO-full interrupt generation is disabled #0 value2 An interrupt is generated on SR0 if any of the packer FIFOs is full when there is a write attempt by the on-time or off-time counter #1 EIEN FIFO Empty Interrupt Enable 3 3 read-write value1 FIFO-full interrupt generation is disabled #0 value2 An interrupt is generated on SR0 if any of the packer FIFOs is empty when there is a read attempt by the output generator #1 TPIEN Trap Interrupt Enable 4 4 read-write value1 Trap interrupt generation is disabled #0 value2 An interrupt is generated on SR0 if a trap occurs #1 EVFR Event Flag 0x30 32 0x00000000 0xFFFFFFFF T0F Trigger 0 Flag 0 0 read-only value1 No trigger event has been detected on BCCU trigger line 0 (BCCU_TRIGOUT0) #0 value2 A trigger event has been detected on BCCU trigger line 0 (BCCU_TRIGOUT0) #1 T1F Trigger 1 Flag 1 1 read-only value1 No trigger event has been detected on BCCU trigger line 1 (BCCU_TRIGOUT1) #0 value2 A trigger event has been detected on BCCU trigger line 1 (BCCU_TRIGOUT1) #1 FF FIFO Full Flag 2 2 read-only value1 No FIFO full event has been detected #0 value2 A FIFO full event has been detected because one of the packer FIFOs is full and there has been a write attempt by the on-time or off-time counter #1 EF FIFO Empty Flag 3 3 read-only value1 No FIFO full event has been detected #0 value2 A FIFO full event has been detected because one of the packer FIFOs is empty and there has been a read attempt by the output generator #1 TPF Trap Flag 4 4 read-only value1 No trap event has been detected #0 value2 A trap event has been detected #1 TPSF Trap State Flag 6 6 read-only value1 BCCU is not in a trap state #0 value2 BCCU is in a trap state, the affected channel outputs are at their passive levels #1 TPINL Trap Input Level 7 7 read-only value1 The current level of BCCU.TRAPL is low #0 value2 The current level of BCCU.TRAPL is high #1 EVFSR Event Flag Set 0x34 32 0x00000000 0xFFFFFFFF T0FS Trigger 0 Flag Set 0 0 write-only value1 No action #0 value2 Sets the Trigger 0 Flag in EVFR and an interrupt will be generated if enabled in EVIER #1 T1FS Trigger 1 Flag Set 1 1 write-only value1 No action #0 value2 Sets the Trigger 1 Flag in EVFR and an interrupt will be generated if enabled in EVIER #1 FFS FIFO Full Flag Set 2 2 write-only value1 No action #0 value2 Sets the FIFO Full Flag in EVFR and an interrupt will be generated if enabled in EVIER #1 EFS FIFO Empty Flag Set 3 3 write-only value1 No action #0 value2 Sets the FIFO Empty Flag in EVFR and an interrupt will be generated if enabled in EVIER #1 TPFS Trap Flag Set 4 4 write-only value1 No action #0 value2 Sets the Trap Flag in EVFR and an interrupt will be generated if enabled in EVIER, no trap will occur #1 TPS Trap Set 6 6 write-only value1 No action #0 value2 Sets the Trap State Flag and Trap Flag in EVFR, a trap will be generated and an interrupt will be generated if enabled in EVIER #1 EVFCR Event Flag Clear 0x38 32 0x00000000 0xFFFFFFFF T0FC Trigger 0 Flag Clear 0 0 write-only value1 No action #0 value2 Clears the Trigger 0 Flag in EVFR #1 T1FC Trigger 1 Flag Clear 1 1 write-only value1 No action #0 value2 Clears the Trigger 1 Flag in EVFR #1 FFC FIFO Full Flag Clear 2 2 write-only value1 No action #0 value2 Clears the FIFO Full Flag in EVFR #1 EFC FIFO Empty Flag Clear 3 3 write-only value1 No action #0 value2 Clears the FIFO Empty Flag in EVFR #1 TPFC Trap Flag Clear 4 4 write-only value1 No action #0 value2 Clears the Trap Flag in EVFR #1 TPC Trap Clear 6 6 write-only value1 No action #0 value2 Clears the Trap State Flag in EVFR; trap state is exited, the affected channels will return to their normal output levels #1 BCCU0_CH0 BCCU Unit 0 BCCU BCCU_CH 0x5003003C 0x0 0x14 registers INTS Channel Intensit0 Shadow 0x00 32 0x00000000 0xFFFFFFFF TCHINT Target Channel Intensity 0 11 read-write INT Channel Intensit0 0x04 32 0x00000000 0xFFFFFFFF CHINT Channel Intensity 0 11 read-only CHCONFIG Channel Configuration 0x08 32 0x00000002 0xFFFFFFFF PKTH Packer Threshold 0 2 read-write PEN Packer Enable 3 3 read-write value1 The packer is not used #0 value2 On-time and off-time counters are running and the packed output bitstream with the packer trigger are generated. #1 DSEL Dimming Select 4 6 read-write value1 Dimming Engine 0 #000 value2 Dimming Engine 1 #001 value3 Dimming Engine 2 #010 value8 Global Dimming Level #111 DBP Dimming Input Bypass 7 7 read-write value1 Channel brightness is the product of the selected dimming input and the channel intensity #0 value2 No dimming input is used, channel brightness is only determined by the channel intensity level #1 GEN Gating Enable 8 8 read-write value1 Gating function is disabled, the input signal (BCCU.INy) has no effect #0 value2 Gating function is enabled, the output gating signal is BCCU.INy #1 WEN Flicker Watchdog Enable 9 9 read-write value1 The flicker watchdog is not used #0 value2 The flicker watchdog is active and limits the number of consecutive zeroes at the sigma-delta modulator output according to GLOBCON.WDMBN #1 TRED Trigger Edge 10 10 read-write value1 Channel triggers occur on channel output transition from passive to active level #0 value2 Channel triggers occur on channel output transition from active to passive level #1 ENFT Forced Trigger Enable 11 11 read-write value1 No forced trigger is generated #0 value2 The trigger generator generates a trigger if the output of the sigma-delta modulator hasn't changed state for 256 bit times; only takes effect if the packer is disabled (PEN=0) #1 LINPRES Linear Walker Clock Prescaler 16 25 read-write PKCMP Packer Compare 0x0C 32 0x00040060 0xFFFFFFFF OFFCMP Packer Off-Time Compare Level 0 7 read-write ONCMP Packer On-Time Compare Level 16 23 read-write PKCNTR Packer Counter 0x10 32 0x00000000 0xFFFFFFFF OFFCNTVAL Off-Time Counter Value 0 7 read-write ONCNTVAL On-Time Counter Value 16 23 read-write BCCU0_CH1 BCCU Unit 0 BCCU 0x50030050 0x0 0x14 registers BCCU0_CH2 BCCU Unit 0 BCCU 0x50030064 0x0 0x14 registers BCCU0_CH3 BCCU Unit 0 BCCU 0x50030078 0x0 0x14 registers BCCU0_CH4 BCCU Unit 0 BCCU 0x5003008C 0x0 0x14 registers BCCU0_CH5 BCCU Unit 0 BCCU 0x500300A0 0x0 0x14 registers BCCU0_CH6 BCCU Unit 0 BCCU 0x500300B4 0x0 0x14 registers BCCU0_CH7 BCCU Unit 0 BCCU 0x500300C8 0x0 0x14 registers BCCU0_CH8 BCCU Unit 0 BCCU 0x500300DC 0x0 0x14 registers BCCU0_DE0 BCCU Unit 0 BCCU BCCU_DE 0x5003017C 0x0 0x0C registers DLS Dimming Level Shadow 0x00 32 0x00000000 0xFFFFFFFF TDLEV Target Dimming Level 0 11 read-write DL Dimming Level 0x04 32 0x00000000 0xFFFFFFFF DLEV Dimming Level 0 11 read-only DTT Dimming Transition Time 0x08 32 0x00000000 0xFFFFFFFF DIMDIV Dimming Clock Divider 0 9 read-write DTEN Dither Enable 16 16 read-write value1 No dithering #0 value2 Dithering is added to every dimming step if the dimming level is below 128; the coarse curve is used for the entire dimming range #1 CSEL Curve Select 17 17 read-write value1 Coarse curve #0 value2 Fine curve #1 BCCU0_DE1 BCCU Unit 0 BCCU 0x50030188 0x0 0x0C registers BCCU0_DE2 BCCU Unit 0 BCCU 0x50030194 0x0 0x0C registers PORT0 Port 0 PORTS 0x40040000 0x0 0x0100 registers OUT Port 0 Output Register 0x0000 32 0x00000000 0xFFFFFFFF P0 Port 0 Output Bit 0 0 0 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P1 Port 0 Output Bit 1 1 1 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P2 Port 0 Output Bit 2 2 2 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P3 Port 0 Output Bit 3 3 3 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P4 Port 0 Output Bit 4 4 4 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P5 Port 0 Output Bit 5 5 5 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P6 Port 0 Output Bit 6 6 6 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P7 Port 0 Output Bit 7 7 7 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P8 Port 0 Output Bit 8 8 8 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P9 Port 0 Output Bit 9 9 9 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P10 Port 0 Output Bit 10 10 10 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P11 Port 0 Output Bit 11 11 11 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P12 Port 0 Output Bit 12 12 12 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P13 Port 0 Output Bit 13 13 13 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P14 Port 0 Output Bit 14 14 14 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 P15 Port 0 Output Bit 15 15 15 read-write value1 The output level of P0.x is 0. #0 value2 The output level of P0.x is 1. #1 OMR Port 0 Output Modification Register 0x0004 32 0x00000000 0xFFFFFFFF PS0 Port 0 Set Bit 0 0 0 write-only PS1 Port 0 Set Bit 1 1 1 write-only PS2 Port 0 Set Bit 2 2 2 write-only PS3 Port 0 Set Bit 3 3 3 write-only PS4 Port 0 Set Bit 4 4 4 write-only PS5 Port 0 Set Bit 5 5 5 write-only PS6 Port 0 Set Bit 6 6 6 write-only PS7 Port 0 Set Bit 7 7 7 write-only PS8 Port 0 Set Bit 8 8 8 write-only PS9 Port 0 Set Bit 9 9 9 write-only PS10 Port 0 Set Bit 10 10 10 write-only PS11 Port 0 Set Bit 11 11 11 write-only PS12 Port 0 Set Bit 12 12 12 write-only PS13 Port 0 Set Bit 13 13 13 write-only PS14 Port 0 Set Bit 14 14 14 write-only PS15 Port 0 Set Bit 15 15 15 write-only PR0 Port 0 Reset Bit 0 16 16 write-only PR1 Port 0 Reset Bit 1 17 17 write-only PR2 Port 0 Reset Bit 2 18 18 write-only PR3 Port 0 Reset Bit 3 19 19 write-only PR4 Port 0 Reset Bit 4 20 20 write-only PR5 Port 0 Reset Bit 5 21 21 write-only PR6 Port 0 Reset Bit 6 22 22 write-only PR7 Port 0 Reset Bit 7 23 23 write-only PR8 Port 0 Reset Bit 8 24 24 write-only PR9 Port 0 Reset Bit 9 25 25 write-only PR10 Port 0 Reset Bit 10 26 26 write-only PR11 Port 0 Reset Bit 11 27 27 write-only PR12 Port 0 Reset Bit 12 28 28 write-only PR13 Port 0 Reset Bit 13 29 29 write-only PR14 Port 0 Reset Bit 14 30 30 write-only PR15 Port 0 Reset Bit 15 31 31 write-only IOCR0 Port 0 Input/Output Control Register 0 0x0010 32 0x00000000 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC1 Port Control for Port n Pin 0 to 3 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC2 Port Control for Port n Pin 0 to 3 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC3 Port Control for Port n Pin 0 to 3 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR4 Port 0 Input/Output Control Register 4 0x0014 32 0x00000000 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 7 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC5 Port Control for Port n Pin 4 to 7 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC6 Port Control for Port n Pin 4 to 7 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC7 Port Control for Port n Pin 4 to 7 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR8 Port 0 Input/Output Control Register 8 0x0018 32 0x00000000 0xFFFFFFFF PC8 Port Control for Port n Pin 8 to 11 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC9 Port Control for Port n Pin 8 to 11 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC10 Port Control for Port n Pin 8 to 11 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC11 Port Control for Port n Pin 8 to 11 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR12 Port 0 Input/Output Control Register 12 0x001C 32 0x00000000 0xFFFFFFFF PC12 Port Control for Port n Pin 12 to 15 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC13 Port Control for Port n Pin 12 to 15 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC14 Port Control for Port n Pin 12 to 15 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC15 Port Control for Port n Pin 12 to 15 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IN Port 0 Input Register 0x0024 32 0x00000000 0xFFFF0000 P0 Port 0 Input Bit 0 0 0 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P1 Port 0 Input Bit 1 1 1 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P2 Port 0 Input Bit 2 2 2 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P3 Port 0 Input Bit 3 3 3 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P4 Port 0 Input Bit 4 4 4 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P5 Port 0 Input Bit 5 5 5 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P6 Port 0 Input Bit 6 6 6 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P7 Port 0 Input Bit 7 7 7 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P8 Port 0 Input Bit 8 8 8 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P9 Port 0 Input Bit 9 9 9 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P10 Port 0 Input Bit 10 10 10 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P11 Port 0 Input Bit 11 11 11 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P12 Port 0 Input Bit 12 12 12 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P13 Port 0 Input Bit 13 13 13 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P14 Port 0 Input Bit 14 14 14 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 P15 Port 0 Input Bit 15 15 15 read-only value1 The input level of P0.x is 0. #0 value2 The input level of P0.x is 1. #1 PHCR0 Port 0 Pad Hysteresis Control Register 0 0x0040 32 0x00000000 0xFFFFFFFF PH0 Pad Hysteresis for Pn.0 2 2 read-write PH1 Pad Hysteresis for Pn.1 6 6 read-write PH2 Pad Hysteresis for Pn.2 10 10 read-write PH3 Pad Hysteresis for Pn.3 14 14 read-write PH4 Pad Hysteresis for Pn.4 18 18 read-write PH5 Pad Hysteresis for Pn.5 22 22 read-write PH6 Pad Hysteresis for Pn.6 26 26 read-write PH7 Pad Hysteresis for Pn.7 30 30 read-write PHCR1 Port 0 Pad Hysteresis Control Register 1 0x0044 32 0x00000000 0xFFFFFFFF PH8 Pad Hysteresis for P0.8 2 2 read-write PH9 Pad Hysteresis for P0.9 6 6 read-write PH10 Pad Hysteresis for P0.10 10 10 read-write PH11 Pad Hysteresis for P0.11 14 14 read-write PH12 Pad Hysteresis for P0.12 18 18 read-write PH13 Pad Hysteresis for P0.13 22 22 read-write PH14 Pad Hysteresis for P0.14 26 26 read-write PH15 Pad Hysteresis for P0.15 30 30 read-write PDISC Port 0 Pin Function Decision Control Register 0x0060 32 0x00000000 0xFFFF0000 PDIS0 Pad Disable for Port 0 Pin 0 0 0 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS1 Pad Disable for Port 0 Pin 1 1 1 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS2 Pad Disable for Port 0 Pin 2 2 2 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS3 Pad Disable for Port 0 Pin 3 3 3 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS4 Pad Disable for Port 0 Pin 4 4 4 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS5 Pad Disable for Port 0 Pin 5 5 5 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS6 Pad Disable for Port 0 Pin 6 6 6 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS7 Pad Disable for Port 0 Pin 7 7 7 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS8 Pad Disable for Port 0 Pin 8 8 8 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS9 Pad Disable for Port 0 Pin 9 9 9 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS10 Pad Disable for Port 0 Pin 10 10 10 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS11 Pad Disable for Port 0 Pin 11 11 11 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS12 Pad Disable for Port 0 Pin 12 12 12 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS13 Pad Disable for Port 0 Pin 13 13 13 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS14 Pad Disable for Port 0 Pin 14 14 14 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PDIS15 Pad Disable for Port 0 Pin 15 15 15 read-only value1 Pad P0.x is enabled. #0 value2 Pad P0.x is disabled. #1 PPS Port 0 Pin Power Save Register 0x0070 32 0x00000000 0xFFFFFFFF PPS0 Port 0 Pin Power Save Bit 0 0 0 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS1 Port 0 Pin Power Save Bit 1 1 1 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS2 Port 0 Pin Power Save Bit 2 2 2 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS3 Port 0 Pin Power Save Bit 3 3 3 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS4 Port 0 Pin Power Save Bit 4 4 4 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS5 Port 0 Pin Power Save Bit 5 5 5 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS6 Port 0 Pin Power Save Bit 6 6 6 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS7 Port 0 Pin Power Save Bit 7 7 7 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS8 Port 0 Pin Power Save Bit 8 8 8 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS9 Port 0 Pin Power Save Bit 9 9 9 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS10 Port 0 Pin Power Save Bit 10 10 10 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS11 Port 0 Pin Power Save Bit 11 11 11 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS12 Port 0 Pin Power Save Bit 12 12 12 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS13 Port 0 Pin Power Save Bit 13 13 13 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS14 Port 0 Pin Power Save Bit 14 14 14 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 PPS15 Port 0 Pin Power Save Bit 15 15 15 read-write value1 Pin Power Save of P0.x is disabled. #0 value2 Pin Power Save of P0.x is enabled. #1 HWSEL Port 0 Pin Hardware Select Register 0x0074 32 0x00000000 0xFFFFFFFF HW0 Port 0 Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port 0 Pin Hardware Select Bit 1 2 3 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port 0 Pin Hardware Select Bit 2 4 5 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port 0 Pin Hardware Select Bit 3 6 7 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port 0 Pin Hardware Select Bit 4 8 9 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port 0 Pin Hardware Select Bit 5 10 11 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port 0 Pin Hardware Select Bit 6 12 13 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW7 Port 0 Pin Hardware Select Bit 7 14 15 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW8 Port 0 Pin Hardware Select Bit 8 16 17 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW9 Port 0 Pin Hardware Select Bit 9 18 19 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW10 Port 0 Pin Hardware Select Bit 10 20 21 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW11 Port 0 Pin Hardware Select Bit 11 22 23 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW12 Port 0 Pin Hardware Select Bit 12 24 25 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW13 Port 0 Pin Hardware Select Bit 13 26 27 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW14 Port 0 Pin Hardware Select Bit 14 28 29 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW15 Port 0 Pin Hardware Select Bit 15 30 31 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 PORT1 Port 1 PORTS 0x40040100 0x0 0x0100 registers IOCR0 Port 1 Input/Output Control Register 0 0x0010 32 0x00000000 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC1 Port Control for Port n Pin 0 to 3 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC2 Port Control for Port n Pin 0 to 3 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC3 Port Control for Port n Pin 0 to 3 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR4 Port 1 Input/Output Control Register 4 0x0014 32 0x00000000 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 6 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC5 Port Control for Port n Pin 4 to 6 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC6 Port Control for Port n Pin 4 to 6 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PHCR0 Port 1 Pad Hysteresis Control Register 0 0x0040 32 0x00000000 0xFFFFFFFF PH0 Pad Hysteresis for P1.0 2 2 read-write PH1 Pad Hysteresis for P1.1 6 6 read-write PH2 Pad Hysteresis for P1.2 10 10 read-write PH3 Pad Hysteresis for P1.3 14 14 read-write PH4 Pad Hysteresis for P1.4 18 18 read-write PH5 Pad Hysteresis for P1.5 22 22 read-write PH6 Pad Hysteresis for P1.6 26 26 read-write PDISC Port 1 Pin Function Decision Control Register 0x0060 32 0x00000000 0xFFFFFF00 PDIS0 Pad Disable for Port 1 Pin 0 0 0 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS1 Pad Disable for Port 1 Pin 1 1 1 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS2 Pad Disable for Port 1 Pin 2 2 2 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS3 Pad Disable for Port 1 Pin 3 3 3 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS4 Pad Disable for Port 1 Pin 4 4 4 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS5 Pad Disable for Port 1 Pin 5 5 5 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 PDIS6 Pad Disable for Port 1 Pin 6 6 6 read-only value1 Pad P1.x is enabled. #0 value2 Pad P1.x is disabled. #1 OUT Port 1 Output Register 0x0000 32 0x00000000 0xFFFFFFFF P0 Port 1 Output Bit 0 0 0 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P1 Port 1 Output Bit 1 1 1 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P2 Port 1 Output Bit 2 2 2 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P3 Port 1 Output Bit 3 3 3 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P4 Port 1 Output Bit 4 4 4 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P5 Port 1 Output Bit 5 5 5 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 P6 Port 1 Output Bit 6 6 6 read-write value1 The output level of P1.x is 0. #0 value2 The output level of P1.x is 1. #1 OMR Port 1 Output Modification Register 0x0004 32 0x00000000 0xFFFFFFFF PS0 Port 1 Set Bit 0 0 0 write-only PS1 Port 1 Set Bit 1 1 1 write-only PS2 Port 1 Set Bit 2 2 2 write-only PS3 Port 1 Set Bit 3 3 3 write-only PS4 Port 1 Set Bit 4 4 4 write-only PS5 Port 1 Set Bit 5 5 5 write-only PS6 Port 1 Set Bit 6 6 6 write-only PR0 Port 1 Reset Bit 0 16 16 write-only PR1 Port 1 Reset Bit 1 17 17 write-only PR2 Port 1 Reset Bit 2 18 18 write-only PR3 Port 1 Reset Bit 3 19 19 write-only PR4 Port 1 Reset Bit 4 20 20 write-only PR5 Port 1 Reset Bit 5 21 21 write-only PR6 Port 1 Reset Bit 6 22 22 write-only IN Port 1 Input Register 0x0024 32 0x00000000 0xFFFFFF00 P0 Port 1 Input Bit 0 0 0 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P1 Port 1 Input Bit 1 1 1 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P2 Port 1 Input Bit 2 2 2 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P3 Port 1 Input Bit 3 3 3 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P4 Port 1 Input Bit 4 4 4 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P5 Port 1 Input Bit 5 5 5 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 P6 Port 1 Input Bit 6 6 6 read-only value1 The input level of P1.x is 0. #0 value2 The input level of P1.x is 1. #1 PPS Port 1 Pin Power Save Register 0x0070 32 0x00000000 0xFFFFFFFF PPS0 Port 1 Pin Power Save Bit 0 0 0 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS1 Port 1 Pin Power Save Bit 1 1 1 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS2 Port 1 Pin Power Save Bit 2 2 2 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS3 Port 1 Pin Power Save Bit 3 3 3 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS4 Port 1 Pin Power Save Bit 4 4 4 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS5 Port 1 Pin Power Save Bit 5 5 5 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 PPS6 Port 1 Pin Power Save Bit 6 6 6 read-write value1 Pin Power Save of P1.x is disabled. #0 value2 Pin Power Save of P1.x is enabled. #1 HWSEL Port 1 Pin Hardware Select Register 0x0074 32 0x00000000 0xFFFFFFFF HW0 Port 1 Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port 1 Pin Hardware Select Bit 1 2 3 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port 1 Pin Hardware Select Bit 2 4 5 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port 1 Pin Hardware Select Bit 3 6 7 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port 1 Pin Hardware Select Bit 4 8 9 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port 1 Pin Hardware Select Bit 5 10 11 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port 1 Pin Hardware Select Bit 6 12 13 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 PORT2 Port 2 PORTS 0x40040200 0x0 0x0100 registers OUT Port 2 Output Register 0x0000 32 0x00000000 0xFFFFFFFF P0 Port 2 Output Bit 0 0 0 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P1 Port 2 Output Bit 1 1 1 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P2 Port 2 Output Bit 2 2 2 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P3 Port 2 Output Bit 3 3 3 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P4 Port 2 Output Bit 4 4 4 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P5 Port 2 Output Bit 5 5 5 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P6 Port 2 Output Bit 6 6 6 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P7 Port 2 Output Bit 7 7 7 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P8 Port 2 Output Bit 8 8 8 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P9 Port 2 Output Bit 9 9 9 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P10 Port 2 Output Bit 10 10 10 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 P11 Port 2 Output Bit 11 11 11 read-write value1 The output level of P2.x is 0. #0 value2 The output level of P2.x is 1. #1 OMR Port 2 Output Modification Register 0x0004 32 0x00000000 0xFFFFFFFF PS0 Port 2 Set Bit 0 0 0 write-only PS1 Port 2 Set Bit 1 1 1 write-only PS2 Port 2 Set Bit 2 2 2 write-only PS3 Port 2 Set Bit 3 3 3 write-only PS4 Port 2 Set Bit 4 4 4 write-only PS5 Port 2 Set Bit 5 5 5 write-only PS6 Port 2 Set Bit 6 6 6 write-only PS7 Port 2 Set Bit 7 7 7 write-only PS8 Port 2 Set Bit 8 8 8 write-only PS9 Port 2 Set Bit 9 9 9 write-only PS10 Port 2 Set Bit 10 10 10 write-only PS11 Port 2 Set Bit 11 11 11 write-only PR0 Port 2 Reset Bit 0 16 16 write-only PR1 Port 2 Reset Bit 1 17 17 write-only PR2 Port 2 Reset Bit 2 18 18 write-only PR3 Port 2 Reset Bit 3 19 19 write-only PR4 Port 2 Reset Bit 4 20 20 write-only PR5 Port 2 Reset Bit 5 21 21 write-only PR6 Port 2 Reset Bit 6 22 22 write-only PR7 Port 2 Reset Bit 7 23 23 write-only PR8 Port 2 Reset Bit 8 24 24 write-only PR9 Port 2 Reset Bit 9 25 25 write-only PR10 Port 2 Reset Bit 10 26 26 write-only PR11 Port 2 Reset Bit 11 27 27 write-only IOCR0 Port 2 Input/Output Control Register 0 0x0010 32 0x00000000 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC1 Port Control for Port n Pin 0 to 3 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC2 Port Control for Port n Pin 0 to 3 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC3 Port Control for Port n Pin 0 to 3 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR4 Port 2 Input/Output Control Register 4 0x0014 32 0x00000000 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 7 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC5 Port Control for Port n Pin 4 to 7 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC6 Port Control for Port n Pin 4 to 7 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC7 Port Control for Port n Pin 4 to 7 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IOCR8 Port 2 Input/Output Control Register 8 0x0018 32 0x00000000 0xFFFFFFFF PC8 Port Control for Port n Pin 8 to 11 3 7 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC9 Port Control for Port n Pin 8 to 11 11 15 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC10 Port Control for Port n Pin 8 to 11 19 23 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 PC11 Port Control for Port n Pin 8 to 11 27 31 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Push-Pull - Alternate output function 5 #10101 value15 Output Push-Pull - Alternate output function 6 #10110 value16 Output Push-Pull - Alternate output function 7 #10111 value17 Output Open Drain - General-purpose output #11000 value18 Output Open Drain - Alternate output function 1 #11001 value19 Output Open Drain - Alternate output function 2 #11010 value20 Output Open Drain - Alternate output function 3 #11011 value21 Output Open Drain - Alternate output function 4 #11100 value22 Output Open Drain - Alternate output function 5 #11101 value23 Output Open Drain - Alternate output function 6 #11110 value24 Output Open Drain - Alternate output function 7 #11111 IN Port 2 Input Register 0x0024 32 0x00000000 0xFFFFF000 P0 Port 2 Input Bit 0 0 0 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P1 Port 2 Input Bit 1 1 1 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P2 Port 2 Input Bit 2 2 2 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P3 Port 2 Input Bit 3 3 3 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P4 Port 2 Input Bit 4 4 4 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P5 Port 2 Input Bit 5 5 5 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P6 Port 2 Input Bit 6 6 6 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P7 Port 2 Input Bit 7 7 7 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P8 Port 2 Input Bit 8 8 8 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P9 Port 2 Input Bit 9 9 9 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P10 Port 2 Input Bit 10 10 10 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 P11 Port 2 Input Bit 11 11 11 read-only value1 The input level of P2.x is 0. #0 value2 The input level of P2.x is 1. #1 PHCR0 Port 2 Pad Hysteresis Control Register 0 0x0040 32 0x00000000 0xFFFFFFFF PH0 Pad Hysteresis for Pn.0 2 2 read-write PH1 Pad Hysteresis for Pn.1 6 6 read-write PH2 Pad Hysteresis for Pn.2 10 10 read-write PH3 Pad Hysteresis for Pn.3 14 14 read-write PH4 Pad Hysteresis for Pn.4 18 18 read-write PH5 Pad Hysteresis for Pn.5 22 22 read-write PH6 Pad Hysteresis for Pn.6 26 26 read-write PH7 Pad Hysteresis for Pn.7 30 30 read-write PHCR1 Port 2 Pad Hysteresis Control Register 1 0x0044 32 0x00000000 0xFFFFFFFF PH8 Pad Hysteresis for P2.8 2 2 read-write PH9 Pad Hysteresis for P2.9 6 6 read-write PH10 Pad Hysteresis for P2.10 10 10 read-write PH11 Pad Hysteresis for P2.11 14 14 read-write PDISC Port 2 Pin Function Decision Control Register 0x0060 32 0x00000000 0xFFFFF000 PDIS0 Pad Disable for Port 2 Pin 0 0 0 read-write value1 Digital Pad input is enabled. Analog and digital input/output path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS1 Pad Disable for Port 2 Pin 1 1 1 read-write value1 Digital Pad input is enabled. Analog and digital input/output path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS2 Pad Disable for Port 2 Pin 2 2 2 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS3 Pad Disable for Port 2 Pin 3 3 3 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS4 Pad Disable for Port 2 Pin 4 4 4 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS5 Pad Disable for Port 2 Pin 5 5 5 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS6 Pad Disable for Port 2 Pin 6 6 6 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS7 Pad Disable for Port 2 Pin 7 7 7 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS8 Pad Disable for Port 2 Pin 8 8 8 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS9 Pad Disable for Port 2 Pin 9 9 9 read-write value1 Digital Pad input is enabled. Analog and digital input path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS10 Pad Disable for Port 2 Pin 10 10 10 read-write value1 Digital Pad input is enabled. Analog and digital input/output path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PDIS11 Pad Disable for Port 2 Pin 11 11 11 read-write value1 Digital Pad input is enabled. Analog and digital input/output path active. #0 value2 Digital Pad input is disabled. Analog input path active. (default) #1 PPS Port 2 Pin Power Save Register 0x0070 32 0x00000000 0xFFFFFFFF PPS0 Port 2 Pin Power Save Bit 0 0 0 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS1 Port 2 Pin Power Save Bit 1 1 1 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS2 Port 2 Pin Power Save Bit 2 2 2 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS3 Port 2 Pin Power Save Bit 3 3 3 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS4 Port 2 Pin Power Save Bit 4 4 4 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS5 Port 2 Pin Power Save Bit 5 5 5 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS6 Port 2 Pin Power Save Bit 6 6 6 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS7 Port 2 Pin Power Save Bit 7 7 7 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS8 Port 2 Pin Power Save Bit 8 8 8 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS9 Port 2 Pin Power Save Bit 9 9 9 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS10 Port 2 Pin Power Save Bit 10 10 10 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 PPS11 Port 2 Pin Power Save Bit 11 11 11 read-write value1 Pin Power Save of P2.x is disabled. #0 value2 Pin Power Save of P2.x is enabled. #1 HWSEL Port 2 Pin Hardware Select Register 0x0074 32 0x00000000 0xFFFFFFFF HW0 Port 2 Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port 2 Pin Hardware Select Bit 1 2 3 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port 2 Pin Hardware Select Bit 2 4 5 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port 2 Pin Hardware Select Bit 3 6 7 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port 2 Pin Hardware Select Bit 4 8 9 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port 2 Pin Hardware Select Bit 5 10 11 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port 2 Pin Hardware Select Bit 6 12 13 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW7 Port 2 Pin Hardware Select Bit 7 14 15 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW8 Port 2 Pin Hardware Select Bit 8 16 17 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW9 Port 2 Pin Hardware Select Bit 9 18 19 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW10 Port 2 Pin Hardware Select Bit 10 20 21 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW11 Port 2 Pin Hardware Select Bit 11 22 23 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10