TLE986x 2.5 TLE986x 8 8 SCU SCU 0x50005000 0x0 0x1000 registers OSC_CON OSC Control Register, RESET_TYPE_4 0x0B0 8 0x10 0xFF OSCTRIM_8 OSC_PLL Trim Configuration Bit [8] 7 7 read-write XPD XTAL (OSC_HP) Power Down Control 4 4 read-write value1 XTAL (OSC_HP) is not powered down. 0b0 value2 XTAL (OSC_HP) is powered down. 0b1 OSC2L OSC-Too-Low Condition Flag 3 3 read-only value1 fOSC is above threshold. 0b0 value2 fOSC is below threshold. 0b1 OSCWDTRST Oscillator Watchdog Reset 2 2 read-write value1 No effect. 0b0 value2 Reset OSC2L flag and restart the oscillator watchdog of the PLL. 0b1 OSCSS Oscillator Source Select 0 1 read-write value1 PLL internal oscillator OSC_PLL (fINT) is selected synchronously as fR. 0b00 value2 XTAL (fOSC from OSC_HP) is selected synchronously as fR. 0b01 value3 PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR. 0b10 value4 PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR. 0b11 PLL_CON PLL Control Register, RESET_TYPE_4 0x044 8 0x64 0xFF NDIV PLL N-Divider 4 7 read-write value1 N = 8 0b0000 value2 N = 9 0b0001 value3 N = 10 0b0010 value4 N = 12 0b0011 value5 N = 14 0b0100 value6 N = 15 0b0101 value7 N = 16 (default) 0b0110 value8 N = 18 0b0111 value9 N = 20 0b1000 value10 N = 21 0b1001 value11 N = 22 0b1010 value12 N = 24 0b1011 value13 N = 25 0b1100 value14 N = 26 0b1101 value15 N = 27 0b1110 value16 N = 28 0b1111 VCOBYP PLL VCO Bypass Mode Select 3 3 read-write value1 Normal (or freerunning) operation (default) 0b0 value2 Prescaler Mode; VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider) 0b1 OSCDISC Oscillator Disconnect 2 2 read-write value1 Oscillator is connected to the PLL 0b0 value2 Oscillator is disconnected to the PLL. 0b1 RESLD Restart Lock Detection 1 1 read-write value1 No effect. 0b0 value2 Reset lock flag and restart lock detection. 0b1 LOCK PLL Lock Status Flag 0 0 read-only value1 The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency. 0b0 value2 The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation. 0b1 CMCON1 Clock Control Register 1, RESET_TYPE_4 0x048 8 0x00 0xFF VCOSEL VCOSEL Setting 7 7 read-write value1 VCOSEL = 0 0b0 value2 VCOSEL = 1 0b1 K1DIV PLL K1-Divider 6 6 read-write value1 K1 = 2 0b0 value2 K1 = 1 0b1 K2DIV PLL K2-Divider 4 5 read-write value1 K2 = 2 0b00 value2 K2 = 3 0b01 value3 K2 = 4 0b10 value4 K2 = 5 0b11 CLKREL Slow Down Clock Divider for fCCLK Generation 0 3 read-write value1 fsys 0b0000 value2 fsys/2 0b0001 value3 fsys/3 0b0010 value4 fsys/4 0b0011 value5 fsys/8 0b0100 value6 fsys/16 0b0101 value7 fsys/24 0b0110 value8 fsys/32 0b0111 value9 fsys/48 0b1000 value10 fsys/64 0b1001 value11 fsys/96 0b1010 value12 fsys/128 0b1011 value13 fsys/192 0b1100 value14 fsys/256 0b1101 value15 fsys/384 0b1110 value16 fsys/512 0b1111 CMCON2 Clock Control Register 2, RESET_TYPE_4 0x04C 8 0x00 0xFF PBA0CLKREL PBA0 Clock Divider 0 0 read-write value1 divide by 1 0b0 value2 divide by 2 0b1 SYSCON0 System Control Register 0, RESET_TYPE_4 0x070 8 0xC0 0xFF SYSCLKSEL System Clock Select 6 7 read-write value1 The PLL clock output signal fPLL is used 0b00 value2 The direct clock input from fOSC is used 0b01 value3 The direct low-precision clock input from fLP_CLK is used. 0b10 value4 The direct low-precision clock input from fLP_CLK is used. 0b11 NVMCLKFAC NVM Access Clock Factor 4 5 read-write value1 Divide by 1 0b00 value2 Divide by 2 0b01 value3 Divide by 3 0b10 value4 Divide by 4 0b11 APCLK_CTRL1 Analog Peripheral Clock Control 1 Register, RESET_TYPE_4 0x054 8 0x30 0xFF CPCLK_DIV Charge Pump Clock Divider 7 7 read-write value1 divide by 2 0b0 value2 divide by 1 0b1 CPCLK_SEL Charge Pump Clock Selection 6 6 read-write value1 LP_CLK is selected 0b0 value2 fsys is selected 0b1 BGCLK_DIV Bandgap Clock Divider 5 5 read-write value1 divide by 2 0b0 value2 divide by 1 0b1 BGCLK_SEL Bandgap Clock Selection 4 4 read-write value1 LP_CLK is selected 0b0 value2 fsys is selected 0b1 CLKWDT_IE Clock Watchdog Interrupt Enable 3 3 read-write value1 Interrupt disabled 0b0 value2 Interrupt enabled 0b1 T3CLK_SEL Timer 3 Clock Selection 2 2 read-write value1 LP_CLK is selected 0b0 value2 MI_CLK is selected 0b1 APCLK_SET Set and Overtake Flag for Clock Settings 1 1 read-write value1 Clock Settings are ignored (previous values are hold) 0b0 value2 Clock Settings Settings are overtaken 0b1 PLL_LOCK PLL Lock Indicator 0 0 read-only APCLK_CTRL2 Analog Peripheral Clock Control 2 Register, RESET_TYPE_4 0x06C 8 0x00 0xFF T3CLK_DIV Timer 3 Clock Divider 2 3 read-write value1 divide by 1 0b00 value2 divide by 2 0b01 value3 divide by 4 0b10 value4 divide by 8 0b11 APCLK1 Analog Peripheral Clock Register 1, RESET_TYPE_4 0x058 8 0x00 0xFF APCLK3SCLR Analog Peripherals Clock Status Clear 7 7 write-only APCLK3STS Loss of Clock Status 6 6 read-only value1 No loss of clock 0b0 value2 Loss of Lock occured 0b1 APCLK1STS Analog Peripherals Clock Status 4 5 read-only value1 The MI_CLK clock is in the required range 0b00 value2 The MI_CLK clock exceeds the higher limit 0b01 value3 The MI_CLK clock exceeds the lower limit 0b10 value4 The MI_CLK clock is not inside the specified limit. 0b11 APCLK1SCLR Analog Peripherals Clock Status Clear 2 2 write-only APCLK1FAC Analog Module Clock Factor 0 1 read-write value1 Divide by 1 0b00 value2 Divide by 2 0b01 value3 Divide by 3 0b10 value4 Divide by 4 0b11 APCLK2 Analog Peripheral Clock Register 2, RESET_TYPE_4 0x05C 8 0x08 0xFF APCLK2SCLR Analog Peripherals Clock Status Clear 7 7 write-only APCLK2STS Analog Peripherals Clock Status 5 6 read-only value1 The TFILT_CLK clock is in the required range 0b00 value2 The TFILT_CLK clock exceeds the higher limit 0b01 value3 The TFILT_CLK clock exceeds the lower limit 0b10 value4 The TFILT_CLK clock is not inside the specified limit. 0b11 APCLK2FAC Slow Down Clock Divider for TFILT_CLK Generation 0 4 read-write value1 fsys 0b00000 value2 fsys/2 0b00001 value3 fsys/3 0b00010 value4 fsys/4 0b00011 value5 fsys/5 0b00100 value6 fsys/6 0b00101 value7 fsys/7 0b00110 value8 fsys/8 0b00111 value9 fsys/9 0b01000 value10 fsys/10 0b01001 value11 fsys/11 0b01010 value12 fsys/12 0b01011 value13 fsys/31 0b11110 value14 fsys/32 0b11111 COCON Clock Output Control Register, RESET_TYPE_4 0x0B4 8 0x00 0xFF EN CLKOUT Enable 7 7 read-write value1 No external clock signal is provided 0b0 value2 The configured external clock signal is provided 0b1 COUTS1 Clock Out Source Select Bit 1 6 6 read-write value1 fCCLK is selected. 0b0 value2 Based on setting of COUTS0. 0b1 TLEN Toggle Latch Enable 5 5 read-write value1 Toggle Latch is disabled. Clock output frequency is chosen by the bit field COREL. 0b0 value2 Toggle Latch is enabled. Clock output frequency is half of the frequency that is chosen by the bit field COREL. The resulting output frequency has 50% duty cycle. 0b1 COUTS0 Clock Out Source Select Bit 0 4 4 read-write value1 Oscillator output frequency is selected. 0b0 value2 Clock output frequency is chosen by the bit field COREL. 0b1 COREL Clock Output Divider 0 3 read-write value1 fsys 0b0000 value2 fsys/2 0b0001 value3 fsys/3 0b0010 value4 fsys/4 0b0011 value5 fsys/6 0b0100 value6 fsys/8 0b0101 value7 fsys/10 0b0110 value8 fsys/12 0b0111 value9 fsys/14 0b1000 value10 fsys/16 0b1001 value11 fsys/18 0b1010 value12 fsys/20 0b1011 value13 fsys/24 0b1100 value14 fsys/32 0b1101 value15 fsys/36 0b1110 value16 fsys/40 0b1111 RSTCON Reset Control Register, RESET_TYPE_3 0x068 8 0x00 0xFF LOCKUP_EN Lockup Reset Enable Flag 7 7 read-write value1 Lockup is disabled. 0b0 value2 Lockup is enabled. 0b1 LOCKUP Lockup Flag 0 0 read-write value1 Lockup Status not active. 0b0 value2 Lockup Status active. 0b1 PMCON0 Power Mode Control Register 0, RESET_TYPE_3 0x040 8 0x00 0xFF SD Slow Down Mode Enable. Active High. 3 3 read-write PD Power Down Mode Enable. Active High. 2 2 read-write SL Sleep Mode Enable. Active High. 1 1 read-write XTAL_ON OSC_HP Operation in Power Down Mode 0 0 read-write value1 OSC_HP (XTAL) will be put to Power Down mode by hardware in power save mode. 0b0 value2 OSC_HP (XTAL) continues to operate in Power Down mode, if enabled by SCU_OSC_CON.XPD. 0b1 MODIEN1 Peripheral Interrupt Enable Register 1, RESET_TYPE_3 0x030 8 0xC7 0xFF TIEN1 UART 1 Transmit Interrupt Enable 7 7 read-write value1 Transmit interrupt is disabled 0b0 value2 Transmit interrupt is enabled 0b1 RIEN1 UART 1 Receive Interrupt Enable 6 6 read-write value1 Receive interrupt is disabled 0b0 value2 Receive interrupt is enabled 0b1 RIREN1 SSC 1 Receive Interrupt Enable 2 2 read-write value1 Receive interrupt is disabled 0b0 value2 Receive interrupt is enabled 0b1 TIREN1 SSC 1 Transmit Interrupt Enable 1 1 read-write value1 Transmit interrupt is disabled 0b0 value2 Transmit interrupt is enabled 0b1 EIREN1 SSC 1 Error Interrupt Enable 0 0 read-write value1 Error interrupt is disabled 0b0 value2 Error interrupt is enabled 0b1 MODIEN2 Peripheral Interrupt Enable Register 2, RESET_TYPE_3 0x034 8 0xC7 0xFF TIEN2 UART 2 Transmit Interrupt Enable 7 7 read-write value1 Transmit interrupt is disabled 0b0 value2 Transmit interrupt is enabled 0b1 RIEN2 UART 2 Receive Interrupt Enable 6 6 read-write value1 Receive interrupt is disabled 0b0 value2 Receive interrupt is enabled 0b1 EXINT2_EN External Interrupt 2 Enable 5 5 read-write value1 External interrupt is disabled 0b0 value2 External interrupt is enabled 0b1 RIREN2 SSC 2 Receive Interrupt Enable 2 2 read-write value1 Receive interrupt is disabled 0b0 value2 Receive interrupt is enabled 0b1 TIREN2 SSC 2 Transmit Interrupt Enable 1 1 read-write value1 Transmit interrupt is disabled 0b0 value2 Transmit interrupt is enabled 0b1 EIREN2 SSC 2 Error Interrupt Enable 0 0 read-write value1 Error interrupt is disabled 0b0 value2 Error interrupt is enabled 0b1 MODIEN3 Peripheral Interrupt Enable Register 3, RESET_TYPE_3 0x038 8 0x00 0xFF MONSTS MON Input Status 5 5 read-only value1 Status zero 0b0 value2 Status one 0b1 MONIE MON Interrupt Enable 4 4 read-write value1 disabled 0b0 value2 enabled 0b1 IE0 External Interrupt Enable 0 0 read-write value1 disabled 0b0 value2 enabled 0b1 MODIEN4 Peripheral Interrupt Enable Register 4, RESET_TYPE_3 0x03C 8 0x00 0xFF IE1 External Interrupt Enable 0 0 read-write value1 disabled 0b0 value2 enabled 0b1 GPT12IEN General Purpose Timer 12 Interrupt Enable Register , RESET_TYPE_3 0x15C 8 0x3F 0xFF CRIE General Purpose Timer 12 Capture and Reload Interrupt Enable 5 5 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 T6IE General Purpose Timer 12 T6 Interrupt Enable 4 4 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 T5IE General Purpose Timer 12 T5 Interrupt Enable 3 3 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 T4IE General Purpose Timer 12 T4 Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 T3IE General Purpose Timer 12 T3 Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 T2IE General Purpose Timer 12 T2 Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 DMAIEN1 DMA Interrupt Enable Register 1, RESET_TYPE_3 0x144 8 0x00 0xFF CH8IE DMA Channel 8 Interrupt Enable 7 7 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH7IE DMA Channel 7 Interrupt Enable 6 6 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH6IE DMA Channel 6 Interrupt Enable 5 5 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH5IE DMA Channel 5 Interrupt Enable 4 4 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH4IE DMA Channel 4 Interrupt Enable 3 3 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH3IE DMA Channel 3 Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH2IE DMA Channel 2 Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 CH1IE DMA Channel 1 Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 DMAIEN2 DMA Interrupt Enable Register 2, RESET_TYPE_3 0x148 8 0x00 0xFF GPT12IE DMA GPT12 triggered Transfer Interrupt Enable 5 5 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 SSCRXIE DMA SSC Receive Transfer Interrupt Enable 4 4 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 SSCTXIE DMA SSC Transmit Transfer Interrupt Enable 3 3 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 TRSEQ2RDYIE DMA Transfer Sequence 2 Ready Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 TRSEQ1RDYIE DMA Transfer Sequence 1 Ready Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 TRERRIE DMA Transfer Error Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 DMASRCSEL DMA Source Selection Register, RESET_TYPE_3 0x14C 8 0x00 0xFF GPT12_T3 GPT12 Transmit Request 7 7 read-only value1 GPT12_T3 Transfer DMA Request not present 0b0 value2 GPT12_T3 Transfer DMA Request present 0b1 SSCRX SSC Receive Request 6 6 read-only value1 SSC Receive DMA Request not present 0b0 value2 SSC Receive DMA Request present 0b1 SSCTX SSC Transmit Request 5 5 read-only value1 SSC Transmit DMA Request not present 0b0 value2 SSC Transmit DMA Request present 0b1 T12PM_DMAEN CC6_T12_PM (Period Match) DMA muxer, DMA channel 11 3 3 read-write value1 ADC1 channel used as DMA channel 11 0b0 value2 CC6 T12_PM used as DMA channel 11 0b1 T12ZM_DMAEN CC6_T12_ZM (Zero Match) DMA muxer, DMA channel 10 2 2 read-write value1 ADC1 channel 7 used as DMA channel 10 0b0 value2 CC6 T12_ZM used DMA channel 10 0b1 SSCRXSRCSEL SSCx Receive Source Select 1 1 read-write value1 SSC1 Receive as DMA input is enabled 0b0 value2 SSC2 Receive as DMA input is enabled 0b1 SSCTXSRCSEL SSCx Transmit Source Select 0 0 read-write value1 SSC1 Transmit as DMA input is enabled 0b0 value2 SSC2 Transmit as DMA input is enabled 0b1 DMASRCCLR DMA Source Selection Clear Register, RESET_TYPE_3 0x198 8 0x00 0xFF GPT12_T3C GPT12 Transmit Request Clear 7 7 write-only value1 GPT12_T3 Transfer DMA Request not cleared 0b0 value2 GPT12_T3 Transfer DMA Request cleared 0b1 SSCRXC SSC Receive Request Clear 6 6 write-only value1 SSC Receive DMA Request not cleared 0b0 value2 SSC Receive DMA Request cleared 0b1 SSCTXC SSC Transmit Request Clear 5 5 write-only value1 SSC Transmit DMA Request not cleared 0b0 value2 SSC Transmit DMA Request cleared 0b1 DMASRCSEL2 DMA Source Selection Register 2, RESET_TYPE_3 0x180 8 0x00 0xFF GPT12_DMAEN GPT12 T3 DMA muxer, DMA channel 12 0 1 read-write value1 Timer3 cc6u_int used as DMA channel 12 0b00 value2 GPT12 T3 used as DMA channel 12 0b01 value3 Timer3 ccu6_int or T12_ZM used as DMA channel 12 0b10 value4 GPT12 T3 or T12_ZM used as DMA channel 12 0b11 MODPISEL Peripheral Input Select Register, RESET_TYPE_3 0x0B8 8 0x00 0xFF U_TX_CONDIS UART1 TxD Connection Disable 7 7 read-write value1 UART1-TX-Output -LIN Transmitter TX Input Connection available. 0b0 value2 UART1-TX-Output -LIN Transmitter TX Input Connection not available (can be stimulated by external port pin). 0b1 URIOS1 UART1 Input/Output Select 6 6 read-write value1 UART1 Receiver Input RXD1_0 (Connection to LIN is available). 0b0 value2 UART1 Receiver Input RXD1_1 (Connection to LIN is not available). 0b1 EXINT2IS External Interrupt 2 Input Select 4 5 read-write value1 External Interrupt Input EXINT2_0 is selected (P2.7). 0b00 value2 External Interrupt Input EXINT2_1 is selected (P1.4). 0b01 value3 External Interrupt Input EXINT2_2 is selected (P0.4). 0b10 value4 External Interrupt Input EXINT2_3 is selected (P0.0). 0b11 EXINT1IS External Interrupt 1 Input Select 2 3 read-write value1 External Interrupt Input EXINT1_0 is selected (P1.1). 0b00 value2 External Interrupt Input EXINT1_1 is selected (P1.3). 0b01 value3 External Interrupt Input EXINT1_2 is selected (P1.0). 0b10 value4 External Interrupt Input EXINT1_3 is selected (P2.4). 0b11 EXINT0IS External Interrupt 0 Input Select 0 1 read-write value1 External Interrupt Input EXINT0_0 is selected (P2.0). 0b00 value2 External Interrupt Input EXINT0_1 is selected (P1.2). 0b01 value3 External Interrupt Input EXINT0_2 is selected (P0.1). 0b10 value4 External Interrupt Input EXINT0_3 is selected (P2.3). 0b11 MODPISEL1 Peripheral Input Select Register 1, RESET_TYPE_3 0x0BC 8 0x00 0xFF T21EXCON Timer 21 External Input Control 7 7 read-write value1 Timer 21 Input T21EX is selected by bit field MODPISEL.T2EXIS. 0b0 value2 Timer 21 Input T21EX is connected to signal from analog subsystem. 0b1 T2EXCON Timer 2 External Input Control 6 6 read-write value1 Timer 2 Input T2EX is selected by bit field MODPISEL.T2EXIS. 0b0 value2 Timer 2 Input T2EX is connected to signal from analog subsystem. 0b1 MODPISEL2 Peripheral Input Select Register 2, RESET_TYPE_3 0x0C0 8 0x00 0xFF T21EXIS Timer 21 External Input Select 6 7 read-write value1 Timer 21 Input T21EX_0 is selected. 0b00 value2 Timer 21 Input T21EX_1 is selected. 0b01 value3 Timer 21 Input T21EX_2 is selected. 0b10 value4 Timer 21 Input T21EX_3 is selected. 0b11 T2EXIS Timer 2 External Input Select 4 5 read-write value1 Timer 2 Input T2EX_0 is selected. 0b00 value2 Timer 2 Input T2EX_1 is selected. 0b01 T21IS Timer 21 Input Select 2 3 read-write value1 Timer 21 Input T21_0 is selected. 0b00 value2 Timer 21 Input T21_1 is selected. 0b01 value3 Timer 21 Input T21_2 is selected. 0b10 value4 Reserved. 0b11 T2IS Timer 2 Input Select 0 1 read-write value1 Timer 2 Input T2_0 is selected. 0b00 MODPISEL3 Peripheral Input Select Register, RESET_TYPE_3 0x0C4 8 0x00 0xFF URIOS2 UART2 Input/Output Select 6 6 read-write value1 UART2 Receiver Input RXD2_0 and Transmitter Output TXD2_0 is selected. 0b0 value2 UART2 Receiver Input RXD2_1 and Transmitter Output TXD2_1 is selected. 0b1 P0_POCON0 Port Output Control Register, RESET_TYPE_3 0x0E8 8 0x44 0xFF PDM1 P0.1 Port Driver Mode 4 6 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 PDM0 P0.0 Port Driver Mode 0 2 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 P0_POCON1 Port Output Control Register, RESET_TYPE_3 0x0EC 8 0x44 0xFF PDM3 P0.3 Port Driver Mode 4 6 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 PDM2 P0.2 Port Driver Mode 0 2 read-write value1 Strong driver and sharp edge mode 0b000 value2 Strong driver and medium edge mode 0b001 value3 Strong driver and soft edge mode 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 P0_POCON2 Port Output Control Register, RESET_TYPE_3 0x0F0 8 0x44 0xFF PDM4 P0.4 Port Driver Mode 0 2 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 P1_POCON0 Port Output Control Register, RESET_TYPE_3 0x0F8 8 0x44 0xFF PDM1 P1.1 Port Driver Mode 4 6 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 PDM0 P1.0 Port Driver Mode 0 2 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 P1_POCON1 Port Output Control Register, RESET_TYPE_3 0x0FC 8 0x44 0xFF PDM3 P1.3 Port Driver Mode 4 6 read-write value1 Strong driver and sharp edge mode 0b000 value2 Strong driver and medium edge mode 0b001 value3 Strong driver and soft edge mode 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 PDM2 P1.2 Port Driver Mode 0 2 read-write value1 Not used 0b000 value2 Not used 0b001 value3 Not Used 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 P1_POCON2 Port Output Control Register, RESET_TYPE_3 0x100 8 0x04 0xFF PDM4 P1.4 Port Driver Mode 0 2 read-write value1 Strong driver and sharp edge mode 0b000 value2 Strong driver and medium edge mode 0b001 value3 Strong driver and soft edge mode 0b010 value4 Weak driver 0b011 value5 Medium driver 0b100 value6 Medium driver 0b101 value7 Medium driver 0b110 value8 Weak driver 0b111 TCCR Temperature Compensation Control Register, RESET_TYPE_3 0x0F4 8 0x03 0xFF TCC Temperature Compensation Control 0 1 read-write value1 TJ: -40 oC to 0 oC 0b00 value2 TJ: 0 oC to 40 oC 0b01 value3 TJ: 40 oC to 80 oC 0b10 value4 TJ: 80 oC to 150 oC 0b11 GPT12PISEL GPT12 Peripheral Input Select Register, RESET_TYPE_3 0x0D0 8 0x00 0xFF T3_GPT12_SEL CCU6_INT_SEL. 5 5 read-write value1 CCU6_INT is triggered by Timer 3 0b0 value2 CCU6_INT is triggered by GPT12PISEL.GPT12. 0b1 TRIG_CONF CCU6 Trigger Configuration. 4 4 read-write value1 Trigger is just for one measurement (default) 0b0 value2 Trigger is present until next input edge (selected by GPT12) - continuos measurement. 0b1 GPT12 GPT12 TIN3B / TIN4D Input Select 0 3 read-write value1 CC60 0b0000 value2 CC61 0b0001 value3 CC62 0b0010 value4 T12 ZM. 0b0011 value5 T12 PM. 0b0100 value6 T12 CM0. 0b0101 value7 T12 CM1. 0b0110 value8 T12 CM2. 0b0111 value9 T13 PM. 0b1000 value10 T13 ZM. 0b1001 value11 T13 CM. 0b1010 value12 any pos or neg edge on CC60/61/62. 0b1011 value13 RES. 0b1100 value14 RES. 0b1101 value15 RES. 0b1110 value16 RES. 0b1111 PMCON1 Peripheral Management Control Register 1, RESET_TYPE_3 0x060 8 0x00 0xFF GPT12_DIS General Purpose Timer 12 Disable Request. Active high. 4 4 read-write value1 GPT12is in normal operation. (default) 0b0 value2 Request to disable the GPT12. 0b1 T2_DIS T2 Disable Request. Active high. 3 3 read-write value1 T2 is in normal operation. (default) 0b0 value2 Request to disable the T2. 0b1 CCU6_DIS CCU6 Disable Request. Active high. 2 2 read-write value1 CCU6 is in normal operation. (default) 0b0 value2 Request to disable the CCU6. 0b1 SSC1_DIS SSC1 Disable Request. Active high. 1 1 read-write value1 SSC is in normal operation. (default) 0b0 value2 Request to disable the SSC. 0b1 ADC1_DIS ADC1 Disable Request. Active high. 0 0 read-write value1 ADC1 is in normal operation. (default) 0b0 value2 Request to disable the ADC. 0b1 PMCON2 Peripheral Management Control Register 2, RESET_TYPE_3 0x064 8 0x00 0xFF T3_DIS T3 Disable Request. Active high. 5 5 read-write value1 T3is in normal operation. (default) 0b0 value2 Request to disable the T3. 0b1 T21_DIS T21 Disable Request. Active high. 3 3 read-write value1 T21 is in normal operation. (default) 0b0 value2 Request to disable the T21. 0b1 SSC2_DIS SSC2 Disable Request. Active high. 1 1 read-write value1 SSC is in normal operation. (default) 0b0 value2 Request to disable the SSC. 0b1 MODSUSP1 Module Suspend Control Register 1, RESET_TYPE_3 0x0C8 8 0x81 0xFF T21_SUSP Timer21 Debug Suspend Bit 6 6 read-write value1 Timer21 will not be suspended. 0b0 value2 Timer21 will be suspended. 0b1 GPT12_SUSP GPT12 Debug Suspend Bit 4 4 read-write value1 GPT12 will not be suspended. 0b0 value2 GPT12 will be suspended. 0b1 T2_SUSP Timer2 Debug Suspend Bit 3 3 read-write value1 Timer2 will not be suspended. 0b0 value2 Timer2 will be suspended. 0b1 T13SUSP Timer 13 Debug Suspend Bit 2 2 read-write value1 Timer 13 in Capture/Compare Unit will not be suspended. 0b0 value2 Timer 13 in Capture/Compare Unit will be suspended. 0b1 T12SUSP Timer 12 Debug Suspend Bit 1 1 read-write value1 Timer 12 in Capture/Compare Unit will not be suspended. 0b0 value2 Timer 12 in Capture/Compare Unit will be suspended. 0b1 WDTSUSP SCU Watchdog Timer Debug Suspend Bit 0 0 read-write value1 WDT will not be suspended. 0b0 value2 WDT will be suspended. 0b1 MODSUSP2 Module Suspend Control Register 2, RESET_TYPE_3 0x0CC 8 0x00 0xFF ADC1_SUSP ADC1 Unit Debug Suspend Bit 2 2 read-write value1 ADC1 will not be suspended. 0b0 value2 ADC1 will be suspended. 0b1 MU_SUSP Measurement Unit Debug Suspend Bit 1 1 read-write value1 MU will not be suspended. 0b0 value2 MU will be suspended. 0b1 T3_SUSP Measurement Unit Debug Suspend Bit 0 0 read-write value1 Timer 3 will not be suspended. 0b0 value2 Timer 3 will be suspended. 0b1 BCON1 Baud Rate Control Register 1, RESET_TYPE_3 0x088 8 0x00 0xFF R Baud Rate Generator Run Control Bit 0 0 read-write value1 Baud-rate generator disabled. 0b0 value2 Baud-rate generator enabled. 0b1 BRPRE Prescaler Bit 1 3 read-write value1 fDIV = fPCLK 0b000 value2 fDIV = fPCLK/2 0b001 value3 fDIV = fPCLK/4 0b010 value4 fDIV = fPCLK/8 0b011 value5 fDIV = fPCLK/16 0b100 value6 fDIV = fPCLK/32 0b101 BCON2 Baud Rate Control Register 2, RESET_TYPE_3 0x098 8 0x00 0xFF R Baud Rate Generator Run Control Bit 0 0 read-write value1 Baud-rate generator disabled. 0b0 value2 Baud-rate generator enabled. 0b1 BRPRE Prescaler Bit 1 3 read-write value1 fDIV = fPCLK 0b000 value2 fDIV = fPCLK/2 0b001 value3 fDIV = fPCLK/4 0b010 value4 fDIV = fPCLK/8 0b011 value5 fDIV = fPCLK/16 0b100 value6 fDIV = fPCLK/32 0b101 BGL1 Baud Rate Timer/Reload Register, Low Byte 1, RESET_TYPE_3 0x08C 8 0x00 0xFF FD_SEL Fractional Divider Selection 0 4 read-write BR_VALUE Baud Rate Timer/Reload Value 5 7 read-write BGL2 Baud Rate Timer/Reload Register, Low Byte 2, RESET_TYPE_3 0x09C 8 0x00 0xFF FD_SEL Fractional Divider Selection 0 4 read-write BR_VALUE Baud Rate Timer/Reload Value 5 7 read-write BGH1 Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3 0x090 8 0x00 0xFF BR_VALUE Baud Rate Timer/Reload Value 0 7 read-write value1 Baud-rate timer is bypassed. 0x00 value2 1 0x01 value3 2 0x02 BGH2 Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3 0x0A0 8 0x00 0xFF BR_VALUE Baud Rate Timer/Reload Value 0 7 read-write value1 Baud-rate timer is bypassed. 0x00 value2 1 0x01 value3 2 0x02 LINST LIN Status Register, RESET_TYPE_3 0x094 8 0x00 0xFF BRDIS Baud Rate Detection Disable 0 0 read-write value1 Break/Synch detection is enabled. 0b0 value2 Break/Synch detection is disabled. 0b1 BGSEL Baud Rate Select for Detection 1 2 read-write BRK Break Field Flag 3 3 read-only value1 Break Field is not detected. 0b0 value2 Break Field is detected. 0b1 EOFSYN End of SYN Byte Interrupt Flag 4 4 read-only value1 End of SYN Byte is not detected. 0b0 value2 End of SYN Byte is detected. 0b1 ERRSYN SYN Byte Error Interrupt Flag 5 5 read-only value1 Error is not detected in SYN Byte. 0b0 value2 Error is detected in SYN Byte. 0b1 SYNEN End of SYN Byte and SYN Byte Error Interrupts Enable 6 6 read-write value1 End of SYN Byte and SYN Byte Error Interrupts are not enabled. 0b0 value2 End of SYN Byte and SYN Byte Error Interrupts are enabled. 0b1 LINSCLR LIN Status Clear Register, RESET_TYPE_3 0x0A4 8 0x00 0xFF BRKC Break Field Flag Clear 3 3 write-only value1 Break Field is not cleared. 0b0 value2 Break Field is cleared. 0b1 EOFSYNC End of SYN Byte Interrupt Flag Clear 4 4 write-only value1 End of SYN Byte is not cleared. 0b0 value2 End of SYN Byte is cleared. 0b1 ERRSYNC SYN Byte Error Interrupt Flag 5 5 write-only value1 Error in SYN Byte not cleared. 0b0 value2 Error in SYN Byte cleared. 0b1 WDTREL Watchdog Timer Reload Register, RESET_TYPE_3 0x078 8 0x00 0xFF WDTREL Watchdog Timer Reload Value 0 7 read-write WDTCON Watchdog Timer Control Register, RESET_TYPE_3 0x050 8 0x00 0xFF WINBEN Watchdog Window-Boundary Enable 5 5 read-write value1 Watchdog Window-Boundary feature is disabled. (default) 0b0 value2 Watchdog Window-Boundary feature is enabled. 0b1 WDTPR Watchdog Prewarning Mode Flag 4 4 read-only value1 Normal mode (default after reset) 0b0 value2 The Watchdog is operating in Prewarning Mode 0b1 WDTEN WDT Enable 2 2 read-write value1 WDT is disabled 0b0 value2 WDT is enabled 0b1 WDTRS WDT Refresh Start 1 1 read-write WDTIN Watchdog Timer Input Frequency Selection 0 0 read-write value1 Input frequency is fPCLK/2 0b0 value2 Input frequency is fPCLK/128 0b1 WDTL Watchdog Timer, Low Byte, RESET_TYPE_3 0x080 8 0x00 0xFF WDT Watchdog Timer Current Value 0 7 read-only WDTH Watchdog Timer, High Byte, RESET_TYPE_3 0x084 8 0x00 0xFF WDT Watchdog Timer Current Value 0 7 read-only WDTWINB Watchdog Window-Boundary Count, RESET_TYPE_3 0x07C 8 0x00 0xFF WDTWINB Watchdog Window-Boundary Count Value 0 7 read-write EDCCON Error Detection and Correction Control Register, RESET_TYPE_3 0x0D4 8 0x00 0xFF NVMIE NVM Double Bit ECC Error Interrupt Enable 2 2 read-write value1 No NMI is generated when a double bit ECC error occurs reading NVM. 0b0 value2 An NMI is generated when a double bit ECC error occurs reading NVM. 0b1 RIE RAM Double Bit ECC Error Interrupt Enable 0 0 read-write value1 No NMI is generated when a double bit ECC error occurs reading RAM. 0b0 value2 An NMI is generated when a double bit ECC error occurs reading RAM. 0b1 EDCSTAT Error Detection and Correction Status Register, RESET_TYPE_4 0x0D8 8 0x00 0xFF RSBE RAM Single Bit Error 4 4 read-only value1 No single bit error on RAM has occured. 0b0 value2 A single bit error on RAM has occured. 0b1 NVMDBE NVM Double Bit Error 2 2 read-only value1 No double bit error on NVM has occured. 0b0 value2 A double bit error on NVM has occured. 0b1 RDBE RAM Double Bit Error 0 0 read-only value1 No double bit error on RAM has occured. 0b0 value2 A double bit error on RAM has occured. 0b1 EDCSCLR Error Detection and Correction Status Clear Register, RESET_TYPE_3 0x10C 8 0x00 0xFF RSBEC RAM Single Bit Error Clear 4 4 write-only value1 A single bit error on RAM is not cleared. 0b0 value2 A single bit error on RAM is cleared. 0b1 NVMDBEC NVM Double Bit Error Clear 2 2 write-only value1 A double bit error on NVM is not cleared. 0b0 value2 A double bit error on NVM is cleared. 0b1 RDBEC RAM Double Bit Error Clear 0 0 write-only value1 A double bit error on RAM is not cleared. 0b0 value2 A double bit error on RAM is cleared. 0b1 PASSWD Password Register, RESET_TYPE_3 0x0AC 8 0x07 0xFF PASS Password Bits 3 7 write-only value1 Enables writing of the bit field MODE. 0b11000 value2 Opens access to writing of all protected bits. 0b10011 value3 Closes access to writing of all protected bits. 0b10101 PROTECT_S Bit-Protection Signal Status Bit 2 2 read-only value1 Software is able to write to all protected bits. 0b0 value2 Software is unable to write to any protected bits. 0b1 MODE Bit-Protection Scheme Control Bit 0 1 read-write value1 Scheme Disabled 0b00 value2 Scheme Enabled (default) 0b11 SYS_STRTUP_STS System Startup Status Register 0x74 8 0x40 0xFF PG100TP_CHKS_ERR 100 TP Page Checksum Error 2 2 rw MRAMINITSTS Map RAM Initialization Status 1 1 rw INIT_FAIL Initialization at startup failed 0 0 rw NVM_PROT_STS NVM Protection Status Register, RESET_TYPE_4 0x0E0 8 0x00 0xFF NVMPROTSTSL_3 NVM Protection Status Register Low Flags 3 3 read-write value1 The data in sectors of the linearly mapped area can not be read 0b0 value2 The data in sectors of the linearly mapped area can be read 0b1 NVMPROTSTSL_2 NVM Protection Status Register Low Flags 2 2 read-write value1 The data in sectors of the non-linearly mapped area can not be read 0b0 value2 The data in sectors of the non-linearly mapped area can be read 0b1 NVMPROTSTSL_1 NVM Protection Status Register Low Flags 1 1 read-write value1 The data in sectors of the linearly mapped area can not be changed 0b0 value2 The data in sectors of the linearly mapped area can be changed 0b1 NVMPROTSTSL_0 NVM Protection Status Register Low Flags 0 0 read-write value1 The data in sectors of the non-linearly mapped area can not be changed 0b0 value2 The data in sectors of the non-linearly mapped area can be changed 0b1 MEM_ACC_STS Memory Access Status Register, RESET_TYPE_3 0x0E4 8 0x00 0xFF RAM_ADDR_ERR RAM Address Protection 7 7 read-only value1 No Protection error 0b0 value2 Protection error 0b1 RAM_PROT_ERR RAM Access Protection 6 6 read-only value1 No Protection error 0b0 value2 Protection error 0b1 ROM_ADDR_ERR ROM Address Protection 5 5 read-only value1 No Protection error 0b0 value2 Protection error 0b1 ROM_PROT_ERR ROM Access Protection 4 4 read-only value1 No Protection error 0b0 value2 Protection error 0b1 NVM_SFR_ADDR_ERR NVM SFR Address Protection 3 3 read-only value1 No Protection error 0b0 value2 Protection error 0b1 NVM_SFR_PROT_ERR NVM SFR Access Protection 2 2 read-only value1 No Protection error 0b0 value2 Protection error 0b1 NVM_ADDR_ERR NVM Address Protection 1 1 read-only value1 No Protection error 0b0 value2 Protection error 0b1 NVM_PROT_ERR NVM Access Protection 0 0 read-only value1 No Protection error 0b0 value2 Protection error 0b1 ID Identity Register, RESET_TYPE_3 0x0A8 8 0x81 0xFF PRODID Product ID 3 7 read-only VERID Version ID 0 2 read-only MEMSTAT Memory Status Register, RESET_TYPE_3 0x0DC 8 0x00 0xFF SASTATUS Service Algorithm Status 6 7 read-write value1 Depending on SECTORINFO, there are two possible outcomes: For SECTORINFO = 00H, NVM initialization is successful and no SA is executed. For SECTORINFO = values other than 00H, SA execution is successful and only one map error is fixed. 0b00 value2 SA execution is successful. More than one mapping error is fixed. 0b01 value3 SA execution is not successful. Map error exists in one sector. 0b10 value4 SA execution is not successful. At least one sector failed (this includes also the case where a sector is repaired but another sector is still failing). 0b11 SECTORINFO Sector Information 0 5 read-write IEN0 Interrupt Enable Register 0, RESET_TYPE_4 0x01C 8 0x00 0xFF EA Global Interrupt Mask 7 7 read-write value1 All pending interrupt requests (except NMI) are blocked from the core. 0b0 value2 Pending interrupt requests are not blocked from the core. 0b1 NMICON NMI Control Register, RESET_TYPE_4 0x024 8 0x00 0xFF NMISUP Supply Prewarning NMI Enable 7 7 read-write value1 Supply NMI is disabled. 0b0 value2 Supply NMI is enabled. 0b1 NMIECC ECC Error NMI Enable 6 6 read-write value1 ECC Error NMI is disabled. 0b0 value2 ECC Error NMI is enabled. 0b1 NMIMAP NVM Map Error NMI Enable 5 5 read-write value1 NVM Map Error NMI is disabled. 0b0 value2 NVM Map Error NMI is enabled. 0b1 NMIOWD Oscillator Watchdog NMI Enable 4 4 read-write value1 Oscillator watchdog NMI is disabled. 0b0 value2 Oscillator watchdog NMI is enabled. 0b1 NMIOT NMI OT Enable 3 3 read-write value1 NMI OT is disabled. 0b0 value2 NMI OT is enabled. 0b1 NMINVM NVM Operation Complete NMI Enable 2 2 read-write value1 NVM operation complete NMI is disabled. 0b0 value2 NVM operation complete NMI is enabled. 0b1 NMIPLL PLL Loss of Lock NMI Enable 1 1 read-write value1 PLL Loss of Lock NMI is disabled. 0b0 value2 PLL Loss of Lock NMI is enabled. 0b1 NMIWDT Watchdog Timer NMI Enable 0 0 read-write value1 WDT NMI is disabled. 0b0 value2 WDT NMI is enabled. 0b1 EXICON0 External Interrupt Control Register 0, RESET_TYPE_3 0x028 8 0x30 0xFF MON MON Input Trigger Select 6 7 read-write value1 external interrupt MON is disabled. 0b00 value2 Interrupt on rising edge. 0b01 value3 Interrupt on falling edge. 0b10 value4 Interrupt on both rising and falling edge. 0b11 EXINT2 External Interrupt 2 Trigger Select 4 5 read-write value1 external interrupt 2 is disabled. 0b00 value2 Interrupt on rising edge. 0b01 value3 Interrupt on falling edge. 0b10 value4 Interrupt on both rising and falling edge. 0b11 EXINT1 External Interrupt 1 Trigger Select 2 3 read-write value1 external interrupt 1 is disabled. 0b00 value2 Interrupt on rising edge. 0b01 value3 Interrupt on falling edge. 0b10 value4 Interrupt on both rising and falling edge. 0b11 EXINT0 External Interrupt 0 Trigger Select 0 1 read-write value1 external interrupt 0 is disabled. 0b00 value2 Interrupt on rising edge. 0b01 value3 Interrupt on falling edge. 0b10 value4 Interrupt on both rising and falling edge. 0b11 IRCON0 Interrupt Request Register 0, RESET_TYPE_3 0x004 8 0x00 0xFF MONF Interrupt Flag for External Interrupt MON on falling edge 7 7 read-only value1 Interrupt on falling edge event has not occurred. 0b0 value2 Interrupt on falling edge event has occurred. 0b1 MONR Interrupt Flag for External Interrupt MON on rising edge 6 6 read-only value1 Interrupt on rising edge event has not occurred. 0b0 value2 Interrupt on rising edge event has occurred. 0b1 EXINT2F Interrupt Flag for External Interrupt 2x on falling edge 5 5 read-only value1 Interrupt on falling edge event has not occurred. 0b0 value2 Interrupt on falling edge event has occurred. 0b1 EXINT2R Interrupt Flag for External Interrupt 2x on rising edge 4 4 read-only value1 Interrupt on rising edge event has not occurred. 0b0 value2 Interrupt on rising edge event has occurred. 0b1 EXINT1F Interrupt Flag for External Interrupt 1x on falling edge 3 3 read-only value1 Interrupt on falling edge event has not occurred. 0b0 value2 Interrupt on falling edge event has occurred. 0b1 EXINT1R Interrupt Flag for External Interrupt 1x on rising edge 2 2 read-only value1 Interrupt on rising edge event has not occurred. 0b0 value2 Interrupt on rising edge event has occurred. 0b1 EXINT0F Interrupt Flag for External Interrupt 0x on falling edge 1 1 read-only value1 Interrupt on falling edge event has not occurred. 0b0 value2 Interrupt on falling edge event has occurred. 0b1 EXINT0R Interrupt Flag for External Interrupt 0x on rising edge 0 0 read-only value1 Interrupt on rising edge event has not occurred. 0b0 value2 Interrupt on rising edge event has occurred. 0b1 IRCON0CLR Interrupt Request 0 Clear Register, RESET_TYPE_3 0x02C 8 0x00 0xFF MONFC Interrupt Flag for External Interrupt MON on falling edge clear 7 7 write-only value1 Interrupt on falling edge event is not cleared. 0b0 value2 Interrupt on falling edge event is cleared. 0b1 MONRC Interrupt Flag for External Interrupt MON on rising edge clear 6 6 write-only value1 Interrupt on rising edge event is not cleared. 0b0 value2 Interrupt on rising edge event is cleared. 0b1 EXINT2FC Interrupt Flag for External Interrupt 2x on falling edge clear 5 5 write-only value1 Interrupt on falling edge event is not cleared. 0b0 value2 Interrupt on falling edge event is cleared. 0b1 EXINT2RC Interrupt Flag for External Interrupt 2x on rising edge clear 4 4 write-only value1 Interrupt on rising edge event is not cleared. 0b0 value2 Interrupt on rising edge event is cleared. 0b1 EXINT1FC Interrupt Flag for External Interrupt 1x on falling edge clear 3 3 write-only value1 Interrupt on falling edge event is not cleared. 0b0 value2 Interrupt on falling edge event is cleared. 0b1 EXINT1RC Interrupt Flag for External Interrupt 1x on rising edge clear 2 2 write-only value1 Interrupt on rising edge event is not cleared. 0b0 value2 Interrupt on rising edge event is cleared. 0b1 EXINT0FC Interrupt Flag for External Interrupt 0x on falling edge clear 1 1 write-only value1 Interrupt on falling edge event is not cleared. 0b0 value2 Interrupt on falling edge event is cleared. 0b1 EXINT0RC Interrupt Flag for External Interrupt 0x on rising edge clear 0 0 write-only value1 Interrupt on rising edge event is not cleared. 0b0 value2 Interrupt on rising edge event is cleared. 0b1 IRCON1 Interrupt Request Register 1, RESET_TYPE_3 0x008 8 0x00 0xFF RIR Receive Interrupt Flag for SSC1 2 2 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 TIR Transmit Interrupt Flag for SSC1 1 1 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 EIR Error Interrupt Flag for SSC1 0 0 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 IRCON1CLR Interrupt Request 1 Clear Register, RESET_TYPE_3 0x178 8 0x00 0xFF RIRC Receive Interrupt Flag for SSC1 Clear 2 2 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 TIRC Transmit Interrupt Flag for SSC1 Clear 1 1 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 EIRC Error Interrupt Flag for SSC1 Clear 0 0 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 IRCON2 Interrupt Request Register 2, RESET_TYPE_3 0x00C 8 0x00 0xFF RIR Receive Interrupt Flag for SSC2 2 2 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 TIR Transmit Interrupt Flag for SSC2 1 1 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 EIR Error Interrupt Flag for SSC2 0 0 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 IRCON2CLR Interrupt Request 2 Clear Register, RESET_TYPE_3 0x17C 8 0x00 0xFF RIRC Receive Interrupt Flag for SSC2 Clear 2 2 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 TIRC Transmit Interrupt Flag for SSC2 Clear 1 1 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 EIRC Error Interrupt Flag for SSC2 Clear 0 0 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 IRCON3 Interrupt Request Register 3, RESET_TYPE_3 0x010 8 0x00 0xFF CCU6SR1 Interrupt Flag 1 for CCU6 4 4 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 CCU6SR0 Interrupt Flag 0 for CCU6 0 0 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 IRCON3CLR Interrupt Request 3 Clear Register, RESET_TYPE_3 0x190 8 0x00 0xFF CCU6SR1C Interrupt Flag 1 for CCU6 Clear 4 4 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 CCU6SR0C Interrupt Flag 0 for CCU6 Clear 0 0 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 IRCON4 Interrupt Request Register 4, RESET_TYPE_3 0x014 8 0x00 0xFF CCU6SR3 Interrupt Flag 3 for CCU6 4 4 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 CCU6SR2 Interrupt Flag 2 for CCU6 0 0 read-only value1 Interrupt event has not occurred. 0b0 value2 Interrupt event has occurred. 0b1 IRCON4CLR Interrupt Request 4 Clear Register, RESET_TYPE_3 0x194 8 0x00 0xFF CCU6SR3C Interrupt Flag 3 for CCU6 Clear 4 4 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 CCU6SR2C Interrupt Flag 2 for CCU6 Clear 0 0 write-only value1 Interrupt event is not cleared. 0b0 value2 Interrupt event is cleared. 0b1 GPT12IRC Timer and Counter Control/Status Register, RESET_TYPE_3 0x160 8 0x00 0xFF CR GPT Module 2 Capture Reload Interrupt Status 5 5 read-only value1 No Capture Reload Interrupt has occurred. 0b0 value2 Capture Reload Interrupt has occurred. 0b1 T6 GPT Module 2Timer6 Interrupt Status 4 4 read-only value1 No Timer 6 Interrupt has occurred. 0b0 value2 Timer 6 Interrupt has occurred. 0b1 T5 GPT Module 2 Timer5 Interrupt Status 3 3 read-only value1 No Timer 5 Interrupt has occurred. 0b0 value2 Timer 5 Interrupt has occurred. 0b1 T4 GPT Module 1 Timer4 Interrupt Status 2 2 read-only value1 No Timer 4 Interrupt has occurred. 0b0 value2 Timer 4 Interrupt has occurred. 0b1 T3 GPT Module 1 Timer3 Interrupt Status 1 1 read-only value1 No Timer 3 Interrupt has occurred. 0b0 value2 Timer 3 Interrupt has occurred. 0b1 T2 GPT Module 1 Timer 2 Interrupt Status 0 0 read-only value1 No Timer 2 Interrupt has occurred. 0b0 value2 Timer 2 Interrupt has occurred. 0b1 GPT12ICLR Timer and Counter Control/Status Clear Register, RESET_TYPE_3 0x164 8 0x00 0xFF CRC GPT Module 2 Capture Reload Interrupt Status Clear 5 5 write-only value1 No Capture Reload Interrupt is cleared. 0b0 value2 Capture Reload Interrupt is cleared. 0b1 T6C GPT Module 2Timer6 Interrupt Status Clear 4 4 write-only value1 No Timer 6 Interrupt is cleared. 0b0 value2 Timer 6 Interrupt is cleared. 0b1 T5C GPT Module 2 Timer5 Interrupt Status Clear 3 3 write-only value1 No Timer 5 Interrupt is cleared. 0b0 value2 Timer 5 Interrupt is cleared. 0b1 T4C GPT Module 1 Timer4 Interrupt Status Clear 2 2 write-only value1 No Timer 4 Interrupt is cleared. 0b0 value2 Timer 4 Interrupt is cleared. 0b1 T3C GPT Module 1 Timer3 Interrupt Status Clear 1 1 write-only value1 No Timer 3 Interrupt is cleared. 0b0 value2 Timer 3 Interrupt is cleared. 0b1 T2C GPT Module 1 Timer 2 Interrupt Status Clear 0 0 write-only value1 No Timer 2 Interrupt is cleared. 0b0 value2 Timer 2 Interrupt is cleared. 0b1 DMAIRC1 DMA Interrupt Control Register 1, RESET_TYPE_3 0x154 8 0x00 0xFF CH8 DMA ADC Channel 8 Interrupt Status (DMA channel 11) 7 7 read-only value1 No DMA Channel 8 Interrupt has occurred. 0b0 value2 DMA Channel 8 Interrupt has occurred. 0b1 CH7 DMA ADC Channel 7 Interrupt Status (DMA channel 10) 6 6 read-only value1 No DMA Channel 7 Interrupt has occurred. 0b0 value2 DMA Channel 7 Interrupt has occurred. 0b1 CH6 DMA ADC Channel 6 Interrupt Status (DMA channel 9) 5 5 read-only value1 No DMA Channel 6 Interrupt has occurred. 0b0 value2 DMA Channel 6 Interrupt has occurred. 0b1 CH5 DMA ADC Channel 5 Interrupt Status (DMA channel 8) 4 4 read-only value1 No DMA Channel 5 Interrupt has occurred. 0b0 value2 DMA Channel 5 Interrupt has occurred. 0b1 CH4 DMA ADC Channel 4 Interrupt Status (DMA channel 7) 3 3 read-only value1 No DMA Channel 4 Interrupt has occurred. 0b0 value2 DMA Channel 4 Interrupt has occurred. 0b1 CH3 DMA ADC Channel 3 Interrupt Status (DMA channel 6) 2 2 read-only value1 No DMA Channel 3 Interrupt has occurred. 0b0 value2 DMA Channel 3 Interrupt has occurred. 0b1 CH2 DMA ADC Channel 2 Interrupt Status (DMA channel 5) 1 1 read-only value1 No DMA Channel 2 Interrupt has occurred. 0b0 value2 DMA Channel 2 Interrupt has occurred. 0b1 CH1 DMA ADC Channel 1 Interrupt Status (DMA channel 4) 0 0 read-only value1 No DMA Channel 1 Interrupt has occurred. 0b0 value2 DMA Channel 1 Interrupt has occurred. 0b1 DMAIRC1CLR DMA Interrupt Control 1 Clear Register, RESET_TYPE_3 0x184 8 0x00 0xFF CH8C DMA ADC Channel 8 Interrupt Status (DMA channel 11) Clear 7 7 write-only value1 No DMA Channel 8 Interrupt is cleared. 0b0 value2 DMA Channel 8 Interrupt is cleared. 0b1 CH7C DMA ADC Channel 7 Interrupt Status (DMA channel 10) Clear 6 6 write-only value1 No DMA Channel 7 Interrupt is cleared. 0b0 value2 DMA Channel 7 Interrupt is cleared. 0b1 CH6C DMA ADC Channel 6 Interrupt Status (DMA channel 9) Clear 5 5 write-only value1 No DMA Channel 6 Interrupt is cleared. 0b0 value2 DMA Channel 6 Interrupt is cleared. 0b1 CH5C DMA ADC Channel 5 Interrupt Status (DMA channel 8) Clear 4 4 write-only value1 No DMA Channel 5 Interrupt is cleared. 0b0 value2 DMA Channel 5 Interrupt is cleared. 0b1 CH4C DMA ADC Channel 4 Interrupt Status (DMA channel 7) Clear 3 3 write-only value1 No DMA Channel 4 Interrupt is cleared. 0b0 value2 DMA Channel 4 Interrupt is cleared. 0b1 CH3C DMA ADC Channel 3 Interrupt Status (DMA channel 6) Clear 2 2 write-only value1 No DMA Channel 3 Interrupt is cleared. 0b0 value2 DMA Channel 3 Interrupt is cleared. 0b1 CH2C DMA ADC Channel 2 Interrupt Status (DMA channel 5) Clear 1 1 write-only value1 No DMA Channel 2 Interrupt is cleared. 0b0 value2 DMA Channel 2 Interrupt is cleared. 0b1 CH1C DMA ADC Channel 1 Interrupt Status (DMA channel 4) Clear 0 0 write-only value1 No DMA Channel 1 Interrupt is cleared. 0b0 value2 DMA Channel 1 Interrupt is cleared. 0b1 DMAIRC2 ADC1 Interrupt Control Register 2, RESET_TYPE_3 0x158 8 0x00 0xFF GPT12 DMA GPT12 Transfer Ready (DMA channel 12) 5 5 read-only value1 No DMA GPT12 Transfer Ready Interrupt has occurred. 0b0 value2 DMA GPT12 Transfer Ready Interrupt has occurred. 0b1 SSC2 DMA SSC2 Transfer Ready (DMA channel 3) 4 4 read-only value1 No DMA SSC2 Transfer Ready Interrupt has occurred. 0b0 value2 DMA SSC2 Transfer Ready Interrupt has occurred. 0b1 SSC1 DMA SSC1 Transfer Ready (DMA channel 2) 3 3 read-only value1 No DMA SSC1 Transfer Ready Interrupt has occurred. 0b0 value2 DMA SSC1 Transfer Ready Interrupt has occurred. 0b1 TRSEQ2DY DMA Transfer Sequence 2 Ready (DMA channel 1) 2 2 read-only value1 No Transfer Sequence Ready Interrupt has occurred. 0b0 value2 Transfer Sequence Ready Interrupt has occurred. 0b1 TRSEQ1DY DMA Transfer Sequence 1 Ready (DMA channel 0) 1 1 read-only value1 No Transfer Sequence Ready Interrupt has occurred. 0b0 value2 Transfer Sequence Ready Interrupt has occurred. 0b1 STRDY DMA Single Transfer Ready 0 0 read-only value1 No Single Transfer Interrupt has occurred. 0b0 value2 Single Transfer Ready Interrupt has occurred. 0b1 DMAIRC2CLR ADC1 Interrupt Control 2 Clear Register, RESET_TYPE_3 0x188 8 0x00 0xFF GPT12C DMA GPT12 Transfer Ready (DMA channel 12) Clear 5 5 write-only value1 No DMA GPT12 Transfer Ready Interrupt is cleared. 0b0 value2 DMA GPT12 Transfer Ready Interrupt is cleared. 0b1 SSC2C DMA SSC2 Transfer Ready (DMA channel 3) Clear 4 4 write-only value1 No DMA SSC2 Transfer Ready Interrupt is cleared. 0b0 value2 DMA SSC2 Transfer Ready Interrupt is cleared. 0b1 SSC1C DMA SSC1 Transfer Ready (DMA channel 2) Clear 3 3 write-only value1 No DMA SSC1 Transfer Ready Interrupt is cleared. 0b0 value2 DMA SSC1 Transfer Ready Interrupt is cleared. 0b1 TRSEQ2DYC DMA Transfer Sequence 2 Ready (DMA channel 1) Clear 2 2 write-only value1 No Transfer Sequence Ready Interrupt is cleared. 0b0 value2 Transfer Sequence Ready Interrupt is cleared. 0b1 TRSEQ1DYC DMA Transfer Sequence 1 Ready (DMA channel 0) Clear 1 1 write-only value1 No Transfer Sequence Ready Interrupt is cleared. 0b0 value2 Transfer Sequence Ready Interrupt is cleared. 0b1 NMISR NMI Status Register, RESET_TYPE_4 0x018 8 0x00 0xFF FNMISUP Supply Prewarning NMI Flag 7 7 read-only value1 No supply prewarning NMI has occurred. 0b0 value2 Supply prewarning has occurred. 0b1 FNMIECC ECC Error NMI Flag 6 6 read-only value1 No uncorrectable ECC error has occurred on NVM, XRAM. 0b0 value2 Uncorrectable ECC error has occurred on NVM, RAM. 0b1 FNMIMAP NVM Map Error NMI Flag 5 5 read-only value1 No NVM Map Error NMI has occurred. 0b0 value2 NVM Map Error has occurred. 0b1 FNMIOWD Oscillator Watchdog or MI_CLK Watchdog NMI Flag 4 4 read-only value1 No oscillator / MI_CLK watchdog NMI has occurred. 0b0 value2 Oscillator / MI_CLK watchdog event has occurred. 0b1 FNMIOT Over-temperature NMI Flag 3 3 read-only value1 No OT NMI has occurred. 0b0 value2 OT NMI event has occurred. 0b1 FNMINVM NVM Operation Complete NMI Flag 2 2 read-only value1 No NVM NMI has occurred. 0b0 value2 NVM operation complete event has occurred. 0b1 FNMIPLL PLL NMI Flag 1 1 read-only value1 No PLL NMI has occurred. 0b0 value2 PLL loss-of-lock has occurred. 0b1 FNMIWDT Watchdog Timer NMI Flag 0 0 read-only value1 No watchdog NMI has occurred. 0b0 value2 WDT prewarning has occurred. 0b1 NMICLR NMI Clear Register, RESET_TYPE_3 0x000 8 0x00 0xFF NMISUPC Supply Prewarning NMI Clear 7 7 write-only value1 Supply NMI is not cleared. 0b0 value2 Supply NMI is cleared. 0b1 NMIECCC ECC Error NMI Clear 6 6 write-only value1 ECC Error NMI is not cleared. 0b0 value2 ECC Error NMI is cleared. 0b1 NMIMAPC NVM Map Error NMI Clear 5 5 write-only value1 NVM Map Error NMI is not cleared. 0b0 value2 NVM Map Error NMI is cleared. 0b1 NMIOWDC Oscillator Watchdog NMI Clear 4 4 write-only value1 Oscillator watchdog NMI is not cleared. 0b0 value2 Oscillator watchdog NMI is cleared. 0b1 NMIOTC NMI OT Clear 3 3 write-only value1 NMI OT is not cleared. 0b0 value2 NMI OT is cleared. 0b1 NMINVMC NVM Operation Complete NMI Clear 2 2 write-only value1 NVM operation complete NMI is not cleared. 0b0 value2 NVM operation complete NMI is cleared. 0b1 NMIPLLC PLL Loss of Lock NMI Clear 1 1 write-only value1 PLL Loss of Lock NMI is not cleared. 0b0 value2 PLL Loss of Lock NMI is cleared. 0b1 NMIWDTC Watchdog Timer NMI Clear 0 0 write-only value1 WDT NMI is not cleared. 0b0 value2 WDT NMI is cleared. 0b1 PORT PORT 0x48028000 0x0 0x2000 registers P0_DATA Port 0 Data Register 0x00 8 0x00 0x00 P0 Port 0 Pin 0 Data Value 0 0 read-write value1 Port 0 pin n data value = 0 0b0 value2 Port 0 pin n data value = 1 0b1 P1 Port 0 Pin 1 Data Value 1 1 read-write value1 Port 0 pin n data value = 0 0b0 value2 Port 0 pin n data value = 1 0b1 P2 Port 0 Pin 2 Data Value 2 2 read-write value1 Port 0 pin n data value = 0 0b0 value2 Port 0 pin n data value = 1 0b1 P3 Port 0 Pin 3 Data Value 3 3 read-write value1 Port 0 pin n data value = 0 0b0 value2 Port 0 pin n data value = 1 0b1 P4 Port 0 Pin 4 Data Value 4 4 read-write value1 Port 0 pin n data value = 0 0b0 value2 Port 0 pin n data value = 1 0b1 P0_DIR Port 0 Direction Register 0x04 8 0x00 0xFF P0 Port 0 Pin 0 Direction Control 0 0 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P1 Port 0 Pin 1 Direction Control 1 1 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P2 Port 0 Pin 2 Direction Control 2 2 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P3 Port 0 Pin 3 Direction Control 3 3 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P4 Port 0 Pin 4 Direction Control 4 4 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P0_OD Port 0 Open Drain Control Register 0x40 8 0x00 0xFF P0 Port 0 Pin 0 Open Drain Mode 0 0 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P1 Port 0 Pin 1 Open Drain Mode 1 1 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P2 Port 0 Pin 2 Open Drain Mode 2 2 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P3 Port 0 Pin 3 Open Drain Mode 3 3 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P4 Port 0 Pin 4 Open Drain Mode 4 4 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P0_PUDSEL Port 0 Pull-Up/Pull-Down Select Register 0x18 8 0x0B 0xFF P0 Pull-Up/Pull-Down Select Port 0 Bit 0 0 0 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected 0b1 P1 Pull-Up/Pull-Down Select Port 0 Bit 1 1 1 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected 0b1 P2 Pull-Up/Pull-Down Select Port 0 Bit 2 2 2 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected 0b1 P3 Pull-Up/Pull-Down Select Port 0 Bit 3 3 3 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected 0b1 P4 Pull-Up/Pull-Down Select Port 0 Bit 4 4 4 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected 0b1 P0_PUDEN Port 0 Pull-Up/Pull-Down Enable Register 0x1C 8 0x1F 0xFF P0 Pull-Up/Pull-Down Enable at Port 0 Bit 0 0 0 read-write value1 Pull-up or Pull-down device is disabled 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P1 Pull-Up/Pull-Down Enable at Port 0 Bit 1 1 1 read-write value1 Pull-up or Pull-down device is disabled 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P2 Pull-Up/Pull-Down Enable at Port 0 Bit 2 2 2 read-write value1 Pull-up or Pull-down device is disabled 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P3 Pull-Up/Pull-Down Enable at Port 0 Bit 3 3 3 read-write value1 Pull-up or Pull-down device is disabled 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P4 Pull-Up/Pull-Down Enable at Port 0 Bit 4 4 4 read-write value1 Pull-up or Pull-down device is disabled 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P0_ALTSEL0 Port 0 Alternate Select Register 0x30 8 0x00 0xFF P0 Alternate Select Port 0 Bit 0 0 0 read-write P1 Alternate Select Port 0 Bit 1 1 1 read-write P2 Alternate Select Port 0 Bit 2 2 2 read-write P3 Alternate Select Port 0 Bit 3 3 3 read-write P4 Alternate Select Port 0 Bit 4 4 4 read-write P0_ALTSEL1 Port 0 Alternate Select Register 0x34 8 0x00 0xFF P0 Alternate Select Port 0 Bit 0 0 0 read-write P1 Alternate Select Port 0 Bit 1 1 1 read-write P2 Alternate Select Port 0 Bit 2 2 2 read-write P3 Alternate Select Port 0 Bit 3 3 3 read-write P4 Alternate Select Port 0 Bit 4 4 4 read-write P1_DATA Port 1 Data Register 0x08 8 0x00 0x00 P0 Port 1 Pin 0 Data Value 0 0 read-write value1 Port 1 pin n data value = 0 0b0 value2 Port 1 pin n data value = 1 0b1 P1 Port 1 Pin 1 Data Value 1 1 read-write value1 Port 1 pin n data value = 0 0b0 value2 Port 1 pin n data value = 1 0b1 P2 Port 1 Pin 2 Data Value 2 2 read-write value1 Port 1 pin n data value = 0 0b0 value2 Port 1 pin n data value = 1 0b1 P3 Port 1 Pin 3 Data Value 3 3 read-write value1 Port 1 pin n data value = 0 0b0 value2 Port 1 pin n data value = 1 0b1 P4 Port 1 Pin 4 Data Value 4 4 read-write value1 Port 1 pin n data value = 0 0b0 value2 Port 1 pin n data value = 1 0b1 P1_DIR Port 1 Direction Register 0x0C 8 0x00 0xFF P0 Port 1 Pin 0 Direction Control 0 0 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P1 Port 1 Pin 1 Direction Control 1 1 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P2 Port 1 Pin 2 Direction Control 2 2 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P3 Port 1 Pin 3 Direction Control 3 3 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P4 Port 1 Pin 4 Direction Control 4 4 read-write value1 Direction is set to input (default) 0b0 value2 Direction is set to output 0b1 P1_OD Port 1 Open Drain Control Register 0x44 8 0x00 0xFF P0 Port 1 Pin 0 Open Drain Mode 0 0 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P1 Port 1 Pin 1 Open Drain Mode 1 1 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P2 Port 1 Pin 2 Open Drain Mode 2 2 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P3 Port 1 Pin 3 Open Drain Mode 3 3 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P4 Port 1 Pin 4 Open Drain Mode 4 4 read-write value1 Normal Mode, output is actively driven for 0 and 1 state (default) 0b0 value2 Open Drain Mode, output is actively driven only for 0 state 0b1 P1_PUDSEL Port 1 Pull-Up/Pull-Down Select Register 0x20 8 0x1F 0xFF P0 Pull-Up/Pull-Down Select Port 1 Bit 0 0 0 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P1 Pull-Up/Pull-Down Select Port 1 Bit 1 1 1 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P2 Pull-Up/Pull-Down Select Port 1 Bit 2 2 2 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P3 Pull-Up/Pull-Down Select Port 1 Bit 3 3 3 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P4 Pull-Up/Pull-Down Select Port 1 Bit 4 4 4 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P1_PUDEN Port 1 Pull-Up/Pull-Down Enable Register 0x24 8 0x00 0xFF P0 Pull-Up/Pull-Down Enable at Port 1 Bit 0 0 0 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P1 Pull-Up/Pull-Down Enable at Port 1 Bit 1 1 1 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P2 Pull-Up/Pull-Down Enable at Port 1 Bit 2 2 2 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P3 Pull-Up/Pull-Down Enable at Port 1 Bit 3 3 3 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P4 Pull-Up/Pull-Down Enable at Port 1 Bit 4 4 4 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P1_ALTSEL0 Port 1 Alternate Select Register 0x38 8 0x00 0xFF P0 Alternate Select Port 1 Bit 0 0 0 read-write P1 Alternate Select Port 1 Bit 1 1 1 read-write P2 Alternate Select Port 1 Bit 2 2 2 read-write P3 Alternate Select Port 1 Bit 3 3 3 read-write P4 Alternate Select Port 1 Bit 4 4 4 read-write P1_ALTSEL1 Port 1 Alternate Select Register 0x3C 8 0x00 0xFF P0 Alternate Select Port 1 Bit 0 0 0 read-write P1 Alternate Select Port 1 Bit 1 1 1 read-write P2 Alternate Select Port 1 Bit 2 2 2 read-write P3 Alternate Select Port 1 Bit 3 3 3 read-write P4 Alternate Select Port 1 Bit 4 4 4 read-write P2_DATA Port 2 Data Register 0x10 8 0x00 0x00 P0 Port 2 Pin 0 Data Value 0 0 read-only value1 Port 2 pin n data value = 0 0b0 value2 Port 2 pin n data value = 1 0b1 P2 Port 2 Pin 2 Data Value 2 2 read-only value1 Port 2 pin n data value = 0 0b0 value2 Port 2 pin n data value = 1 0b1 P3 Port 2 Pin 3 Data Value 3 3 read-only value1 Port 2 pin n data value = 0 0b0 value2 Port 2 pin n data value = 1 0b1 P4 Port 2 Pin 4 Data Value 4 4 read-only value1 Port 2 pin n data value = 0 0b0 value2 Port 2 pin n data value = 1 0b1 P5 Port 2 Pin 5 Data Value 5 5 read-only value1 Port 2 pin n data value = 0 0b0 value2 Port 2 pin n data value = 1 0b1 P2_DIR Port 2 Direction Register 0x14 8 0xBF 0xFF P0 Port 2 Pin 0 Driver Control 0 0 read-write value1 Input driver is enabled 0b0 value2 Input driver is disabled (default) 0b1 P2 Port 2 Pin 2 Driver Control 2 2 read-write value1 Input driver is enabled 0b0 value2 Input driver is disabled (default) 0b1 P3 Port 2 Pin 3 Driver Control 3 3 read-write value1 Input driver is enabled 0b0 value2 Input driver is disabled (default) 0b1 P4 Port 2 Pin 4 Driver Control 4 4 read-write value1 Input driver is enabled 0b0 value2 Input driver is disabled (default) 0b1 P5 Port 2 Pin 5 Driver Control 5 5 read-write value1 Input driver is enabled 0b0 value2 Input driver is disabled (default) 0b1 P2_PUDSEL Port 2 Pull-Up/Pull-Down Select Register 0x28 8 0xBF 0xFF P0 Pull-Up/Pull-Down Select Port 2 Bit 0 0 0 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P2 Pull-Up/Pull-Down Select Port 2 Bit 2 2 2 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P3 Pull-Up/Pull-Down Select Port 2 Bit 3 3 3 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P4 Pull-Up/Pull-Down Select Port 2 Bit 4 4 4 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P5 Pull-Up/Pull-Down Select Port 2 Bit 5 5 5 read-write value1 Pull-down device is selected 0b0 value2 Pull-up device is selected (default) 0b1 P2_PUDEN Port 2 Pull-Up/Pull-Down Enable Register 0x2C 8 0x00 0xFF P0 Pull-Up/Pull-Down Enable at Port 2 Bit 0 0 0 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P2 Pull-Up/Pull-Down Enable at Port 2 Bit 2 2 2 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P3 Pull-Up/Pull-Down Enable at Port 2 Bit 3 3 3 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P4 Pull-Up/Pull-Down Enable at Port 2 Bit 4 4 4 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 P5 Pull-Up/Pull-Down Enable at Port 2 Bit 5 5 5 read-write value1 Pull-up or Pull-down device is disabled (default) 0b0 value2 Pull-up or Pull-down device is enabled 0b1 GPT12E GPT12E 0x40010000 0x0 0x4000 registers T2 Timer T2 Count Register 0x20 16 0x0000 0xFFFF T2 Timer T2 Current Value 0 15 read-write T3 Timer T3 Count Register 0x24 16 0x0000 0xFFFF T3 Timer T3 Current Value 0 15 read-write T4 Timer T4 Count Register 0x28 16 0x0000 0xFFFF T4 Timer T4 Current Value 0 15 read-write T3CON Timer T3 Control Register 0x0C 16 0x0000 0xFFFF T3I Timer T3 Input Parameter Selection 0 2 read-write T3M Timer T3 Mode Control 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reserved. Do not use this combination 0b100 value6 Reserved. Do not use this combination 0b101 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T3R Timer T3 Run Bit 6 6 read-write value1 Timer T3 stops 0b0 value2 Timer T3 runs 0b1 T3UD Timer T3 Up/Down Control 7 7 read-write value1 Timer T3 counts up 0b0 value2 Timer T3 counts down 0b1 T3UDE Timer T3 External Up/Down Enable 8 8 read-write value1 Count direction is controlled by bit T3UD; input T3EUD is disconnected 0b0 value2 Count direction is controlled by input T3EUD 0b1 T3OE Overflow/Underflow Output Enable 9 9 read-write value1 Alternate Output Function Disabled 0b0 value2 State of T3 toggle latch is output on pin T3OUT 0b1 T3OTL Timer T3 Overflow Toggle Latch 10 10 read-write BPS1 GPT1 Block Prescaler Control 11 12 read-write value1 fGPT/8 0b00 value2 fGPT/4 0b01 value3 fGPT/32 0b10 value4 fGPT/16 0b11 T3EDGE Timer T3 Edge Detection Flag 13 13 read-write value1 No count edge was detected 0b0 value2 A count edge was detected 0b1 T3CHDIR Timer T3 Count Direction Change Flag 14 14 read-write value1 No change of count direction was detected 0b0 value2 A change of count direction was detected 0b1 T3RDIR Timer T3 Rotation Direction Flag 15 15 read-only value1 Timer T3 counts up 0b0 value2 Timer T3 counts down 0b1 T2CON Timer T2 Control Register 0x08 16 0x0000 0xFFFF T2I Timer T2 Input Parameter Selection 0 2 read-write T2M Timer T2 Mode Control (Basic Operating Mode) 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reload Mode 0b100 value6 Capture Mode 0b101 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T2R Timer T2 Run Bit 6 6 read-write value1 Timer T2 stops 0b0 value2 Timer T2 runs 0b1 T2UD Timer T2 Up/Down Control 7 7 read-write value1 Timer T2 counts up 0b0 value2 Timer T2 counts down 0b1 T2UDE Timer T2 External Up/Down Enable 8 8 read-write value1 Count direction is controlled by bit T2UD; input T2EUD is disconnected 0b0 value2 Count direction is controlled by input T2EUD 0b1 T2RC Timer T2 Remote Control 9 9 read-write value1 Timer T2 is controlled by its own run bit T2R 0b0 value2 Timer T2 is controlled by the run bit T3R of core timer T3, not by bit T2R 0b1 T2IRDIS Timer T2 Interrupt Disable 12 12 read-write value1 Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is enabled 0b0 value2 Interrupt generation for T2CHDIR and T2EDGE interrupts in Incremental Interface Mode is disabled 0b1 T2EDGE Timer T2 Edge Detection 13 13 read-write value1 No count edge was detected 0b0 value2 A count edge was detected 0b1 T2CHDIR Timer T2 Count Direction Change 14 14 read-write value1 No change in count direction was detected 0b0 value2 A change in count direction was detected 0b1 T2RDIR Timer T2 Rotation Direction 15 15 read-only value1 Timer T2 counts up 0b0 value2 Timer T2 counts down 0b1 T4CON Timer T4 Control Register 0x10 16 0x0000 0xFFFF T4I Timer T4 Input Parameter Selection 0 2 read-write T4M Timer T4 Mode Control (Basic Operating Mode) 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reload Mode 0b100 value6 Capture Mode 0b101 value7 Incremental Interface Mode (Rotation Detection Mode) 0b110 value8 Incremental Interface Mode (Edge Detection Mode) 0b111 T4R Timer T4 Run Bit 6 6 read-write value1 Timer T4 stops 0b0 value2 Timer T4 runs 0b1 T4UD Timer T4 Up/Down Control 7 7 read-write value1 Timer T4 counts up 0b0 value2 Timer T4 counts down 0b1 T4UDE Timer T4 External Up/Down Enable 8 8 read-write value1 Count direction is controlled by bit T4UD; input T4EUD is disconnected 0b0 value2 Count direction is controlled by input T4EUD 0b1 T4RC Timer T4 Remote Control 9 9 read-write value1 Timer T4 is controlled by its own run bit T4R 0b0 value2 Timer T4 is controlled by the run bit T3R of core timer T3, but not by bit T4R 0b1 CLRT2EN Clear Timer T2 Enable 10 10 read-write value1 No effect of T4EUD on timer T2 0b0 value2 A falling edge on T4EUD clears timer T2 0b1 CLRT3EN Clear Timer T3 Enable 11 11 read-write value1 No effect of T4IN on timer T3 0b0 value2 A falling edge on T4IN clears timer T3 0b1 T4IRDIS Timer T4 Interrupt Disable 12 12 read-write value1 Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is enabled 0b0 value2 Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is disabled 0b1 T4EDGE Timer T4 Edge Detection 13 13 read-write value1 No count edge was detected 0b0 value2 A count edge was detected 0b1 T4CHDIR Timer T4 Count Direction Change 14 14 read-write value1 No change in count direction was detected 0b0 value2 A change in count direction was detected 0b1 T4RDIR Timer T4 Rotation Direction 15 15 read-only value1 Timer T4 counts up 0b0 value2 Timer T4 counts down 0b1 T5 Timer 5 Count Register 0x2C 16 0x0000 0xFFFF T5 Timer T5 Current Value 0 15 read-write T6 Timer T6 Count Register 0x30 16 0x0000 0xFFFF T6 Timer T6 Current Value 0 15 read-write CAPREL Capture/Reload Register 0x1C 16 0x0000 0xFFFF CAPREL Current reload value or Captured value 0 15 read-write T6CON Timer T6 Control Register 0x18 16 0x0000 0xFFFF T6I Timer T6 Input Parameter Selection 0 2 read-write T6M Timer T6 Mode Control (Basic Operating Mode) 3 5 read-write value1 Timer Mode 0b000 value2 Counter Mode 0b001 value3 Gated Timer Mode with gate active low 0b010 value4 Gated Timer Mode with gate active high 0b011 value5 Reserved. Do not use this combination. 0b100 value6 Reserved. Do not use this combination. 0b101 value7 Reserved. Do not use this combination. 0b110 value8 Reserved. Do not use this combination. 0b111 T6R Timer T6 Run Bit 6 6 read-write value1 Timer T6 stops 0b0 value2 Timer T6 runs 0b1 T6UD Timer T6 Up/Down Control 7 7 read-write value1 Timer T6 counts up 0b0 value2 Timer T6 counts down 0b1 T6UDE Timer T6 External Up/Down Enable 8 8 read-write value1 Count direction is controlled by bit T6UD; input T6EUD is disconnected 0b0 value2 Count direction is controlled by input T6EUD 0b1 T6OE Overflow/Underflow Output Enable 9 9 read-write value1 Alternate Output Function Disabled 0b0 value2 State of timer T6 toggle latch is output on pin T6OUT 0b1 T6OTL Timer T6 Overflow Toggle Latch 10 10 read-write BPS2 GPT2 Block Prescaler Control 11 12 read-write value1 fGPT/4 0b00 value2 fGPT/2 0b01 value3 fGPT/16 0b10 value4 fGPT/8 0b11 T6CLR Timer T6 Clear Enable Bit 14 14 read-write value1 Timer T6 is not cleared on a capture event 0b0 value2 Timer T6 is cleared on a capture event 0b1 T6SR Timer T6 Reload Mode Enable 15 15 read-write value1 Reload from register CAPREL disabled 0b0 value2 Reload from register CAPREL enabled 0b1 T5CON Timer 5 Control Register 0x14 16 0x0000 0xFFFF T5I Timer T5 Input Parameter Selection 0 2 read-write T5M Timer T5 Mode Control (Basic Operating Mode) 3 4 read-write value1 Timer Mode 0b00 value2 Counter Mode 0b01 value3 Gated Timer Mode with gate active low 0b10 value4 Gated Timer Mode with gate active high 0b11 T5R Timer T5 Run Bit 6 6 read-write value1 Timer T5 stops 0b0 value2 Timer T5 runs 0b1 T5UD Timer T5 Up/Down Control 7 7 read-write value1 Timer T5 counts up 0b0 value2 Timer T5 counts down 0b1 T5UDE Timer T5 External Up/Down Enable 8 8 read-write value1 Count direction is controlled by bit T5UD; input T5EUD is disconnected 0b0 value2 Count direction is controlled by input T5EUD 0b1 T5RC Timer T5 Remote Control 9 9 read-write value1 Timer T5 is controlled by its own run bit T5R 0b0 value2 Timer T5 is controlled by the run bit T6R of core timer T6, not by bit T5R 0b1 CT3 Timer T3 Capture Trigger Enable 10 10 read-write value1 Capture trigger from input line CAPIN 0b0 value2 Capture trigger from T3 input lines T3IN and/or T3EUD 0b1 CI Register CAPREL Capture Trigger Selection 12 13 read-write value1 Capture disabled 0b00 value2 Positive transition (rising edge) on CAPIN or any transition on T3IN 0b01 value3 Negative transition (falling edge) on CAPIN or any transition on T3EUD 0b10 value4 Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD 0b11 T5CLR Timer T5 Clear Enable Bit 14 14 read-write value1 Timer T5 is not cleared on a capture event 0b0 value2 Timer T5 is cleared on a capture event 0b1 T5SC Timer T5 Capture Mode Enable 15 15 read-write value1 Capture into register CAPREL disabled 0b0 value2 Capture into register CAPREL enabled 0b1 PISEL Port Input Select Register 0x04 16 0x0000 0xFFFF IST2IN Input Select for T2IN 0 0 read-write value1 Signal T2INA is selected 0b0 value2 Signal T2INB is selected 0b1 IST2EUD Input Select for T2EUD 1 1 read-write value1 Signal T2EUDA is selected 0b0 value2 Signal T2EUDB is selected 0b1 IST3IN Input Select for T3IN 2 3 read-write value1 Signal T3INA is selected 0b00 value2 Signal T3INB is selected 0b01 value3 Signal T3INC is selected 0b10 value4 Signal T3IND is selected 0b11 IST3EUD Input Select for T3EUD 4 5 read-write value1 Signal T3EUDA is selected 0b00 value2 Signal T3EUDB is selected 0b01 value3 Signal T3EUDC is selected 0b10 value4 Signal T3EUDD is selected 0b11 IST4IN Input Select for T4IN 6 7 read-write value1 Signal T4INA is selected 0b00 value2 Signal T4INB is selected 0b01 value3 Signal T4INC is selected 0b10 value4 Signal T4IND is selected 0b11 IST4EUD Input Select for T4EUD 8 9 read-write value1 Signal T4EUDA is selected 0b00 value2 Signal T4EUDB is selected 0b01 value3 Signal T4EUDC is selected 0b10 value4 Signal T4EUDD is selected 0b11 IST5IN Input Select for T5IN 10 10 read-write value1 Signal T5INA is selected 0b0 value2 Signal T5INB is selected 0b1 IST5EUD Input Select for T5EUD 11 11 read-write value1 Signal T5EUDA is selected 0b0 value2 Signal T5EUDB is selected 0b1 IST6IN Input Select for T6IN 12 12 read-write value1 Signal T6INA is selected 0b0 value2 Signal T6INB is selected 0b1 IST6EUD Input Select for T6EUD 13 13 read-write value1 Signal T6EUDA is selected 0b0 value2 Signal T6EUDB is selected 0b1 ISCAPIN Input Select for CAPIN 14 15 read-write value1 Signal CAPINA is selected 0b00 value2 Signal CAPINB is selected 0b01 value3 Signal CAPINC (Read trigger from T3) is selected 0b10 value4 Signal CAPIND (Read trigger from T2 or T3 or T4) is selected 0b11 ID Module Identification Register 0x00 16 0x5804 0xFFFF MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Identification Number 8 15 read-only TIMER2 TIMER2 0x48004000 0x0 0x1000 registers T2MOD Timer 2 Mode Register 0x04 8 0x00 0xFF DCEN Up/Down Counter Enable 0 0 read-write value1 Up/Down Counter function is disabled 0b0 value2 Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0) 0b1 T2PRE Timer 2 Prescaler Bit 1 3 read-write value1 fT2 = fPCLK 0b000 value2 fT2 = fPCLK / 2 0b001 value3 fT2 = fPCLK / 4 0b010 value4 fT2 = fPCLK / 8 0b011 value5 fT2 = fPCLK / 16 0b100 value6 fT2 = fPCLK / 32 0b101 value7 fT2 = fPCLK / 64 0b110 value8 fT2 = fPCLK / 128 0b111 PREN Prescaler Enable 4 4 read-write value1 Prescaler is disabled and the 2 or 12 divider takes effect. 0b0 value2 Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed. 0b1 EDGESEL Edge Select in Capture Mode/Reload Mode 5 5 read-write value1 The falling edge at Pin T2EX is selected. 0b0 value2 The rising edge at Pin T2EX is selected. 0b1 T2RHEN Timer 2 External Start Enable 6 6 read-write value1 Timer 2 External Start is disabled. 0b0 value2 Timer 2 External Start is enabled. 0b1 T2REGS Edge Select for Timer 2 External Start 7 7 read-write value1 The falling edge at Pin T2EX is selected. 0b0 value2 The rising edge at Pin T2EX is selected. 0b1 T2CON Timer 2 Control Register 0x00 8 0x00 0xFF CP_RL2 Capture/Reload Select 0 0 read-write value1 Reload upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1). 0b0 value2 Capture Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1.The negative or positive transition at Pin T2EX is selected by bit EDGESEL. 0b1 C_T2 Timer or Counter Select 1 1 read-write value1 Timer function selected. 0b0 value2 Count upon negative edge at pin T2. 0b1 TR2 Timer 2 Start/Stop Control 2 2 read-write value1 Stop Timer 2. 0b0 value2 Start Timer 2. 0b1 EXEN2 Timer 2 External Enable Control 3 3 read-write value1 External events are disabled. 0b0 value2 External events are enabled in Capture/Reload Mode. 0b1 EXF2 Timer 2 External Flag 6 6 read-only TF2 Timer 2 Overflow/Underflow Flag 7 7 read-only T2ICLR Timer 2 Interrupt Clear Register 0x1C 8 0x00 0xFF EXF2CLR External Interrupt Clear Flag 6 6 write-only value1 External interrupt is not cleared. 0b0 value2 External interrupt is cleared. 0b1 TF2CLR Overflow/Underflow Interrupt Clear Flag 7 7 write-only value1 Overflow/underflow interrupt is not cleared. 0b0 value2 Overflow/underflow interrupt is cleared. 0b1 T2CON1 Timer 2 Control Register 1 0x18 8 0x03 0xFF EXF2EN External Interrupt Enable 0 0 read-write value1 External interrupt is disabled. 0b0 value2 External interrupt is enabled. 0b1 TF2EN Overflow/Underflow Interrupt Enable 1 1 read-write value1 Overflow/underflow interrupt is disabled. 0b0 value2 Overflow/underflow interrupt is enabled. 0b1 RC2L Timer 2 Reload/Capture Register, Low Byte 0x08 8 0x00 0xFF RC2 Reload/Capture Value 0 7 read-write RC2H Timer 2 Reload/Capture Register, High Byte 0x0C 8 0x00 0xFF RC2 Reload/Capture Value 0 7 read-write T2L Timer 2, Low Byte 0x10 8 0x00 0xFF T2L Timer 2 Value 0 7 read-write T2H Timer 2, High Byte 0x14 8 0x00 0xFF T2H Timer 2 Value 0 7 read-write TIMER21 TIMER21 0x48005000 0x0 0x1000 registers T2MOD Timer 2 Mode Register 0x04 8 0x00 0xFF DCEN Up/Down Counter Enable 0 0 read-write value1 Up/Down Counter function is disabled 0b0 value2 Up/Down Counter function is enabled and controlled by pin T2EX (Up = 1, Down = 0) 0b1 T2PRE Timer 2 Prescaler Bit 1 3 read-write value1 fT2 = fPCLK 0b000 value2 fT2 = fPCLK / 2 0b001 value3 fT2 = fPCLK / 4 0b010 value4 fT2 = fPCLK / 8 0b011 value5 fT2 = fPCLK / 16 0b100 value6 fT2 = fPCLK / 32 0b101 value7 fT2 = fPCLK / 64 0b110 value8 fT2 = fPCLK / 128 0b111 PREN Prescaler Enable 4 4 read-write value1 Prescaler is disabled and the 2 or 12 divider takes effect. 0b0 value2 Prescaler is enabled (see T2PRE bit) and the 2 or 12 divider is bypassed. 0b1 EDGESEL Edge Select in Capture Mode/Reload Mode 5 5 read-write value1 The falling edge at Pin T2EX is selected. 0b0 value2 The rising edge at Pin T2EX is selected. 0b1 T2RHEN Timer 2 External Start Enable 6 6 read-write value1 Timer 2 External Start is disabled. 0b0 value2 Timer 2 External Start is enabled. 0b1 T2REGS Edge Select for Timer 2 External Start 7 7 read-write value1 The falling edge at Pin T2EX is selected. 0b0 value2 The rising edge at Pin T2EX is selected. 0b1 T2CON Timer 2 Control Register 0x00 8 0x00 0xFF CP_RL2 Capture/Reload Select 0 0 read-write value1 Reload upon overflow or upon negative/positive transition at pin T2EX (when EXEN2 = 1). 0b0 value2 Capture Timer 2 data register contents on the negative/positive transition at pin T2EX, provided EXEN2 = 1.The negative or positive transition at Pin T2EX is selected by bit EDGESEL. 0b1 C_T2 Timer or Counter Select 1 1 read-write value1 Timer function selected. 0b0 value2 Count upon negative edge at pin T2. 0b1 TR2 Timer 2 Start/Stop Control 2 2 read-write value1 Stop Timer 2. 0b0 value2 Start Timer 2. 0b1 EXEN2 Timer 2 External Enable Control 3 3 read-write value1 External events are disabled. 0b0 value2 External events are enabled in Capture/Reload Mode. 0b1 EXF2 Timer 2 External Flag 6 6 read-only TF2 Timer 2 Overflow/Underflow Flag 7 7 read-only T2ICLR Timer 2 Interrupt Clear Register 0x1C 8 0x00 0xFF EXF2CLR External Interrupt Clear Flag 6 6 write-only value1 External interrupt is not cleared. 0b0 value2 External interrupt is cleared. 0b1 TF2CLR Overflow/Underflow Interrupt Clear Flag 7 7 write-only value1 Overflow/underflow interrupt is not cleared. 0b0 value2 Overflow/underflow interrupt is cleared. 0b1 T2CON1 Timer 2 Control Register 1 0x18 8 0x03 0xFF EXF2EN External Interrupt Enable 0 0 read-write value1 External interrupt is disabled. 0b0 value2 External interrupt is enabled. 0b1 TF2EN Overflow/Underflow Interrupt Enable 1 1 read-write value1 Overflow/underflow interrupt is disabled. 0b0 value2 Overflow/underflow interrupt is enabled. 0b1 RC2L Timer 2 Reload/Capture Register, Low Byte 0x08 8 0x00 0xFF RC2 Reload/Capture Value 0 7 read-write RC2H Timer 2 Reload/Capture Register, High Byte 0x0C 8 0x00 0xFF RC2 Reload/Capture Value 0 7 read-write T2L Timer 2, Low Byte 0x10 8 0x00 0xFF T2L Timer 2 Value 0 7 read-write T2H Timer 2, High Byte 0x14 8 0x00 0xFF T2H Timer 2 Value 0 7 read-write CCU6 CCU6 0x4000C000 0x0 0x4000 registers PISEL0 Port Input Select Register 0 0x6C 16 0x0000 0xFFFF ISCC60 Input Select for CC60 0 1 read-write value1 The input pin for CC60_0. 0b00 value2 The input pin for CC60_1. 0b01 value3 The input pin for CC60_2. 0b10 ISCC61 Input Select for CC61 2 3 read-write value1 The input pin for CC61_0. 0b00 value2 The input pin for CC61_1. 0b01 ISCC62 Input Select for CC62 4 5 read-write value1 The input pin for CC62_0. 0b00 value2 The input pin for CC62_1. 0b01 value3 The input pin for CC62_2. 0b10 ISTRP Input Select for CTRAP 6 7 read-write value1 The input pin for CTRAP_0. 0b00 value2 The input pin for CTRAP_1. 0b01 ISPOS0 Input Select for CCPOS0 8 9 read-write CCPOS0_0 The input pin for CCPOS0_0. 0b00 CCPOS0_1 The input pin for CCPOS0_1. 0b01 CCPOS0_2 The input pin for CCPOS0_2. 0b10 CCPOS0_3 The input pin for CCPOS0_3. 0b11 ISPOS1 Input Select for CCPOS1 10 11 read-write CCPO1_0 The input pin for CCPOS1_0. 0b00 CCPO1_1 The input pin for CCPOS1_1. 0b01 CCPO1_2 The input pin for CCPOS1_2. 0b10 ISPOS2 Input Select for CCPOS2 12 13 read-write CCPOS2_0 The input pin for CCPOS2_0. 0b00 CCPOS2_1 The input pin for CCPOS2_1. 0b01 CCPOS2_2 The input pin for CCPOS2_2. 0b10 CCPOS2_3 The input pin for CCPOS2_3. 0b11 IST12HR Input Select for T12HR 14 15 read-write value1 Either signal T12HRA (if T12EXT = 0) or T12HRE (if T12EXT = 1) is selected. 0b00 value2 Either signal T12HRB (if T12EXT = 0) or T12HRF (if T12EXT = 1) is selected. 0b01 value3 Either signal T12HRC (if T12EXT = 0) or T12HRG (if T12EXT = 1) is selected. 0b10 value4 Either signal T12HRD (if T12EXT = 0) or T12HRH (if T12EXT = 1) is selected. 0b11 PISEL2 Port Input Select Register 2 0x74 16 0x00 0xFF IST13HR Input Select for T13HR 0 1 read-write value1 Either signal T13HRA (if T13EXT = 0) or T13HRE (if T13EXT = 1) is selected. 0b00 value2 Either signal T13HRB (if T13EXT = 0) or T13HRF (if T13EXT = 1) is selected. 0b01 value3 Either signal T13HRC (if T13EXT = 0) or T13HRG (if T13EXT = 1) is selected. 0b10 value4 Either signal T13HRD (if T13EXT = 0) or T13HRH (if T13EXT = 1) is selected. 0b11 ISCNT12 Input Select for T12 Counting Input 2 3 read-write value1 The T12 prescaler generates the counting events. Bit TCTR4.T12CNT is not taken into account. 0b00 value2 Bit TCTR4.T12CNT written with 1 is a counting event. The T12 prescaler is not taken into account. 0b01 value3 The timer T12 is counting each rising edge detected in the selected T12HR signal. 0b10 value4 The timer T12 is counting each falling edge detected in the selected T12HR signal. 0b11 ISCNT13 Input Select for T13 Counting Input 4 5 read-write value1 The T13 prescaler generates the counting events. Bit TCTR4.T13CNT is not taken into account. 0b00 value2 Bit TCTR4.T13CNT written with 1 is a counting event. The T13 prescaler is not taken into account. 0b01 value3 The timer T13 is counting each rising edge detected in the selected T13HR signal. 0b10 value4 The timer T13 is counting each falling edge detected in the selected T13HR signal. 0b11 T12EXT Extension for T12HR Inputs 6 6 read-write value1 One of the signals T12HR[D:A] is selected. 0b0 value2 One of the signals T12HR[H:E] is selected. 0b1 T13EXT Extension for T13HR Inputs 7 7 read-write value1 One of the signals T13HR[D:A] is selected. 0b0 value2 One of the signals T13HR[H:E] is selected. 0b1 T12MSEL Capture/Compare T12 Mode Select Register 0x40 16 0x0000 0xFFFF MSEL60 Capture/Compare Mode Selection 0 3 read-write value1 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 value2 Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 value3 Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 value4 Compare output on pins COUT6n and CC6n. 0b0011 value5 Double-Register Capture modes, see . 0b01XX value6 Hall Sensor mode, see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 value7 Hysteresis-like mode, see . 0b1001 value8 Multi-Input Capture modes, see . 0b101X value9 Multi-Input Capture modes, see . 0b11XX MSEL61 Capture/Compare Mode Selection 4 7 read-write value1 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 value2 Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 value3 Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 value4 Compare output on pins COUT6n and CC6n. 0b0011 value5 Double-Register Capture modes, see . 0b01XX value6 Hall Sensor mode, see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 value7 Hysteresis-like mode, see . 0b1001 value8 Multi-Input Capture modes, see . 0b101X value9 Multi-Input Capture modes, see . 0b11XX MSEL62 Capture/Compare Mode Selection 8 11 read-write value1 Compare outputs disabled, pins CC6n and COUT6n can be used for I/O. No capture action. 0b0000 value2 Compare output on pin CC6n, pin COUT6n can be used for I/O. No capture action. 0b0001 value3 Compare output on pin COUT6n, pin CC6n can be used for I/O. No capture action. 0b0010 value4 Compare output on pins COUT6n and CC6n. 0b0011 value5 Double-Register Capture modes, see . 0b01XX value6 Hall Sensor mode, see . In order to enable the hall edge detection, all three MSEL6x must be programmed to Hall Sensor mode. 0b1000 value7 Hysteresis-like mode, see . 0b1001 value8 Multi-Input Capture modes, see . 0b101X value9 Multi-Input Capture modes, see . 0b11XX HSYNC Hall Synchronization 12 14 read-write value1 Any edge at one of the inputs CCPOSx (x = 0, 1, 2) triggers the sampling. 0b000 value2 A T13 compare-match triggers the sampling. 0b001 value3 A T13 period-match triggers the sampling. 0b010 value4 The Hall sampling triggered by hardware sources is switched off. 0b011 value5 A T12 period-match (while counting up) triggers the sampling. 0b100 value6 A T12 one-match (while counting down) triggers the sampling. 0b101 value7 A T12 compare-match of channel 0 (while counting up) triggers the sampling. 0b110 value8 A T12 compare-match of channel 0 (while counting down) triggers the sampling. 0b111 DBYP Delay Bypass 15 15 read-write value1 The delay bypass is not active. The dead-time counter DTC0 is generating a delay after the source signal becomes active. 0b0 value2 The delay bypass is active. The dead-time counter DTC0 is not used by the sampling of the Hall pattern. 0b1 T12 Timer T12 Counter Register 0x78 16 0x00 0xFF T12CV Timer T12 Counter Value 0 15 read-write T12PR Timer T12 Period Register 0x24 16 0x0000 0xFFFF T12PV T12 Period Value 0 15 read-write CC60R Capture/Compare Register for Channel CC60 0x34 16 0x0000 0xFFFF CCV Channel x Capture/Compare Value 0 15 read-only CC61R Capture/Compare Register for Channel CC61 0x38 16 0x0000 0xFFFF CCV Channel x Capture/Compare Value 0 15 read-only CC62R Capture/Compare Register for Channel CC62 0x3C 16 0x0000 0xFFFF CCV Channel x Capture/Compare Value 0 15 read-only CC60SR Capture/Compare Shadow Register for Channel CC60 0x14 16 0x0000 0xFFFF CCS Shadow Register for Channel x Capture/Compare Value 0 15 read-write CC61SR Capture/Compare Shadow Register for Channel CC61 0x18 16 0x0000 0xFFFF CCS Shadow Register for Channel x Capture/Compare Value 0 15 read-write CC62SR Capture/Compare Shadow Register for Channel CC62 0x1C 16 0x0000 0xFFFF CCS Shadow Register for Channel x Capture/Compare Value 0 15 read-write T12DTC Timer T12 Dead-Time Control Register 0x2C 16 0x0000 0xFFFF DTM Dead-Time 0 7 read-write DTE0 Dead-Time Enable Bits 8 8 read-write value1 Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 value2 Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTE1 Dead-Time Enable Bits 9 9 read-write value1 Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 value2 Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTE2 Dead-Time Enable Bits 10 10 read-write value1 Dead-time generation is disabled. The corresponding outputs switch from the passive state to the active state (according to the actual compare status) without any delay. 0b0 value2 Dead-time generation is enabled. The corresponding outputs switch from the passive state to the active state (according to the compare status) with the delay programmed in bit field DTM. 0b1 DTR0 Dead-Time Run Indication Bits 12 12 read-only value1 The value of the corresponding dead-time counter channel is 0. 0b0 value2 The value of the corresponding dead-time counter channel is not 0. 0b1 DTR1 Dead-Time Run Indication Bits 13 13 read-only value1 The value of the corresponding dead-time counter channel is 0. 0b0 value2 The value of the corresponding dead-time counter channel is not 0. 0b1 DTR2 Dead-Time Run Indication Bits 14 14 read-only value1 The value of the corresponding dead-time counter channel is 0. 0b0 value2 The value of the corresponding dead-time counter channel is not 0. 0b1 T13 Timer T13 Counter Register 0x7C 16 0x0000 0xFFFF T13CV Timer T13 Counter Value 0 15 read-write T13PR Timer T13 Period Register 0x28 16 0x0000 0xFFFF T13PV T13 Period Value 0 15 read-write CC63R Capture/Compare Register for Channel CC63 0x00 16 0x0000 0xFFFF CCV Channel CC63 Compare Value 0 15 read-only CC63SR Capture/Compare Shadow Register for Channel CC63 0x20 16 0x0000 0xFFFF CCS Shadow Register for Channel CC63 Compare Value 0 15 read-write CMPSTAT Compare State Register 0x80 16 0x0000 0xFFFF CC60ST Capture/Compare State Bits (x = 0, 1, 2, 3) 0 0 read-only value1 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 value2 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CC61ST Capture/Compare State Bits (x = 0, 1, 2, 3) 1 1 read-only value1 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 value2 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CC62ST Capture/Compare State Bits (x = 0, 1, 2, 3) 2 2 read-only value1 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 value2 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CC63ST Capture/Compare State Bits (x = 0, 1, 2, 3) 6 6 read-only value1 In compare mode, the timer count is less than the compare value. In capture mode, the selected edge has not yet been detected since the bit has been reset by software the last time. 0b0 value2 In compare mode, the counter value is greater than or equal to the compare value. In capture mode, the selected edge has been detected. 0b1 CCPOS0 Sampled Hall Pattern Bits (x = 0, 1, 2) 3 3 read-only value1 The input CCPOSx has been sampled as 0. 0b0 value2 The input CCPOSx has been sampled as 1. 0b1 CCPOS1 Sampled Hall Pattern Bits (x = 0, 1, 2) 4 4 read-only value1 The input CCPOSx has been sampled as 0. 0b0 value2 The input CCPOSx has been sampled as 1. 0b1 CCPOS2 Sampled Hall Pattern Bits (x = 0, 1, 2) 5 5 read-only value1 The input CCPOSx has been sampled as 0. 0b0 value2 The input CCPOSx has been sampled as 1. 0b1 CC60PS Passive State Select for Compare Outputs 8 8 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC61PS Passive State Select for Compare Outputs 10 10 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 CC62PS Passive State Select for Compare Outputs 12 12 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT60PS Passive State Select for Compare Outputs 9 9 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT61PS Passive State Select for Compare Outputs 11 11 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT62PS Passive State Select for Compare Outputs 13 13 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 COUT63PS Passive State Select for Compare Outputs 14 14 read-write value1 The corresponding compare output drives passive level while CC6xST is 0. 0b0 value2 The corresponding compare output drives passive level while CC6xST is 1. 0b1 T13IM T13 Inverted Modulation 15 15 read-write value1 T13 output is not inverted. 0b0 value2 T13 output is inverted for further modulation. 0b1 CMPMODIF Compare State Modification Register 0x10 16 0x0000 0xFFFF MCC60S Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3) 0 0 write-only MCC61S Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3) 1 1 write-only MCC62S Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3) 2 2 write-only MCC63S Capture/Compare Status Modification Bits (Set) (x = 0, 1, 2, 3) 6 6 write-only MCC60R Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3) 8 8 write-only MCC61R Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3) 9 9 write-only MCC62R Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3) 10 10 write-only MCC63R Capture/Compare Status Modification Bits (Reset) (x = 0, 1, 2, 3) 14 14 write-only TCTR0 Timer Control Register 0 0x30 16 0x0000 0xFFFF T12CLK Timer T12 Input Clock Select 0 2 read-write value1 fT12 = fCCU 0b000 value2 fT12 = fCCU / 2 0b001 value3 fT12 = fCCU / 4 0b010 value4 fT12 = fCCU / 8 0b011 value5 fT12 = fCCU / 16 0b100 value6 fT12 = fCCU / 32 0b101 value7 fT12 = fCCU / 64 0b110 value8 fT12 = fCCU / 128 0b111 T12PRE Timer T12 Prescaler Bit 3 3 read-write value1 The additional prescaler for T12 is disabled. 0b0 value2 The additional prescaler for T12 is enabled. 0b1 T12R Timer T12 Run Bit 4 4 read-only value1 Timer T12 is stopped. 0b0 value2 Timer T12 is running. 0b1 STE12 Timer T12 Shadow Transfer Enable 5 5 read-only value1 The shadow register transfer is disabled. 0b0 value2 The shadow register transfer is enabled. 0b1 CDIR Count Direction of Timer T12 6 6 read-only value1 T12 counts up. 0b0 value2 T12 counts down. 0b1 CTM T12 Operating Mode 7 7 read-write value1 Edge-aligned Mode: T12 always counts up and continues counting from zero after reaching the period value. 0b0 value2 Center-aligned Mode: T12 counts down after detecting a period-match and counts up after detecting a one-match. 0b1 T13CLK Timer T13 Input Clock Select 8 10 read-write value1 fT13 = fCCU 0b000 value2 fT13 = fCCU / 2 0b001 value3 fT13 = fCCU / 4 0b010 value4 fT13 = fCCU / 8 0b011 value5 fT13 = fCCU / 16 0b100 value6 fT13 = fCCU / 32 0b101 value7 fT13 = fCCU / 64 0b110 value8 fT13 = fCCU / 128 0b111 T13PRE Timer T13 Prescaler Bit 11 11 read-write value1 The additional prescaler for T13 is disabled. 0b0 value2 The additional prescaler for T13 is enabled. 0b1 T13R Timer T13 Run Bit 12 12 read-only value1 Timer T13 is stopped. 0b0 value2 Timer T13 is running. 0b1 STE13 Timer T13 Shadow Transfer Enable 13 13 read-only value1 The shadow register transfer is disabled. 0b0 value2 The shadow register transfer is enabled. 0b1 TCTR2 Timer Control Register 2 0x58 16 0x0000 0xFFFF T12SSC Timer T12 Single Shot Control 0 0 read-write value1 The single-shot mode is disabled, no hardware action on T12R. 0b0 value2 The single shot mode is enabled, the bit T12R is reset by hardware if: - T12 reaches its period value in edge-aligned mode - T12 reaches the value 1 while down counting in center-aligned mode. In parallel to the reset action of bit T12R, the bits CC6xST (x = 0, 1, 2) are reset. 0b1 T13SSC Timer T13 Single Shot Control 1 1 read-write value1 No hardware action on T13R 0b0 value2 The single-shot mode is enabled, the bit T13R is reset by hardware if T13 reaches its period value. In parallel to the reset action of bit T13R, the bit CC63ST is reset. 0b1 T13TEC T13 Trigger Event Control 2 4 read-write value1 no action 0b000 value2 set T13R on a T12 compare event on channel 0 0b001 value3 set T13R on a T12 compare event on channel 1 0b010 value4 set T13R on a T12 compare event on channel 2 0b011 value5 set T13R on any T12 compare event on the channels 0, 1, or 2 0b100 value6 set T13R upon a period-match of T12 0b101 value7 set T13R upon a zero-match of T12 (while counting up) 0b110 value8 set T13R on any edge of inputs CCPOSx 0b111 T13TED Timer T13 Trigger Event Direction 5 6 read-write value1 no action 0b00 value2 while T12 is counting up 0b01 value3 while T12 is counting down 0b10 value4 independent on the count direction of T12 0b11 T12RSEL Timer T12 External Run Selection 8 9 read-write value1 The external setting of T12R is disabled. 0b00 value2 Bit T12R is set if a rising edge of signal T12HR is detected. 0b01 value3 Bit T12R is set if a falling edge of signal T12HR is detected. 0b10 value4 Bit T12R is set if an edge of signal T12HR is detected. 0b11 T13RSEL Timer T13 External Run Selection 10 11 read-write value1 The external setting of T13R is disabled. 0b00 value2 Bit T13R is set if a rising edge of signal T13HR is detected. 0b01 value3 Bit T13R is set if a falling edge of signal T13HR is detected. 0b10 value4 Bit T13R is set if an edge of signal T13HR is detected. 0b11 TCTR4 Timer Control Register 4 0x04 16 0x0000 0xFFFF T12RR Timer T12 Run Reset 0 0 write-only value1 T12R is not influenced. 0b0 value2 T12R is cleared, T12 stops counting. 0b1 T12RS Timer T12 Run Set 1 1 write-only value1 T12R is not influenced. 0b0 value2 T12R is set, T12 counts. 0b1 T12RES Timer T12 Reset 2 2 write-only value1 No effect on T12. 0b0 value2 The T12 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T12RES has no impact on bit T12R. 0b1 DTRES Dead-Time Counter Reset 3 3 write-only value1 No effect on the dead-time counters. 0b0 value2 The three dead-time counter channels are reset to zero. 0b1 T12CNT Timer T12 Count Event 5 5 write-only value1 No action 0b0 value2 If enabled (PISEL2), timer T12 counts one step. 0b1 T12STR Timer T12 Shadow Transfer Request 6 6 write-only value1 No action 0b0 value2 STE12 is set, enabling the shadow transfer. 0b1 T12STD Timer T12 Shadow Transfer Disable 7 7 write-only value1 No action 0b0 value2 STE12 is reset without triggering the shadow transfer. 0b1 T13RR Timer T13 Run Reset 8 8 write-only value1 T13R is not influenced. 0b0 value2 T13R is cleared, T13 stops counting. 0b1 T13RS Timer T13 Run Set 9 9 write-only value1 T13R is not influenced. 0b0 value2 T13R is set, T13 counts. 0b1 T13RES Timer T13 Reset 10 10 write-only value1 No effect on T13. 0b0 value2 The T13 counter register is reset to zero. The switching of the output signals is according to the switching rules. Setting of T13RES has no impact on bit T13R. 0b1 T13CNT Timer T13 Count Event 13 13 write-only value1 No action 0b0 value2 If enabled (PISEL2), timer T13 counts one step. 0b1 T13STR Timer T13 Shadow Transfer Request 14 14 write-only value1 No action 0b0 value2 STE13 is set, enabling the shadow transfer. 0b1 T13STD Timer T13 Shadow Transfer Disable 15 15 write-only value1 No action 0b0 value2 STE13 is reset without triggering the shadow transfer. 0b1 MODCTR Modulation Control Register 0x5C 16 0x0000 0xFFFF T12MODEN T12 Modulation Enable 0 5 read-write value1 The modulation of the corresponding output signal by a T12 PWM pattern is disabled. 0b0 value2 The modulation of the corresponding output signal by a T12 PWM pattern is enabled. 0b1 MCMEN Multi-Channel Mode Enable 7 7 read-write value1 The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is disabled. 0b0 value2 The modulation of the corresponding output signal by a multi-channel pattern according to bit field MCMOUT is enabled. 0b1 T13MODEN T13 Modulation Enable 8 13 read-write value1 The modulation of the corresponding output signal by a T13 PWM pattern is disabled. 0b0 value2 The modulation of the corresponding output signal by a T13 PWM pattern is enabled. 0b1 ECT13O Enable Compare Timer T13 Output 15 15 read-write value1 The alternate output function COUT63 is disabled. 0b0 value2 The alternate output function COUT63 is enabled for the PWM signal generated by T13. 0b1 TRPCTR Trap Control Register 0x60 16 0x0000 0xFFFF TRPM0 Trap Mode Control Bits 1, 0 0 0 read-write TRPM1 Trap Mode Control Bits 1, 0 1 1 read-write TRPM2 Trap Mode Control Bit 2 2 2 read-write value1 The trap state can be left (return to normal operation = bit TRPS = 0) as soon as the input CTRAP becomes inactive. Bit TRPF is automatically cleared by hardware if the input pin CTRAP becomes 1. Bit TRPS is automatically cleared by hardware if bit TRPF is 0 and if the synchronization condition (according to TRPM0,1) is detected. 0b0 value2 The trap state can be left (return to normal operation = bit TRPS = 0) as soon as bit TRPF is reset by software after the input CTRAP becomes inactive (TRPF is not cleared by hardware). Bit TRPS is automatically cleared by hardware if bit TRPF = 0 and if the synchronization condition (according to TRPM0,1) is detected. 0b1 TRPEN Trap Enable Control 8 13 read-write value1 The trap functionality of the corresponding output signal is disabled. The output state is independent from bit TRPS. 0b0 value2 The trap functionality of the corresponding output signal is enabled. The output is set to the passive state while TRPS = 1. 0b1 TRPEN13 Trap Enable Control for Timer T13 14 14 read-write value1 The trap functionality for T13 is disabled. Timer T13 (if selected and enabled) provides PWM functionality even while TRPS = 1. 0b0 value2 The trap functionality for T13 is enabled. The timer T13 PWM output signal is set to the passive state while TRPS = 1. 0b1 TRPPEN Trap Pin Enable 15 15 read-write value1 The trap functionality based on the input pin CTRAP is disabled. A trap can only be generated by software by setting bit TRPF. 0b0 value2 The trap functionality based on the input pin CTRAP is enabled. A trap can be generated by software by setting bit TRPF or by CTRAP = 0. 0b1 PSLR Passive State Level Register 0x50 16 0x00 0xFF PSL Compare Outputs Passive State Level 0 5 read-write value1 The passive level is 0. 0b0 value2 The passive level is 1. 0b1 PSL63 Passive State Level of Output COUT63 7 7 read-write value1 The passive level is 0. 0b0 value2 The passive level is 1. 0b1 MCMOUTS Multi-Channel Mode Output Shadow Register 0x08 16 0x0000 0xFFFF MCMPS Multi-Channel PWM Pattern Shadow 0 5 read-write STRMCM Shadow Transfer Request for MCMPS 7 7 write-only value1 Bit field MCMP is updated according to the defined hardware action. The write access to bit field MCMPS does not modify bit field MCMP. 0b0 value2 Bit field MCMP is updated by the value written to bit field MCMPS. 0b1 EXPHS Expected Hall Pattern Shadow 8 10 read-write CURHS Current Hall Pattern Shadow 11 13 read-write STRHP Shadow Transfer Request for the Hall Pattern 15 15 write-only value1 The bit fields CURH and EXPH are updated according to the defined hardware action. The write access to bit fields CURHS and EXPHS does not modify the bit fields CURH and EXPH. 0b0 value2 The bit fields CURH and EXPH are updated by the value written to the bit fields CURHS and EXPHS. 0b1 MCMOUT Multi-Channel Mode Output Register 0x64 16 0x0000 0xFFFF MCMP Multi-Channel PWM Pattern 0 5 read-only value1 The output is set to the passive state. The PWM generated by T12 or T13 is not taken into account. 0b0 value2 The output can deliver the PWM generated by T12 or T13 (according to register MODCTR). 0b1 R Reminder Flag 6 6 read-only value1 Currently, no shadow transfer from MCMPS to MCMP is requested. 0b0 value2 A shadow transfer from MCMPS to MCMP has been requested by the selected trigger source, but it has not yet been executed, because the selected synchronization condition has not yet occurred. 0b1 EXPH Expected Hall Pattern 8 10 read-only CURH Current Hall Pattern 11 13 read-only MCMCTR Multi-Channel Mode Control Register 0x54 16 0x0000 0xFFFF SWSEL Switching Selection 0 2 read-write value1 no trigger request will be generated 0b000 value2 correct hall pattern on CCPOSx detected 0b001 value3 T13 period-match detected (while counting up) 0b010 value4 T12 one-match (while counting down) 0b011 value5 T12 channel 1 compare-match detected (phase delay function) 0b100 value6 T12 period match detected (while counting up) else reserved, no trigger request will be generated 0b101 SWSYN Switching Synchronization 4 5 read-write value1 direct; the trigger event directly causes the shadow transfer 0b00 value2 T13 zero-match triggers the shadow transfer 0b01 value3 a T12 zero-match (while counting up) triggers the shadow transfer 0b10 value4 reserved; no action 0b11 STE12U Shadow Transfer Enable for T12 Upcounting 8 8 read-write value1 No action 0b0 value2 The T12_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 STE12D Shadow Transfer Enable for T12 Downcounting 9 9 read-write value1 No action 0b0 value2 The T12_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 STE13U Shadow Transfer Enable for T13 Upcounting 10 10 read-write value1 No action 0b0 value2 The T13_ST shadow transfer mechanism is enabled if MCMEN = 1. 0b1 IS Capture/Compare Interrupt Status Register 0x68 16 0x0000 0xFFFF ICC60R Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2) 0 0 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 ICC61R Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2) 2 2 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 ICC62R Capture, Compare-Match Rising Edge Flag (x = 0, 1, 2) 4 4 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 ICC60F Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2) 1 1 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 ICC61F Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2) 3 3 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 ICC62F Capture, Compare-Match Falling Edge Flag (x = 0, 1, 2) 5 5 read-only value1 The event has not yet occurred since this bit has been reset for the last time. 0b0 value2 The event described above has been detected. 0b1 T12OM Timer T12 One-Match Flag 6 6 read-only value1 A timer T12 one-match (while counting down) has not yet been detected since this bit has been reset for the last time. 0b0 value2 A timer T12 one-match (while counting down) has been detected. 0b1 T12PM Timer T12 Period-Match Flag 7 7 read-only value1 A timer T12 period-match (while counting up) has not yet been detected since this bit has been reset for the last time. 0b0 value2 A timer T12 period-match (while counting up) has been detected. 0b1 T13CM Timer T13 Compare-Match Flag 8 8 read-only value1 A timer T13 compare-match has not yet been detected since this bit has been reset for the last time. 0b0 value2 A timer T13 compare-match has been detected. 0b1 T13PM Timer T13 Period-Match Flag 9 9 read-only value1 A timer T13 period-match has not yet been detected since this bit has been reset for the last time. 0b0 value2 A timer T13 period-match has been detected. 0b1 TRPF Trap Flag 10 10 read-only value1 The trap condition has not been detected. 0b0 value2 The trap condition has been detected (input CTRAP has been 0 or by software). 0b1 TRPS Trap State 11 11 read-only value1 The trap state is not active. 0b0 value2 The trap state is active. Bit TRPS is set while bit TRPF = 1. It is reset according to the mode selected in register TRPCTR. 0b1 CHE Correct Hall Event 12 12 read-only value1 A transition to a correct (= expected) hall event has not yet been detected since this bit has been reset for the last time. 0b0 value2 A transition to a correct (= expected) hall event has been detected. 0b1 WHE Wrong Hall Event 13 13 read-only value1 A transition to a wrong hall event (not the expected one) has not yet been detected since this bit has been reset for the last time. 0b0 value2 A transition to a wrong hall event (not the expected one) has been detected. 0b1 IDLE IDLE State 14 14 read-only value1 No action. 0b0 value2 Bit field MCMP is cleared and held to 0, the selected outputs are set to passive state. 0b1 STR Multi-Channel Mode Shadow Transfer Request 15 15 read-only value1 The shadow transfer has not yet taken place. 0b0 value2 The shadow transfer has taken place. 0b1 ISS Capture/Compare Interrupt Status Set Register 0x4C 16 0x0000 0xFFFF SCC60R Set Capture, Compare-Match Rising Edge Flag 0 0 write-only value1 No action 0b0 value2 Bit CC60R in register IS will be set. 0b1 SCC60F Set Capture, Compare-Match Falling Edge Flag 1 1 write-only value1 No action 0b0 value2 Bit CC60F in register IS will be set. 0b1 SCC61R Set Capture, Compare-Match Rising Edge Flag 2 2 write-only value1 No action 0b0 value2 Bit CC61R in register IS will be set. 0b1 SCC61F Set Capture, Compare-Match Falling Edge Flag 3 3 write-only value1 No action 0b0 value2 Bit CC61F in register IS will be set. 0b1 SCC62R Set Capture, Compare-Match Rising Edge Flag 4 4 write-only value1 No action 0b0 value2 Bit CC62R in register IS will be set. 0b1 SCC62F Set Capture, Compare-Match Falling Edge Flag 5 5 write-only value1 No action 0b0 value2 Bit CC62F in register IS will be set. 0b1 ST12OM Set Timer T12 One-Match Flag 6 6 write-only value1 No action 0b0 value2 Bit T12OM in register IS will be set. 0b1 ST12PM Set Timer T12 Period-Match Flag 7 7 write-only value1 No action 0b0 value2 Bit T12PM in register IS will be set. 0b1 ST13CM Set Timer T13 Compare-Match Flag 8 8 write-only value1 No action 0b0 value2 Bit T13CM in register IS will be set. 0b1 ST13PM Set Timer T13 Period-Match Flag 9 9 write-only value1 No action 0b0 value2 Bit T13PM in register IS will be set. 0b1 STRPF Set Trap Flag 10 10 write-only value1 No action 0b0 value2 Bits TRPF and TRPS in register IS will be set. 0b1 SWHC Software Hall Compare 11 11 write-only value1 No action 0b0 value2 The Hall compare action is triggered. 0b1 SCHE Set Correct Hall Event Flag 12 12 write-only value1 No action 0b0 value2 Bit CHE in register IS will be set. 0b1 SWHE Set Wrong Hall Event Flag 13 13 write-only value1 No action 0b0 value2 Bit WHE in register IS will be set. 0b1 SIDLE Set IDLE Flag 14 14 write-only value1 No action 0b0 value2 Bit IDLE in register IS will be set. 0b1 SSTR Set STR Flag 15 15 write-only value1 No action 0b0 value2 Bit STR in register IS will be set. 0b1 ISR Capture/Compare Interrupt Status Reset Register 0x0C 16 0x0000 0xFFFF RCC60R Reset Capture, Compare-Match Rising Edge Flag 0 0 write-only value1 No action 0b0 value2 Bit CC60R in register IS will be reset. 0b1 RCC60F Reset Capture, Compare-Match Falling Edge Flag 1 1 write-only value1 No action 0b0 value2 Bit CC60F in register IS will be reset. 0b1 RCC61R Reset Capture, Compare-Match Rising Edge Flag 2 2 write-only value1 No action 0b0 value2 Bit CC61R in register IS will be reset. 0b1 RCC61F Reset Capture, Compare-Match Falling Edge Flag 3 3 write-only value1 No action 0b0 value2 Bit CC61F in register IS will be reset. 0b1 RCC62R Reset Capture, Compare-Match Rising Edge Flag 4 4 write-only value1 No action 0b0 value2 Bit CC62R in register IS will be reset. 0b1 RCC62F Reset Capture, Compare-Match Falling Edge Flag 5 5 write-only value1 No action 0b0 value2 Bit CC62F in register IS will be reset. 0b1 RT12OM Reset Timer T12 One-Match Flag 6 6 write-only value1 No action 0b0 value2 Bit T12OM in register IS will be reset. 0b1 RT12PM Reset Timer T12 Period-Match Flag 7 7 write-only value1 No action 0b0 value2 Bit T12PM in register IS will be reset. 0b1 RT13CM Reset Timer T13 Compare-Match Flag 8 8 write-only value1 No action 0b0 value2 Bit T13CM in register IS will be reset. 0b1 RT13PM Reset Timer T13 Period-Match Flag 9 9 write-only value1 No action 0b0 value2 Bit T13PM in register IS will be reset. 0b1 RTRPF Reset Trap Flag 10 10 write-only value1 No action 0b0 value2 Bit TRPF in register IS will be reset (not taken into account while input CTRAP = 0 and TRPPEN = 1. 0b1 RCHE Reset Correct Hall Event Flag 12 12 write-only value1 No action 0b0 value2 Bit CHE in register IS will be reset. 0b1 RWHE Reset Wrong Hall Event Flag 13 13 write-only value1 No action 0b0 value2 Bit WHE in register IS will be reset. 0b1 RIDLE Reset IDLE Flag 14 14 write-only value1 No action 0b0 value2 Bit IDLE in register IS will be reset. 0b1 RSTR Reset STR Flag 15 15 write-only value1 No action 0b0 value2 Bit STR in register IS will be reset. 0b1 IEN Capture/Compare Interrupt Enable Register 0x44 16 0x0000 0xFFFF ENCC60R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 0 0 0 read-write value1 No interrupt will be generated if the set condition for bit CC60R in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC60R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. 0b1 ENCC60F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 0 1 1 read-write value1 No interrupt will be generated if the set condition for bit CC60F in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC60F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC60. 0b1 ENCC61R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 1 2 2 read-write value1 No interrupt will be generated if the set condition for bit CC61R in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC61R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. 0b1 ENCC61F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 1 3 3 read-write value1 No interrupt will be generated if the set condition for bit CC61F in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC61F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC61. 0b1 ENCC62R Capture, Compare-Match Rising Edge Interrupt Enable for Channel 2 4 4 read-write value1 No interrupt will be generated if the set condition for bit CC62R in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC62R in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. 0b1 ENCC62F Capture, Compare-Match Falling Edge Interrupt Enable for Channel 2 5 5 read-write value1 No interrupt will be generated if the set condition for bit CC62F in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CC62F in register IS occurs. The interrupt line that will be activated is selected by bit field INPCC62. 0b1 ENT12OM Enable Interrupt for T12 One-Match 6 6 read-write value1 No interrupt will be generated if the set condition for bit T12OM in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit T12OM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. 0b1 ENT12PM Enable Interrupt for T12 Period-Match 7 7 read-write value1 No interrupt will be generated if the set condition for bit T12PM in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit T12PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT12. 0b1 ENT13CM Enable Interrupt for T13 Compare-Match 8 8 read-write value1 No interrupt will be generated if the set condition for bit T13CM in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit T13CM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. 0b1 ENT13PM Enable Interrupt for T13 Period-Match 9 9 read-write value1 No interrupt will be generated if the set condition for bit T13PM in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit T13PM in register IS occurs. The interrupt line that will be activated is selected by bit field INPT13. 0b1 ENTRPF Enable Interrupt for Trap Flag 10 10 read-write value1 No interrupt will be generated if the set condition for bit TRPF in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit TRPF in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. 0b1 ENCHE Enable Interrupt for Correct Hall Event 12 12 read-write value1 No interrupt will be generated if the set condition for bit CHE in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit CHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. 0b1 ENWHE Enable Interrupt for Wrong Hall Event 13 13 read-write value1 No interrupt will be generated if the set condition for bit WHE in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit WHE in register IS occurs. The interrupt line that will be activated is selected by bit field INPERR. 0b1 ENIDLE Enable Idle 14 14 read-write value1 The bit IDLE is not automatically set when a wrong hall event is detected. 0b0 value2 The bit IDLE is automatically set when a wrong hall event is detected. 0b1 ENSTR Enable Multi-Channel Mode Shadow Transfer Interrupt 15 15 read-write value1 No interrupt will be generated if the set condition for bit STR in register IS occurs. 0b0 value2 An interrupt will be generated if the set condition for bit STR in register IS occurs. The interrupt line that will be activated is selected by bit field INPCHE. 0b1 INP Capture/Compare Interrupt Node Pointer Register 0x48 16 0x3940 0xFFFF INPCC60 Interrupt Node Pointer for Channel 0 Interrupts 0 1 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPCC61 Interrupt Node Pointer for Channel 1 Interrupts 2 3 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPCC62 Interrupt Node Pointer for Channel 2 Interrupts 4 5 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPCHE Interrupt Node Pointer for the CHE Interrupt 6 7 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPERR Interrupt Node Pointer for Error Interrupts 8 9 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPT12 Interrupt Node Pointer for Timer T12 Interrupts 10 11 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 INPT13 Interrupt Node Pointer for Timer T13 Interrupts 12 13 read-write value1 Interrupt output line SR0 is selected. 0b00 value2 Interrupt output line SR1 is selected. 0b01 value3 Interrupt output line SR2 is selected. 0b10 value4 Interrupt output line SR3 is selected. 0b11 UART1 UART1 0x48020000 0x0 0x2000 registers SCON Serial Channel Control Register 0x00 8 0x00 0xFF RI Receive Interrupt Flag 0 0 read-write TI Transmit Interrupt Flag 1 1 read-write RB8 Serial Port Receiver Bit 9 2 2 read-write TB8 Serial Port Transmitter Bit 9 3 3 read-write REN Enable Receiver of Serial Port 4 4 read-write value1 Serial reception is disabled. 0b0 value2 Serial reception is enabled. 0b1 SM2 Enable Serial Port Multiprocessor Communication in Modes 2 and 3 5 5 read-write SM1_SM0 Serial Port Operating Mode Selection 6 7 read-write value1 Mode 0: 8-bit shift register, fixed baud rate (fPCLK/2). 0b00 value2 Mode 1: 8-bit UART, variable baud rate. 0b01 value3 Mode 2: 9-bit UART, fixed baud rate (fPCLK/64 or fPCLK/32). 0b10 value4 Mode 3: 9-bit UART, variable baud rate. 0b11 SBUF Serial Data Buffer 0x04 8 0x00 0xFF VAL Serial Interface Buffer Register 0 7 read-write SCONCLR Serial Channel Control Clear Register 0x08 8 0x00 0xFF RICLR Receive Interrupt Clear Flag 0 0 write-only TICLR Transmit Interrupt Clear Flag 1 1 write-only UART2 UART2 0x48022000 0x0 0x2000 registers SCON Serial Channel Control Register 0x00 8 0x00 0xFF RI Receive Interrupt Flag 0 0 read-write TI Transmit Interrupt Flag 1 1 read-write RB8 Serial Port Receiver Bit 9 2 2 read-write TB8 Serial Port Transmitter Bit 9 3 3 read-write REN Enable Receiver of Serial Port 4 4 read-write value1 Serial reception is disabled. 0b0 value2 Serial reception is enabled. 0b1 SM2 Enable Serial Port Multiprocessor Communication in Modes 2 and 3 5 5 read-write SM1_SM0 Serial Port Operating Mode Selection 6 7 read-write value1 Mode 0: 8-bit shift register, fixed baud rate (fPCLK/2). 0b00 value2 Mode 1: 8-bit UART, variable baud rate. 0b01 value3 Mode 2: 9-bit UART, fixed baud rate (fPCLK/64 or fPCLK/32). 0b10 value4 Mode 3: 9-bit UART, variable baud rate. 0b11 SBUF Serial Data Buffer 0x04 8 0x00 0xFF VAL Serial Interface Buffer Register 0 7 read-write SCONCLR Serial Channel Control Clear Register 0x08 8 0x00 0xFF RICLR Receive Interrupt Clear Flag 0 0 write-only TICLR Transmit Interrupt Clear Flag 1 1 write-only SSC1 SSC1 0x48024000 0x0 0x2000 registers PISEL Port Input Select Register, RESET_TYPE_3 0x00 16 0x00 0xFF MIS_0 Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=Receiver input (Port A: P1.2) is selected (SSC2)., 0b1=Receiver input (Port B: P2.5) is selected (SSC2)., 0 0 read-write SIS Slave Mode Receiver Input Select: 0b0=Receiver input (Port A: P0.2) is selected (SSC1)., 0b1=Receiver input (Port B: P0.2) is selected (SSC1)., 0b0=Receiver input (Port A: P1.1) is selected (SSC2)., 0b1=Receiver input (Port B: P1.1) is selected (SSC2)., 1 1 read-write CIS Slave Mode Clock Input Select: 0b0=Clock input (Port A: P0.3) is selected (SSC1)., 0b1=Clock input (Port B: P0.3) is selected (SSC1)., 0b0=Clock input (Port A: P1.0) is selected (SSC2)., 0b1=Clock input (Port B: P1.0) is selected (SSC2)., 2 2 read-write MIS_1 Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=n/a (SSC2)., 0b1=n/a (SSC2)., 3 3 read-write CON Control Register Yes 0x04 16 0x0000 0xFFFF BC Bit Count Field 0 3 read-only TE Transmit Error Flag 8 8 read-only value1 No error. 0b0 value2 Transfer starts with the slave's transmit buffer not being updated. 0b1 RE Receive Error Flag 9 9 read-only value1 No error. 0b0 value2 Reception completed before the receive buffer was read. 0b1 PE Phase Error Flag 10 10 read-only value1 No error. 0b0 value2 Received data changes around sampling clock edge. 0b1 BE Baud Rate Error Flag 11 11 read-only value1 No error. 0b0 value2 More than factor 2 or 0.5 between slave's actual and expected baud rate. 0b1 BSY Busy Flag 12 12 read-only MS Master Select Bit 14 14 read-write value1 Slave Mode. Operate on shift clock received via SCLK. 0b0 value2 Master Mode. Generate shift clock and output it via SCLK. 0b1 EN Enable Bit = 1 15 15 read-write ISRCLR Interrupt Status Register Clear 0x14 16 0x0000 0xFFFF TECLR Transmit Error Flag Clear 8 8 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 RECLR Receive Error Flag Clear 9 9 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 PECLR Phase Error Flag Clear 10 10 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 BECLR Baud Rate Error Flag Clear 11 11 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 BR Baud Rate Timer Reload Register 0x10 16 0x0000 0xFFFF BR_VALUE Baud Rate Timer/Reload Register Value 0 15 read-write TB Transmitter Buffer Register 0x08 16 0x0000 0xFFFF TB_VALUE Transmit Data Register Value 0 15 read-write RB Receiver Buffer Register 0x0C 16 0x0000 0xFFFF RB_VALUE Receive Data Register Value 0 15 read-only SSC2 SSC2 0x48026000 0x0 0x2000 registers PISEL Port Input Select Register, RESET_TYPE_3 0x00 16 0x00 0xFF MIS_0 Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=Receiver input (Port A: P1.2) is selected (SSC2)., 0b1=Receiver input (Port B: P2.5) is selected (SSC2)., 0 0 read-write SIS Slave Mode Receiver Input Select: 0b0=Receiver input (Port A: P0.2) is selected (SSC1)., 0b1=Receiver input (Port B: P0.2) is selected (SSC1)., 0b0=Receiver input (Port A: P1.1) is selected (SSC2)., 0b1=Receiver input (Port B: P1.1) is selected (SSC2)., 1 1 read-write CIS Slave Mode Clock Input Select: 0b0=Clock input (Port A: P0.3) is selected (SSC1)., 0b1=Clock input (Port B: P0.3) is selected (SSC1)., 0b0=Clock input (Port A: P1.0) is selected (SSC2)., 0b1=Clock input (Port B: P1.0) is selected (SSC2)., 2 2 read-write MIS_1 Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=n/a (SSC2)., 0b1=n/a (SSC2)., 3 3 read-write CON Control Register Yes 0x04 16 0x0000 0xFFFF BC Bit Count Field 0 3 read-only TE Transmit Error Flag 8 8 read-only value1 No error. 0b0 value2 Transfer starts with the slave's transmit buffer not being updated. 0b1 RE Receive Error Flag 9 9 read-only value1 No error. 0b0 value2 Reception completed before the receive buffer was read. 0b1 PE Phase Error Flag 10 10 read-only value1 No error. 0b0 value2 Received data changes around sampling clock edge. 0b1 BE Baud Rate Error Flag 11 11 read-only value1 No error. 0b0 value2 More than factor 2 or 0.5 between slave's actual and expected baud rate. 0b1 BSY Busy Flag 12 12 read-only MS Master Select Bit 14 14 read-write value1 Slave Mode. Operate on shift clock received via SCLK. 0b0 value2 Master Mode. Generate shift clock and output it via SCLK. 0b1 EN Enable Bit = 1 15 15 read-write ISRCLR Interrupt Status Register Clear 0x14 16 0x0000 0xFFFF TECLR Transmit Error Flag Clear 8 8 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 RECLR Receive Error Flag Clear 9 9 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 PECLR Phase Error Flag Clear 10 10 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 BECLR Baud Rate Error Flag Clear 11 11 write-only value1 No error clear. 0b0 value2 Error clear. 0b1 BR Baud Rate Timer Reload Register 0x10 16 0x0000 0xFFFF BR_VALUE Baud Rate Timer/Reload Register Value 0 15 read-write TB Transmitter Buffer Register 0x08 16 0x0000 0xFFFF TB_VALUE Transmit Data Register Value 0 15 read-write RB Receiver Buffer Register 0x0C 16 0x0000 0xFFFF RB_VALUE Receive Data Register Value 0 15 read-only PMU PMU 0x50004000 0x0 0x1000 registers MON_CNF Settings Monitor 1 0x034 8 #01000111 #11111111 STS MON Status Input 7 7 read-only value1 MON input has low status 0b0 value2 MON input has high status 0b1 PU Pull-Up Current Source for MON Input Enable 5 5 read-write value1 Pull-up source disabled 0b0 value2 Pull-up source enabled 0b1 PD Pull-Down Current Source for MON Input Enable 4 4 read-write value1 Pull-down source disabled 0b0 value2 Pull-down source enabled 0b1 CYC MON for Cycle Sense Enable 3 3 read-write value1 Cycle Sense disabled 0b0 value2 Cycle Sense enabled 0b1 RISE MON Wake-up on Rising Edge Enable 2 2 read-write value1 Wake-up disabled 0b0 value2 Wake-up enabled 0b1 FALL MON Wake-up on Falling Edge Enable 1 1 read-write value1 Wake-up disabled 0b0 value2 Wake-up enabled 0b1 EN MON Enable 0 0 read-write value1 MON disabled 0b0 value2 MON enabled 0b1 PMU_SUPPLY_STS Voltage Reg Status Register 0x004 8 #00000000 #11001100 PMU_5V_FAIL_EN Enabling of VDDP status information as interrupt source 6 6 read-write value1 No interrupts are generated 0b0 value2 Interrupts are generated 0b1 PMU_5V_OVERLOAD Overload at VDDP regulator 5 5 read-only value1 No overload 0b0 value2 Overload 0b1 PMU_5V_OVERVOLT Overvoltage at VDDP regulator 4 4 read-only value1 No overvoltage 0b0 value2 Overvoltage 0b1 PMU_1V5_FAIL_EN Enabling of VDDC status information as interrupt source 2 2 read-write value1 No interrupts are generated 0b0 value2 Interrupts are generated 0b1 PMU_1V5_OVERLOAD Overload at VDDC regulator 1 1 read-only value1 No overload 0b0 value2 Overload 0b1 PMU_1V5_OVERVOLT Overvoltage at VDDC regulator 0 0 read-only value1 No overvoltage 0b0 value2 Overvoltage 0b1 VDDEXT_CTRL VDDEXT Control 0x08 8 #00000000 #00001111 STABLE VDDEXT Supply works inside its specified range 1 7 7 read-only value1 VDDEXT Voltage inside of specified range 0b1 value2 VDDEXT Voltage outside of specified range 0b0 OK VDDEXT Supply works inside its specified range 2 6 6 read-only value1 VDDEXT in low drop mode 0b1 value2 VDDEXT not in low drop mode 0b0 OVERLOAD VDDEXT Supply Overload 5 5 read-write value1 VDDEXT not in overload condition 0b0 value2 VDDEXT in overload condition 0b1 OVERVOLT VDDEXT Supply Overvoltage 4 4 read-write value1 VDDEXT not in overvoltage condition 0b0 value2 VDDEXT in overvoltage condition 0b1 SHORT VDDEXT Supply Shorted Output 3 3 read-write value1 VDDEXT no short circuit 0b0 value2 VDDEXT short circuit 0b1 FAIL_EN Enabling of VDDEXT Supply status information as interrupt source 2 2 read-write value1 VDDEXT fail interrupts are disabled 0b0 value2 VDDEXT fail Interrupts are enabled 0b1 CYC_EN VDDEXT Supply for Cyclic Sense Enable 1 1 read-write value1 VDDEXT for cyclic sense disable 0b0 value2 VDDEXT for cyclic sense enable 0b1 ENABLE VDDEXT Supply Enable 0 0 read-write value1 VDDEXT Supply disabled 0b0 value2 VDDEXT supply enabled 0b1 SYS_FAIL_STS System Fail Status Register 0x070 8 0x00000000 0xFFFFFFFF WDT1_SEQ_FAIL External Watchdog (WDT1) Sequential Fail 6 6 read-write No Fail System working properly 0b0 Sequential Watchdog Fail 5 consecutive watchdog fails 0b1 SYS_OT System Overtemperature Indication Flag 5 5 read-write No Overtemperature System ok 0b0 Overtemperature System Overtemperature 0b1 PMU_5V_OVL VDDP Overload Flag 3 3 read-write No Overload VDDP ok 0b0 Overload VDDP Overload 0b1 PMU_1V5_OVL VDDC Overload Flag 2 2 read-write No Overload VDDC ok 0b0 Overload Hall VDDC Overload 0b1 SUPP_TMOUT Supply Time Out 1 1 read-write Main Supply ok VDDP or VDDC are in expected range 0b0 Main Supply fail VDDP or VDDC do not have stable operating point 0b1 SUPP_SHORT Supply Short 0 0 read-write Main Supply ok VDDP or VDDC are in expected range 0b0 Main Supply short VDDP or VDDC do not have stable operating point 0b1 WAKE_STS_FAIL Wake Status Fail Register 0x080 8 #00000000 #11111111 VDDEXTSHORT Stop-Exit due to short circuit at the VDDEXT Supply 2 2 read-write value1 No short circuit 0b0 value2 Short circuit 0b1 SUPPFAIL Stop-Exit due to overvoltage at the VDDEXT Supply 0 0 read-write value1 No overvoltage 0b0 value2 Module suspend enabled 0b1 WAKE_CONF_GPIO0_RISE Wake Configuration GPIO Port 0 Rising Edge Register 0xD8 8 #00000000 #11111111 GPIO0_RI_4 Port 0_4 Wake-up on Rising Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_RI_3 Port 0_3 Wake-up on Rising Edge enable 3 3 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_RI_2 Port 0_2 Wake-up on Rising Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_RI_1 Port 0_1 Wake-up on Rising Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_RI_0 Port 0_0 Wake-up on Rising Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_CONF_GPIO0_FALL Wake Configuration GPIO Port 0 Falling Edge Register 0xDC 8 #00000000 #11111111 GPIO0_FA_4 Port 0_4 Wake-up on Falling Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_FA_3 Port 0_3 Wake-up on Falling Edge enable 3 3 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_FA_2 Port 0_2 Wake-up on Falling Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_FA_1 Port 0_1 Wake-up on Falling Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO0_FA_0 Port 0_0 Wake-up on Falling Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_CONF_GPIO0_CYC Wake Port 0 Cycle Enabled Register 0xE0 8 #00000000 #11111111 GPIO0_CYC_4 GPIO0_4 input for cycle sense enable 4 4 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO0_CYC_3 GPIO0_3 input for cycle sense enable 3 3 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO0_CYC_2 GPIO0_2 input for cycle sense enable 2 2 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO0_CYC_1 GPIO0_1 input for cycle sense enable 1 1 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO0_CYC_0 GPIO0_0 input for cycle sense enable 0 0 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 WAKE_CONF_GPIO1_RISE Wake Configuration GPIO Port 1 Rising Edge Register 0xE4 8 #00000000 #11111111 GPIO1_RI_4 Port 1_4 Wake-up on Rising Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_RI_3 Port 1_3 Wake-up on Rising Edge enable 3 3 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_RI_2 Port 1_2 Wake-up on Rising Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_RI_1 Port 1_1 Wake-up on Rising Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_RI_0 Port 1_0 Wake-up on Rising Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_CONF_GPIO1_FALL Wake Configuration GPIO Port 1 Falling Edge Register 0xE8 8 #00000000 #11111111 GPIO1_FA_4 Port 1_4 Wake-up on Falling Edge enable 4 4 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_FA_3 Port 1_3 Wake-up on Falling Edge enable 3 3 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_FA_2 Port 1_2 Wake-up on Falling Edge enable 2 2 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_FA_1 Port 1_1 Wake-up on Falling Edge enable 1 1 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 GPIO1_FA_0 Port 1_0 Wake-up on Falling Edge enable 0 0 read-write ENABLE wake-up enabled 0b1 DISABLE wake-up disabled 0b0 WAKE_CONF_GPIO1_CYC Wake Port 1 Cycle Enabled Register 0xEC 8 #00000000 #11111111 GPIO1_CYC_4 GPIO1_4 input for cycle sense enable 4 4 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO1_CYC_3 GPIO1_3 input for cycle sense enable 3 3 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO1_CYC_2 GPIO1_2 input for cycle sense enable 2 2 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO1_CYC_1 GPIO1_1 input for cycle sense enable 1 1 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 GPIO1_CYC_0 GPIO1_0 input for cycle sense enable 0 0 read-write ENABLE input for cycle sense enabled 0b1 DISABLE input for cycle sense disabled 0b0 CNF_WAKE_FILTER PMU Wake-up Timing Register 0x0AC 8 #00000000 #11111111 CNF_GPIO_FT Wake-up Filter time for General Purpose IO 2 3 read-write 10_us 10 us filter time 0b00 20_us 20 us filter time 0b01 40_us 40 us filter time 0b10 5_us 5 us filter time 0b11 CNF_MON_FT Wake-up Filter time for Monitoring Inputs 1 1 read-write 20_us 20 us filter time 0b0 40_us 40 us filter time 0b1 CNF_LIN_FT Wake-up Filter time for LIN WAKE 0 0 read-write 30_us 30 us filter time 0b0 50_us 50 us filter time 0b1 LIN_WAKE_EN LIN Wake Enable 0x050 8 #00000000 #11111111 LIN_EN Lin Wake enable 7 7 read-write Disable . 0b0 Enable . 0b1 WAKE_STATUS Main wake status register 0x000 8 #00000000 #11000000 FAIL Wake-up after VDDEXT Fail 5 5 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 CYC_WAKE Wake-up caused by Cyclic Wake 4 4 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 GPIO1 Wake-up via GPIO1 which is a logical OR combination of all Wake_STS_GPIO1 bits 3 3 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 GPIO0 Wake-up via GPIO0 which is a logical OR combination of all Wake_STS_GPIO0 bits 2 2 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 MON_WAKE Wake-up via MON 1 1 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 LIN_WAKE Wake-up via LIN- Message 0 0 read-only value1 No Wake-up occurred 0b0 value2 Wake-up occurred 0b1 WAKE_STS_MON Wake Source MON Input Register 0x084 8 #00000000 #11111111 WAKE_STS Status of MON 0 0 read-only No wake-up detected . 0b0 wake-up detected . 0b1 WAKE_STS_GPIO0 Wake Status GPIO 0 Register 0x088 8 #00000000 #11111111 GPIO0_STS_4 Status of GPIO0_4 4 4 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO0_STS_3 Status of GPIO0_3 3 3 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO0_STS_2 Status of GPIO0_2 2 2 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO0_STS_1 Status of GPIO0_1 1 1 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO0_STS_0 Status of GPIO0_0 0 0 read-only No wake-up detected . 0b0 wake-up detected . 0b1 WAKE_STS_GPIO1 Wake Status GPIO 1 Register 0x08C 8 #00000000 #11111111 GPIO1_STS_4 Wake GPIO1_4 4 4 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO1_STS_3 Wake GPIO1_3 3 3 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO1_STS_2 Wake GPIO1_2 2 2 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO1_STS_1 Wake GPIO1_1 1 1 read-only No wake-up detected . 0b0 wake-up detected . 0b1 GPIO1_STS_0 Wake GPIO1_0 0 0 read-only No wake-up detected . 0b0 wake-up detected . 0b1 CNF_PMU_SETTINGS PMU Settings Register 0x020 8 #00000100 #11111111 EN_VDDEXT_OC_OFF_N Disabling VDDEXT Shutdown in Overload Condition 7 7 read-write value1 Shutdown enabled 0b0 value2 Shutdown disabled 0b1 CYC_SENSE_EN Enabling Cyclic Sense 3 3 read-write value1 Cyclic Sense disabled 0b0 value2 Cyclic Sense enabled 0b1 CYC_WAKE_EN Enabling Cyclic Wake 2 2 read-write value1 Cyclic Wake disabled 0b0 value2 Cyclic Wake enabled 0b1 EN_0V9_N Disables the reduction of the VDDC regulator output to 0.9 V during Stop-Mode 1 1 read-write value1 Output voltage reduction enabled 0b0 value2 Output voltage reduction disabled 0b1 WAKE_W_RST Wake-up with reset execution 0 0 read-write value1 Stop-Exit without reset execution 0b0 value2 Stop-Exit with reset execution 0b1 CNF_CYC_SENSE Dead Time in Cyclic Sense Register 0x028 8 #00000000 #11111111 OSC_100kHz_EN 100 kHz Oscillator Enable 7 7 read-write DISABLE Oscillator is disabled 0b0 ENABLE Oscillator is enabled 0b1 E01 Exponent 4 5 read-write value1 Exponent value is 0 0b00 value2 Exponent value is 1 0b01 value3 Exponent value is 2 0b10 value4 Exponent value is 3 0b11 M03 Mantissa 0 3 read-write value1 Mantissa value is 1 0b0000 value2 Mantissa value is 16 0b1111 CNF_CYC_WAKE Dead Time in Cyclic Wake Register 0x02C 8 #00110111 #11111111 E01 Exponent 4 5 read-write value1 Exponent value is 0 0b00 value2 Exponent value is 1 0b01 value3 Exponent value is 2 0b10 value4 Exponent value is 3 0b11 M03 Mantissa 0 3 read-write value1 Mantissa value is 1 0b0000 value2 Mntissa value is 16 0b1111 CNF_CYC_SAMPLE_DEL Sample Delay in Cyclic Sense Register 0x030 8 #00000000 #11111111 M03 Mantissa 0 3 read-write value1 variable value M3M2M1M0 is 0 0b0000 value2 variable value M3M3M1M0 is 15 0b1111 CNF_RST_TFB Reset Blind Time Register 0x06C 8 0x00000003 0xFFFFFFFF RST_TFB Reset Pin Blind Time Selection Bits 0 1 read-write RST_TFB_0 0,5 us typ. 0b00 RST_TFB_1 1 us typ. 0b01 RST_TFB_2 5 us typ. 0b10 RST_TFB_3 31 us typ. 0b11 PMU_RESET_STS1 Reset Status Hard Register 0x010 8 0x00000000 0xFFFFFFFF PMU_1V5DidPOR Power-On Reset Flag 7 7 read-write value1 No Power-On reset executed 0b0 value2 Power-On reset executed 0b1 PMU_PIN PIN-Reset Flag 6 6 read-write value1 No PIN-Reset executed 0b0 value2 PIN-Reset executed 0b1 PMU_ExtWDT External Watchdog (WDT1) Reset Flag 5 5 read-write value1 No External Watchdog reset executed 0b0 value2 External Watchdog reset executed 0b1 PMU_ClkWDT Clock Watchdog (CLKWDT) Reset Flag 4 4 read-write value1 No Clock Watchdog reset executed 0b0 value2 Clock Watchdog reset executed 0b1 PMU_LPR Low Priority Resets (see PMU_RESET_STS2) 3 3 read-write value1 Low Priority-Reset executed 0b0 value2 Low Priority executed 0b1 PMU_SleepEX Flag which indicates a reset caused by Sleep-Exit 2 2 read-write value1 No reset caused by Sleep-Exit executed 0b0 value2 Reset caused by Sleep-Exit executed 0b1 PMU_WAKE Flag which indicates a reset caused by Stop-Exit 1 1 read-write value1 No reset caused by Stop-Exit executed 0b0 value2 Reset caused by Stop-Exit executed 0b1 SYS_FAIL Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register 0 0 read-write value1 No reset caused by System Fail executed 0b0 value2 Reset caused by System Fail executed 0b1 PMU_RESET_STS2 Reset Status Soft Register 0x014 8 0x00000000 0xFFFFFFFF LOCKUP Lockup-Reset Flag 2 2 read-write value1 No Lockup-Reset executed 0b0 value2 Lockup-Reset executed 0b1 PMU_SOFT Soft-Reset Flag 1 1 read-write value1 No Soft-Reset executed 0b0 value2 Soft-Reset executed 0b1 PMU_IntWDT Internal Watchdog Reset Flag 0 0 read-write value1 No Internal Watchdog reset executed 0b0 value2 Internal Watchdog reset executed 0b1 GPUDATA00 General Purpose User DATA0 0x0C0 8 0x00000000 0xFFFFFFFF DATA0 DATA0 Storage Byte 0 7 read-write GPUDATA01 General Purpose User DATA1 0x0C4 8 0x00000000 0xFFFFFFFF DATA1 DATA1 Storage Byte 0 7 read-write GPUDATA02 General Purpose User DATA2 0x0C8 8 0x00000000 0xFFFFFFFF DATA2 DATA2 Storage Byte 0 7 read-write GPUDATA03 General Purpose User DATA3 0x0CC 8 0x00000000 0xFFFFFFFF DATA3 DATA3 Storage Byte 0 7 read-write GPUDATA04 General Purpose User DATA4 0x0D0 8 0x00000000 0xFFFFFFFF DATA4 DATA4 Storage Byte 0 7 read-write GPUDATA05 General Purpose User DATA5 0x0D4 8 0x00000000 0xFFFFFFFF DATA5 DATA5 Storage Byte 0 7 read-write SystemStartConfig System Startup Config 0x2D4 8 0x00000000 0xFFFFFFFF MBIST_EN System Startup Configuration Bit for RAM MBIST at Sleep Mode exit 0 0 read-write value1 No MBIST executed at Sleep Mode exit 0b0 value2 MBIST executed at Sleep Mode exit 0b1 SCUPM SCUPM 0x50006000 0x0 0x1000 registers AMCLK_FREQ_STS Analog Module Clock Frequency Status Register 0x00 32 #0000000000000000 #1100000011000000 AMCLK2_FREQ Current frequency of Analog Module Clock 2 (TFILT_CLK) 8 13 read-only AMCLK1_FREQ Current frequency of Analog Module Clock System Clock (MI_CLK) 0 5 read-only AMCLK_CTRL Analog Module Clock Control 0x04 32 0x00000001 0xFFFFFFFF CLKWDT_PD_N Clock Watchdog Powerdown 0 0 read-write DISABLE Clock Watchdog disabled 0b0 ENABLE Clock Watchdog enabaled 0b1 AMCLK_TH_HYS Analog Module Clock Limit Register 0x0C 32 0xD4E194B3 0xFFFFFFFF AMCLK2_LOW_HYS Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis 30 31 read-write AMCLK2_LOW_TH Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold 24 29 read-write AMCLK2_UP_HYS Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis 22 23 read-write AMCLK2_UP_TH Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold 16 21 read-write AMCLK1_LOW_HYS Analog Module Clock 1 (MI_CLK) Lower Hysteresis 14 15 read-write AMCLK1_LOW_TH Analog Module Clock 1 (MI_CLK) Lower Limit Threshold 8 13 read-write AMCLK1_UP_HYS Analog Module Clock 1 (MI_CLK) Upper Hysteresis 6 7 read-write AMCLK1_UP_TH Analog Module Clock 1 (MI_CLK) Upper Limit Threshold 0 5 read-write STCALIB System Tick Calibration Register 0x6C 32 0x00000000 0xFFFFFFFF STCALIB System Tick Calibration 0 25 read-write SYS_IS System Interrupt Status 0x18 32 0x00000000 0xFFFFFFFF ADC2_ESM_IS ADC2 Exceptional Sequence Measurement Interrupt Status 15 15 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_OVL_IS VREF5V Overload Interrupt Status 14 14 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_UPTH_IS VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status 13 13 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_LOWTH_IS VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status 12 12 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 REFBG_UPTHWARN_IS 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status 11 11 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 REFBG_LOTHWARN_IS 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status 10 10 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 SYS_OT_IS System Overtemperature Shutdown (ADC2, Channel 8) interrupt status 9 9 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 SYS_OTWARN_IS System Overtemperature Prewarning (ADC2, Channel 8) interrupt status 8 8 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 PMU_OT_IS PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status 7 7 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 PMU_OTWARN_IS PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status 6 6 read-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 LIN_TMOUT_IS LIN TXD timeout 2 2 read-only INACTIVE no interrupt status set 0b0 ACTIVE LIN TXD timeout occurred 0b1 LIN_OT_IS LIN Overtemperature interrupt status 1 1 read-only INACTIVE no interrupt status set 0b0 ACTIVE LIN Overtemperature occurred 0b1 LIN_OC_IS LIN Overcurrent interrupt status 0 0 read-only INACTIVE no interrupt status set 0b0 ACTIVE LIN Overcurrent occurred 0b1 SYS_ISCLR System Interrupt Status Clear 0x14 32 0x00000000 0xFFFFFFFF ADC2_ESM_ICLR ADC2 Exceptional Sequence Measurement Interrupt Status 15 15 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_OVL_ICLR VREF5V Overload Interrupt Status 14 14 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_UPTH_ICLR VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status 13 13 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 VREF5V_LOWTH_ICLR VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status 12 12 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 REFBG_UPTHWARN_ICLR 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status 11 11 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 REFBG_LOTHWARN_ICLR 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status 10 10 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 SYS_OT_ICLR System Overtemperature Shutdown (ADC2, Channel 8) interrupt status 9 9 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 SYS_OTWARN_ICLR System Overtemperature Prewarning (ADC2, Channel 8) interrupt status 8 8 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 PMU_OT_ICLR PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status 7 7 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 PMU_OTWARN_ICLR PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status 6 6 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 LIN_TMOUT_ICLR LIN TXD timeout 2 2 write-only INACTIVE no interrupt status set 0b0 ACTIVE LIN Overtemperature occurred 0b1 LIN_OT_ICLR LIN Overtemperature interrupt status 1 1 write-only INACTIVE no interrupt status set 0b0 ACTIVE LIN Overtemperature occurred 0b1 LIN_OC_ICLR LIN Overcurrent interrupt status 0 0 write-only INACTIVE no interrupt status set 0b0 ACTIVE at least one interrupt status set 0b1 BDRV_IS Bridge Driver Interrrupt Status 0x58 32 0x00000000 0xFFFFFFFF VSD_UPTH_STS Warning for VSD Upper Threshold Measurement (ADC2 channel 6) Status 28 28 read-only INACTIVE no overvoltage status set 0b0 ACTIVE overvoltage status set 0b1 VSD_LOWTH_STS Warning for VSD Lower Threshold Measurement (ADC2 channel 6) Status 27 27 read-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VCP_UPTH_STS Warning for VCP Upper Threshold Measurement (ADC2 channel 7) Status 26 26 read-only INACTIVE no overvoltage status set 0b0 ACTIVE overvoltage status set 0b1 VCP_LOWTH1_STS Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 7) Status 25 25 read-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VCP_LOWTH2_STS Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status 24 24 read-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VSD_UPTH_IS Warning for VSD Upper Threshold Measurement (ADC2 channel 6) Interrupt Status 20 20 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VSD_LOWTH_IS Warning for VSD Lower Threshold Measurement (ADC2 channel 6) Interrupt Status 19 19 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_UPTH_IS Warning for VCP Upper Threshold Measurement (ADC2 channel 7) Interrupt Status 18 18 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_LOWTH1_IS Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 7) Interrupt Status 17 17 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_LOWTH2_IS Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status 16 16 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 HS2_OC_IS External High Side 2 FET Over-current Status 13 13 read-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 HS1_OC_IS External High 1 FET Over-current Status 12 12 read-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 LS2_OC_IS External Low Side 2 FET Over-current Status 11 11 read-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 LS1_OC_IS External Low Side 1 FET Over-current Status 10 10 read-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 HS2_DS_IS Bridge Driver High Side 2 Pre-Driver short Interrupt Status 3 3 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 HS1_DS_IS Bridge Driver High Side 1 Pre-Driver short Interrupt Status 2 2 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 LS2_DS_IS Bridge Driver Low Side 2 Pre-Driver short Interrupt Status 1 1 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 LS1_DS_IS Bridge Driver Low Side 1 Pre-Driver short Interrupt Status 0 0 read-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 BDRV_ISCLR Bridge Driver Interrrupt Status Clear 0x54 32 0x00000000 0xFFFFFFFF VSD_UPTH_SCLR Warning for VSD Upper Threshold Measurement (ADC2 channel 6) Status 28 28 write-only INACTIVE no overvoltage status set 0b0 ACTIVE overvoltage status set 0b1 VSD_LOWTH_SCLR Warning for VSD Lower Threshold Measurement (ADC2 channel 6) Status 27 27 write-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VCP_UPTH_SCLR Warning for VCP Upper Threshold Measurement (ADC2 channel 7) Status 26 26 write-only INACTIVE no overvoltage status set 0b0 ACTIVE overvoltage status set 0b1 VCP_LOWTH1_SCLR Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 7) Status 25 25 write-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VCP_LOWTH2_SCLR Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status 24 24 write-only INACTIVE no undervoltage status set 0b0 ACTIVE undervoltage status set 0b1 VSD_UPTH_ICLR Warning for VSD Upper Threshold Measurement (ADC2 channel 6) Interrupt Status 20 20 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VSD_LOWTH_ICLR Warning for VSD Lower Threshold Measurement (ADC2 channel 6) Interrupt Status 19 19 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_UPTH_ICLR Warning for VCP Upper Threshold Measurement (ADC2 channel 7) Interrupt Status 18 18 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_LOWTH1_ICLR Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 7) Interrupt Status 17 17 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 VCP_LOWTH2_ICLR Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status 16 16 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 HS2_OC_ICLR External High Side 2 FET Over-current Status 13 13 write-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 HS1_OC_ICLR External High 1 FET Over-current Status 12 12 write-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 LS2_OC_ICLR External Low Side 2 FET Over-current Status 11 11 write-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 LS1_OC_ICLR External Low Side 1 FET Over-current Status 10 10 write-only INACTIVE no interrupt status set. 0b0 ACTIVE at least one interrupt status set. 0b1 HS2_DS_ICLR Bridge Driver High Side 2 Pre-Driver short Interrupt Status 3 3 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 HS1_DS_ICLR Bridge Driver High Side 1 Pre-Driver short Interrupt Status 2 2 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 LS2_DS_ICLR Bridge Driver Low Side 2 Pre-Driver short Interrupt Status 1 1 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 LS1_DS_ICLR Bridge Driver Low Side 1 Pre-Driver short Interrupt Status 0 0 write-only INACTIVE no interrupt status set 0b0 ACTIVE interrupt status set 0b1 SYS_SUPPLY_IRQ_STS System Supply Interrupt Status 0x1C 32 0x00000000 0xFFFFFFFF VDD1V5_OV_STS VDDC Overvoltage Status 23 23 read-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD5V_OV_STS VDDP Overvoltage Status 22 22 read-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VS_OV_STS VS Overvoltage Interrupt Status 21 21 read-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VBAT_OV_STS VBAT Overvoltage Status 20 20 read-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD1V5_UV_STS VDDC Undervoltage Status 19 19 read-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD5V_UV_STS VDDP Undervoltage Status 18 18 read-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VS_UV_STS VS Undervoltage Status 17 17 read-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VBAT_UV_STS VBAT Undervoltage Status 16 16 read-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD1V5_OV_IS VDDC Overvoltage Interrupt Status (ADC2 channel 3) 7 7 read-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD5V_OV_IS VDDP Overvoltage Interrupt Status (ADC2 channel 2) 6 6 read-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VS_OV_IS VS Overvoltage Interrupt Status (ADC2 channel 1) 5 5 read-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VBAT_OV_IS VBAT Overvoltage Interrupt Status (ADC2 channel 0) 4 4 read-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD1V5_UV_IS VDDC Undervoltage Interrupt Status (ADC2 channel 3) 3 3 read-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VDD5V_UV_IS VDDP Undervoltage Interrupt Status (ADC2 channel 2) 2 2 read-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VS_UV_IS VS Undervoltage Interrupt Status (ADC2 channel 1) 1 1 read-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VBAT_UV_IS VBAT Undervoltage Interrupt Status (ADC2 channel 0) 0 0 read-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 SYS_SUPPLY_IRQ_CLR System Supply Interrupt Status Clear 0x24 32 0x00000000 0xFFFFFFFF VDD1V5_OV_SCLR VDDC Overvoltage Status 23 23 write-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD5V_OV_SCLR VDDP Overvoltage Status 22 22 write-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VS_OV_SCLR VS Overvoltage Interrupt Status 21 21 write-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VBAT_OV_SCLR VBAT Overvoltage Status 20 20 write-only No Overvoltage occurred 0b0 Overvoltage occurred 0b1 VDD1V5_UV_SCLR VDDC Undervoltage Status 19 19 write-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD5V_UV_SCLR VDDP Undervoltage Status 18 18 write-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VS_UV_SCLR VS Undervoltage Status 17 17 write-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VBAT_UV_SCLR VBAT Undervoltage Status 16 16 write-only No Undervoltage occurred 0b0 Undervoltage occurred 0b1 VDD1V5_OV_ICLR VDDC Overvoltage Interrupt Status (ADC2 channel 3) 7 7 write-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD5V_OV_ICLR VDDP Overvoltage Interrupt Status (ADC2 channel 2) 6 6 write-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VS_OV_ICLR VS Overvoltage Interrupt Status (ADC2 channel 1) 5 5 write-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VBAT_OV_ICLR VBAT Overvoltage Interrupt Status (ADC2 channel 0) 4 4 write-only No Overvoltage Interrupt occurred 0b0 Overvoltage Interrupt occurred 0b1 VDD1V5_UV_ICLR VDDC Undervoltage Interrupt Status (ADC2 channel 3) 3 3 write-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VDD5V_UV_ICLR VDDP Undervoltage Interrupt Status (ADC2 channel 2) 2 2 write-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VS_UV_ICLR VS Undervoltage Interrupt Status (ADC2 channel 1) 1 1 write-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 VBAT_UV_ICLR VBAT Undervoltage Interrupt Status (ADC2 channel 0) 0 0 write-only No Undervoltage Interrupt occurred 0b0 Undervoltage Interrupt occurred 0b1 SYS_IRQ_CTRL System Interrupt Control 0x28 32 0x00000000 0xFFFFFFFF ADC2_ESM_IE ADC2 Exceptional Sequence Measurement Interrupt Enable 15 15 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VREF5V_OVL_IE VREF5V Overload Interrupt Enable 14 14 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VREF5V_UPTH_IE VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Enable 13 13 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VREF5V_LOWTH_IE VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Enable 12 12 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 REFBG_UPTHWARN_IE Reference Voltage Overvoltage Interrupt Enable 11 11 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 REFBG_LOTHWARN_IE Reference Voltage Undervoltage Interrupt Enable 10 10 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 SYS_OT_IE System Overtemperature Shutdown Interrupt Enable (leads to shutdown of System) 9 9 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 SYS_OTWARN_IE System Overtemperature Warning Interrupt Enable 8 8 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 PMU_OT_IE PMU Regulator Overtemperature Shutdown Interrupt Enable (leads to shutdown of System) 7 7 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 PMU_OTWARN_IE PMU Regulator Overtemperature Warning Interrupt Enable 6 6 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LIN_TMOUT_IE LIN TXD timeout Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LIN_OT_IE LIN Overtemperature Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LIN_OC_IE LIN Overcurrent Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 BDRV_IRQ_CTRL Bridge Driver Interrupt Control 0x5C 32 0x00000000 0xFFFFFFFF VSD_UPTH_IE VSD Measurement Upper Threshold Interrupt Enable 20 20 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VSD_LOWTH_IE VSD Measurement Lower Threshold Interrupt Enable 19 19 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VCP_UPTH_IE VCP Measurement Upper Threshold Interrupt Enable 18 18 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VCP_LOWTH1_IE VCP Measurement Lower Threshold 1 Interrupt Enable 17 17 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VCP_LOWTH2_IE VCP Measurement Lower Threshold 2 Interrupt Enable 16 16 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 HS2_OC_IE External High Side 2 FET Over-current Interrupt Enable 13 13 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 HS1_OC_IE External High Side 1 FET Over-current Interrupt Enable 12 12 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LS2_OC_IE External Low Side 2 FET Over-current Interrupt Enable 11 11 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LS1_OC_IE External Low Side 1 FET Over-current Interrupt Enable 10 10 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 HS2_DS_IE Bridge Driver High Side 2 Pre-Driver Short Interrupt Enable 3 3 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 HS1_DS_IE Bridge Driver High Side 1 Pre-Driver Short Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LS2_DS_IE Bridge Driver Low Side 2 Pre-Driver Short Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 LS1_DS_IE Bridge Driver Low Side 1 Pre-Driver Short Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 SYS_SUPPLY_IRQ_CTRL System Supply Interrupt Control 0x20 32 0x000000FF 0xFFFFFFFF VDD1V5_OV_IE VDD1V5 Overvoltage Interrupt Enable 7 7 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VDD5V_OV_IE VDD5V Overvoltage Interrupt Enable 6 6 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VS_OV_IE VS Overvoltage Interrupt Enable 5 5 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VBAT_OV_IE VBAT Overvoltage Interrupt Enable 4 4 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VDD1V5_UV_IE VDD1V5 Undervoltage Interrupt Enable 3 3 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VDD5V_UV_IE VDD5V Undervoltage Interrupt Enable 2 2 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VS_UV_IE VS Undervoltage Interrupt Enable 1 1 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 VBAT_UV_IE VBAT Undervoltage Interrupt Enable 0 0 read-write value1 Interrupt is disabled 0b0 value2 Interrupt is enabled 0b1 PCU_CTRL_STS Power Control Unit Control Status 0x30 32 0x06E37EF3 0xFFFFFFFF CLKLOSS_SD_DIS Power Switches Loss of Clock Shutdown Disable (AMCLK3) 25 25 read-write Enable Automatic Shutdown Signal for Power Switches in case of loss of clock 0b0 Disable Automatic Shutdown Signal for Power Switches in case of loss of clock 0b1 SYS_OT_PS_DIS System Overtemperature Power Switches Shutdown Disable 24 24 read-write Enable Automatic Shutdown Signal for Power Switches in case of system overtemperature preenable 0b0 Disable Automatic Shutdown Signal for Power Switches in case of system overtemperature enable 0b1 LIN_VS_UV_SD_DIS LIN Module VS Undervoltage Transmitter Shutdown 8 8 read-write Enable Automatic Shutdown for Power modules in case of VS Undervoltage enabled 0b0 Disable Automatic Shutdown for Power modules in case of VS Undervoltage disabled 0b1 FAIL_PS_DIS Disable LIN, BDRV and CP because of Overtemperature 7 7 read-write Switch off Enabled LIN, BDRV and CP will be turned off when Overtemperature occurs 0b0 Switch off Disabled LIN, BDRV and CP will be kept on when Overtemperature occurs . 0b1 CLKWDT_SD_DIS Power Modules Clock Watchdog Shutdown Disable 1 1 read-write Shutdown Enable Power Devices will be switched off when Clock Watchdog occurs 0b0 Shutdown Disable Power Devices will not be shutdown when Clock Watchog occurs 0b1 BFSTS Bus Fault Status 0x80 32 0x00000000 0xFFFFFFFF SBFSTS System Bus Fault Status Valid Flag 1 1 read-only Valid Adress is valid 0b1 not valid Adress is not valid 0b0 DBFSTS Data Bus Fault Status Valid Flag 0 0 read-only Valid Adress is valid 0b1 not valid Adress is not valid 0b0 BFSTS_CLR Bus Fault Status Clear Register 0x8C 32 0x00000000 0xFFFFFFFF SBFSTSCLR System Bus Fault Status Clear Flag 1 1 write-only Cleared Valid Adress is cleared 0b1 not cleared Valid Adress is not cleared 0b0 DBFSTSCLR Data Bus Fault Status Clear Flag 0 0 write-only Cleared Adress is cleared 0b1 not cleared Adress is not cleared 0b0 DBFA Data Bus Fault Address Register 0x84 32 0x00000000 0x00000000 DBFA Reserved 0 31 read-only SBFA System Bus Fault Address Register 0x88 32 0x00000000 0x00000000 SBFA Reserved 0 31 read-only WDT1_TRIG WDT1 Watchdog Control 0x34 32 0x00000108 0xFFFFFFFF SOWCONF Short Open Window Configuration 6 7 read-write DIS Short Open Windows disabled 0b00 SOW1 one successive Short Open Window allowed 0b01 SOW2 two successive Short Open Windows allowed 0b10 SOW3 three successive Short Open Windows allowed 0b11 WDP_SEL Watchdog Period Selection and trigger 0 5 read-write SOW_TRIG trigger short open window 0x00 WP_1 Watchdog period 16 ms 0x01 WP_2 Watchdog period 32 ms 0x02 WP_3 Watchdog period 48 ms 0x03 WP_63 Watchdog period 1008 ms 0x3F CPU CPU 0xE000E000 0x0 0x1000 registers ICT Interrupt Controller Type 0x004 32 0x00000000 0xFFFFFFFF INTLINESNUM Interrupt Lines 0 4 read-only value1 0 to 32 0b00000 value2 33 to 64 0b00001 value3 65 to 95 0b00010 value4 97 to 128 0b00011 value5 129 to 160 0b00100 value6 161 to 192 0b00101 value7 193 to 224 0b00110 value8 225 to 256 0b00111 SYSTICK_CS SysTick Control and Status 0x010 32 0x00000000 0xFFFFFFFF COUNTFLAG Count Flag 16 16 read-write CLKSOURCE CLK Source 2 2 read-write value1 external reference clock (STCLK : 4:1 from hclk) 0b0 value2 core clock (HCLK) 0b1 TICKINT TICKINT 1 1 read-write value1 counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 0b0 value2 counting down to 0 pends the SysTick handler. 0b1 ENABLE Enable 0 0 read-write value1 counter disabled. 0b0 value2 counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0b1 SYSTICK_RL SysTick Reload Value 0x014 32 0x00000000 0xFF000000 RELOAD Reload 0 23 read-write SYSTICK_CUR SysTick Current Value 0x018 32 0x00000000 0xFF000000 CURRENT Current 0 23 read-write SYSTICK_CAL SysTick Calibration Value 0x01C 32 #00000000000000000000000000000000 #00111111000000000000000000000000 NOREF No Reference Clock 31 31 read-only value1 n.u. 0b0 value2 the reference clock is not provided 0b1 SKEW Skew 30 30 read-only value1 n.u. 0b0 value2 the calibration value is not exactly 10 ms because of clock frequency. This could affect its suitability as a software real time clock. 0b1 TENMS Tenms 0 23 read-only NVIC_ISER0 Interrupt Set-Enable 0x100 32 0x00000000 0xFFFFFFFF Int_DMA Interrupt Set for DMA 15 15 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_BDRV Interrupt Set for Bridge Driver 14 14 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT1 Interrupt Set for External Int 1 13 13 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT0 Interrupt Set for External Int 0 12 12 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART2 Interrupt Set for UART2 11 11 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART1 Interrupt Set for UART1 10 10 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC2 Interrupt Set for SSC2 9 9 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC1 Interrupt Set for SSC1 8 8 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR3 Interrupt Set for CCU6 SR3 7 7 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR2 Interrupt Set for CCU6 SR2 6 6 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR1 Interrupt Set for CCU6 SR1 5 5 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR0 Interrupt Set for CCU6 SR0 4 4 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC1 Interrupt Set for ADC1 3 3 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC2 Interrupt Set for MU, ADC2 2 2 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT2 Interrupt Set for GPT2 1 1 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT1 Interrupt Set for GPT1 0 0 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 NVIC_ICER0 Interrupt Clear-Enable 0x180 32 0x00000000 0xFFFFFFFF Int_DMA Interrupt Clr for DMA 15 15 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_BDRV Interrupt Clear for Bridge Driver 14 14 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT1 Interrupt Clear for External Int 1 13 13 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT0 Interrupt Clear for External Int 0 12 12 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART2 Interrupt Clear for UART2 11 11 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART1 Interrupt Clear for UART1 10 10 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC2 Interrupt Clear for SSC2 9 9 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC1 Interrupt Clear for SSC1 8 8 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR3 Interrupt Clear for CCU6 SR3 7 7 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR2 Interrupt Clear for CCU6 SR2 6 6 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR1 Interrupt Clear for CCU6 SR1 5 5 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR0 Interrupt Clear for CCU6 SR0 4 4 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC1 Interrupt Clear for ADC1 3 3 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC2 Interrupt Clear for MU, ADC2 2 2 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT2 Interrupt Clear for GPT2 1 1 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT1 Interrupt Clear for GPT1 0 0 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 NVIC_ISPR0 Interrupt Set-Pending 0x200 32 0x00000000 0xFFFFFFFF Int_DMA Interrupt Set Pend for DMA 15 15 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_BDRV Interrupt Set Pending for Bridge Driver 14 14 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT1 Interrupt Set Pending for External Int 1 13 13 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT0 Interrupt Set Pending for External Int 0 12 12 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART2 Interrupt Set Pending for UART2 11 11 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART1 Interrupt Set Pending for UART1 10 10 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC2 Interrupt Set Pending for SSC2 9 9 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC1 Interrupt Set Pending for SSC1 8 8 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR3 Interrupt Set Pending for CCU6 SR3 7 7 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR2 Interrupt Set Pending for CCU6 SR2 6 6 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR1 Interrupt Set Pending for CCU6 SR1 5 5 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR0 Interrupt Set Pending for CCU6 SR0 4 4 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC1 Interrupt Set Pending for ADC1 3 3 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC2 Interrupt Set Pending for MU, ADC2 2 2 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT2 Interrupt Set Pending for GPT2 1 1 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT1 Interrupt Set Pending for GPT1 0 0 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 NVIC_ICPR0 Interrupt Clear-Pending 0x280 32 0x00000000 0xFFFFFFFF Int_DMA Interrupt Clr Pend for DMA 15 15 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_BDRV Interrupt Clear Pending for Bridge Driver 14 14 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT1 Interrupt Clear Pending for External Int 1 13 13 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT0 Interrupt Clear Pending for External Int 0 12 12 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART2 Interrupt Clear Pending for UART2 11 11 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART1 Interrupt Clear Pending for UART1 10 10 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC2 Interrupt Clear Pending for SSC2 9 9 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC1 Interrupt Clear Pending for SSC1 8 8 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR3 Interrupt Clear Pending for CCU6 SR3 7 7 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR2 Interrupt Clear Pending for CCU6 SR2 6 6 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR1 Interrupt Clear Pending for CCU6 SR1 5 5 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR0 Interrupt Clear Pending for CCU6 SR0 4 4 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC1 Interrupt Clear Pending for ADC1 3 3 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC2 Interrupt Clear Pending for MU, ADC2 2 2 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT2 Interrupt Clear Pending for GPT2 1 1 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT1 Interrupt Clear Pending for GPT1 0 0 read-write DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 NVIC_IABR0 Active Bit Register Interrupt Active Flags 0x300 32 0x00000000 0xFFFFFFFF Int_DMA Interrupt Active for DMA 15 15 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_BDRV Interrupt Active for Bridge Driver 14 14 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT1 Interrupt Active for External Int 1 13 13 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_EXINT0 Interrupt Active for External Int 0 12 12 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART2 Interrupt Active for UART2 11 11 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_UART1 Interrupt Active for UART1 10 10 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC2 Interrupt Active for SSC2 9 9 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_SSC1 Interrupt Active for SSC1 8 8 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR3 Interrupt Active for CCU6 SR3 7 7 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR2 Interrupt Active for CCU6 SR2 6 6 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR1 Interrupt Active for CCU6 SR1 5 5 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_CCU6SR0 Interrupt Active for CCU6 SR0 4 4 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC1 Interrupt Active for ADC1 3 3 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_ADC2 Interrupt Active for MU, ADC2 2 2 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT2 Interrupt Active for GPT2 1 1 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 Int_GPT1 Interrupt Active for GPT1 0 0 read-only DISABLE disables interrupt for read operation, no effect for write operation 0b0 ENABLE enables interrupt for read and write operation 0b1 NVIC_IPR0 Interrupt Priority 0x400 32 0x00000000 0xFFFFFFFF PRI_ADC1 Priority for ADC1 24 31 read-write PRI_ADC2 Priority for MU, ADC2 16 23 read-write PRI_GPT2 Priority for GPT2 8 15 read-write PRI_GPT1 Priority for GPT1 0 7 read-write NVIC_IPR1 Interrupt Priority 0x404 32 0x00000000 0xFFFFFFFF PRI_CCU6SR3 Priority for CCU6 SR3 24 31 read-write PRI_CCU6SR2 Priority for CCU6 SR2 16 23 read-write PRI_CCU6SR1 Priority for CCU6 SR1 8 15 read-write PRI_CCU6SR0 Priority for CCU6 SR0 0 7 read-write NVIC_IPR2 Interrupt Priority 0x408 32 0x00000000 0xFFFFFFFF PRI_UART2 Priority for UART2 24 31 read-write PRI_UART1 Priority for UART1 16 23 read-write PRI_SSC2 Priority for SSC2 8 15 read-write PRI_SSC1 Priority for SSC1 0 7 read-write NVIC_IPR3 Interrupt Priority 0x40C 32 0x00000000 0xFFFFFFFF PRI_DMA Priority for DMA 24 31 read-write PRI_BDRV Priority for Bridge Driver 16 23 read-write PRI_EXINT1 Priority for Ext. Int 1 8 15 read-write PRI_EXINT0 Priority for Ext. Int 0 0 7 read-write CPUID CPU ID Base Register 0xD00 32 0x412FC231 0xFFFFFFFF IMPLEMENTER Implementer Code 24 31 read-only VARIANT Variant Number 20 23 read-only ARCHITECTURE Architecture 16 19 read-only PARTNO Part Number 4 15 read-only REVISION Revision Number 0 3 read-only ICSR Interrupt Control State Register 0xD04 32 0x00000000 0xFFFFFFFF NMIPENDSET NMI PendSet 31 31 read-write value1 on writes, has no effect. On reads, NMI is active. 0b0 value2 on writes, make the NMI exception active. On reads, NMI is active. 0b1 PENDSVSET PENDSVSET 28 28 read-write value1 on writes, has no effect. On reads, PendSV is not pending. 0b0 value2 on writes, make PendSV exception pending. On reads, PendSV is pending. 0b1 PENDSVCLR PENDSVCLR 27 27 write-only value1 no effect 0b0 value2 remove pending status 0b1 PENDSTSET PENDSTSET 26 26 read-write value1 on writes, has no effect. On reads, SysTick is not pending. 0b0 value2 on writes, make SysTick exception pending. On reads, SysTick is pending. 0b1 PENDSTCLR PENDSTCLR 25 25 write-only value1 no effect 0b0 value2 remove pending status 0b1 ISRPREEMPT ISRPREEMPT 23 23 read-only value1 will not service 0b0 value2 will service a pending exception 0b1 ISRPENDING ISRPENDING 22 22 read-only value1 no external interrupt is pending 0b0 value2 external interrupt is pending 0b1 VECTPENDING VECTPENDING 12 20 read-only value1 no pending exceptions 0b0 RETTOBASE RETTOBASE 11 11 read-only value1 There is an active exception other than the exception shown by IPSR. 0b0 value2 There is no active exception other than any exception shown by IPSR. 0b1 VECTACTIVE VECTACTIVE 0 8 read-only value1 Thread mode 0b0 VTOR Vector Table Offset Register 0xD08 32 0x00000000 0xFFFFFFFF TBLOFF Vector Table Offset 7 31 read-write AIRCR Application Interrupt/Reset Control Register 0xD0C 32 0x00000000 0xFFFFFFFF VECTKEY Vector Key 16 31 read-write ENDIANNESS Memory System Endianness 15 15 read-only value1 little endian 0b0 value2 big endian 0b1 PRIGROUP Priority Grouping 8 10 read-write SYSRESETREQ System Reset Request 2 2 read-write value1 do not request a reset 0b0 value2 request a reset 0b1 VECTCLRACTIVE VECTCLRACTIVE 1 1 write-only VECTRESET VECTRESET 0 0 write-only SCR System Control Register 0xD10 32 0x00000000 0xFFFFFFFF SEVONPEND SEVONPEND 4 4 read-write value1 transitions from inactive to pending are not wake-up events 0b0 value2 transitions from inactive to pending are wake-up events 0b1 SLEEPDEEP Sleep Deep 2 2 read-write value1 selected sleep state is not deep sleep 0b0 value2 selected sleep state is deep sleep 0b1 SLEEPONEXIT Sleep on Exit 1 1 read-write value1 do not enter sleep state 0b0 value2 enter sleep state 0b1 CCR Configuration Control Register 0xD14 32 0x00000200 0xFFFFFFFF STKALIGN STKALIGN 9 9 read-write value1 guaranteed SP alignment is 4-byte, no SP adjustment is performed. 0b0 value2 8-byte alignment guaranteed, SP adjusted if necessary. 0b1 BFHFMIGN BFHFMIGN 8 8 read-write value1 precise data access fault causes a lockup 0b0 value2 handler ignores the fault 0b1 DIV_0_TRP DIV_0_TRP 4 4 read-write value1 trapping disabled 0b0 value2 trapping enabled 0b1 UNALIGN_TRP UNALIGN_TRP 3 3 read-write value1 trapping disabled 0b0 value2 trapping enabled 0b1 USERSETMPEND USERSETMPEND 1 1 read-write value1 unprivileged software cannot access the STIR. 0b0 value2 unprivileged software can access the STIR. 0b1 NONBASETHRDENA NONBASETHRDENA 0 0 read-write value1 any attempt to enter Thread mode at an execution priority level of other than base level faults. 0b0 value2 the processor can enter Thread mode at any execution priority level because of a controlled return value. 0b1 SHPR1 System Handler Priority Register 1 0xD18 32 0x00000000 0xFFFFFFFF PRI_7 Reserved for Priority of System Handler 7 24 31 read-write PRI_6 Priority of System Handler 6, UsageFault 16 23 read-write PRI_5 Priority of System Handler 5, BusFault 8 15 read-write PRI_4 Priority of System Handler 4, MemManage 0 7 read-write SHPR2 System Handler Priority Register 2 0x21C 32 0x00000000 0xFFFFFFFF PRI_11 Priority of System Handler 11, SVCall 24 31 read-write PRI_10 Reserved for Priority of System Handler 10 16 23 read-write PRI_9 Reserved for Priority of System Handler 9 8 15 read-write PRI_8 Reserved for Priority of System Handler 8 0 7 read-write SHPR3 System Handler Priority Register 3 0xD20 32 0x00000000 0xFFFFFFFF PRI_15 Priority of System Handler 15, SysTick 24 31 read-write PRI_14 Priority of System Handler 14, PendSV 16 23 read-write PRI_13 Reserved for Priority of System Handler 13 8 15 read-write PRI_12 Priority of System Handler 12, DebugMonitor 0 7 read-write SHCSR System Handler Control and State Register 0xD24 32 0x00000000 0xFFFFFFFF USGFAULTENA USGFAULTENA 18 18 read-write value1 Disable UsageFault 0b0 value2 Enable UsageFault 0b1 BUSFAULTENA BUSFAULTENA 17 17 read-write value1 Disable BusFault 0b0 value2 Enable BusFault 0b1 MEMFAULTENA MEMFAULTENA 16 16 read-write value1 Disable MemManage fault 0b0 value2 Enable MemManage fault 0b1 SVCALLPENDED SVCALLPENDED 15 15 read-write value1 SVCall is not pending 0b0 value2 SVCall is pending 0b1 BUSFAULTPENDED BUSFAULTPENDED 14 14 read-write value1 BusFault is not pending 0b0 value2 BusFault is pending 0b1 MEMFAULTPENDED MEMFAULTPENDED 13 13 read-write value1 MemManage is not pending 0b0 value2 MemManage is pending 0b1 USGFAULTPENDED USGFAULTPENDED 12 12 read-write value1 UsageFault is not pending 0b0 value2 UsageFault is pending 0b1 SYSTICKACT SYSTICKACT 11 11 read-write value1 SysTick is not active 0b0 value2 SysTick is active 0b1 PENDSVACT PENDSVACT 10 10 read-write value1 PendSV is not active 0b0 value2 PendSV is active 0b1 MONITORACT MONITORACT 8 8 read-write value1 Monitor is not active 0b0 value2 Monitor is active 0b1 SVCALLACT SVCALLACT 7 7 read-write value1 SVCall is not active 0b0 value2 SVCall is active 0b1 USGFAULTACT USGFAULTACT 3 3 read-write value1 UsageFault is not active 0b0 value2 UsageFault is active 0b1 BUSFAULTACT BUSFAULTACT 1 1 read-write value1 BusFault is not active 0b0 value2 BusFault is active 0b1 MEMFAULTACT MEMFAULTACT 0 0 read-write value1 MemManage is not active 0b0 value2 MemManage is active 0b1 CFSR Configurable Fault Status Register 0xD28 32 0x00000000 0xFFFFFFFF DIVBYZERO Divide by Zero 25 25 read-write value1 No Divide by zero error has occurred. 0b0 value2 A divide by zero error has occurred. 0b1 UNALIGNED Unaligned 24 24 read-write value1 No unaligned access error has occurred. 0b0 value2 A unaligned access error has occurred. 0b1 NOCP No CP 19 19 read-write value1 No coprocessor access error has occurred. 0b0 value2 A coprocessor access error has occurred. 0b1 INVPC INVPC 18 18 read-write value1 No integrity check error has occurred. 0b0 value2 A integrity check error has occurred. 0b1 INVSTATE INVSTATE 17 17 read-write value1 EPSR.T bit and EPSR.IT bits are valid for instruction execution. 0b0 value2 Instruction executed with invalid EPSR.T or EPSR.IT field. 0b1 UNDEFINSTR Undefined Instruction 16 16 read-write value1 No Undefined Instruction Usage fault has occurred. 0b0 value2 The processor hat attempted to execute an undefined instruction. This might be an undefined instruction associated with an enabled coprocessor. 0b1 BFARVALID BFAR Valid 15 15 read-write value1 BFAR does not have valid contents. 0b0 value2 BFAR has valid contents. 0b1 LSPERR LSPERR 13 13 read-write value1 No bus fault occurred during FP lazy state preservation 0b0 value2 A bus fault occurred during FP lazy state preservation 0b1 STKERR STKERR 12 12 read-write value1 No derived bus fault occurred 0b0 value2 A derived bus fault occurred on exception entry 0b1 UNSTKERR UNSTKERR 11 11 read-write value1 No derived bus fault occurred 0b0 value2 A derived bus fault occurred on exception return 0b1 IMPRECISERR IMPRECISERR 10 10 read-write value1 No precise data access error has occurred 0b0 value2 An imprecise data access error has occurred. 0b1 PRECISERR PRECISERR 9 9 read-write value1 No precise data access error has occurred 0b0 value2 An imprecise data access error has occurred, and the processor has written the faulting address to the BFAR. 0b1 IBUSERR IBUSERR 8 8 read-write value1 No bus fault on an instruction prefetch has occurred. 0b0 value2 A bus fault on an instruction prefetch has occurred. The fault is signalled only if the instruction is issued. 0b1 MMARVALID MMARVALID 7 7 read-write value1 MMAR does not have valid contents. 0b0 value2 MMAR has valid contents. 0b1 MLSPERR MLSPERR 5 5 read-write value1 No MemManage fault occurred during FP lazy state preservation 0b0 value2 A MemManage fault occurred during FP lazy state preservation 0b1 MSTERR MSTERR 4 4 read-write value1 No derived MemManage fault occurred 0b0 value2 A derived MemManage fault occurred on exception entry 0b1 MUNSTKERR MUNSTKERR 3 3 read-write value1 No derived MemManage fault occurred 0b0 value2 A derived MemManage fault occurred on exception return 0b1 DACCVIOL DACCVIOL 1 1 read-write value1 No data access violation has occurred. 0b0 value2 Data access violation. The MMAR shows the data address that the load or store tried to access. 0b1 IACCVIOL IACCVIOL 0 0 read-write value1 No MPU or Execute Never (XN) default memory map access violation has occurred. 0b0 value2 MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred. The fault is signalled only if the instruction is issued. 0b1 HFSR Hard Fault Status Register 0xD2C 32 0x00000000 0xFFFFFFFF DEBUGEVT Debug Event 31 31 read-write value1 No Debug event has occurred 0b0 value2 Debug event has occurred. The Debug Fault Status Register has been updated. 0b1 FORCED Forced 30 30 read-write value1 No priority escalation has occurred 0b0 value2 Processor has escalated a configurable priority exception to HardFault 0b1 VECTTBL VECTTBL 1 1 read-write value1 No vector table read fault has occurred 0b0 value2 Vector table read fault has occurred 0b1 DFSR Debug Fault Status Register 0xD30 32 0x00000000 0xFFFFFFFF EXTERNAL External 4 4 read-write value1 No EDBGRQ debug event 0b0 value2 EDBGRQ debug event 0b1 VCATCH Vector Catch 3 3 read-write value1 No vector catch triggered 0b0 value2 Vector catch triggered 0b1 DWTTRAP DWTTRAP 2 2 read-write value1 No current debug event generated by the DWT 0b0 value2 At least one current debug event generated by the DWT 0b1 BKPT BKPT 1 1 read-write value1 No current breakpoint debug event 0b0 value2 At least one current breakpoint debug event 0b1 HALTED HALTED 0 0 read-write value1 No active halt request debug event 0b0 value2 Halt request debug event active 0b1 MMFAR MemManage Fault Status Register 0xD34 32 0x00000000 0x00000000 ADDRESS Data Address for an MPU Fault 0 31 read-write BFAR Bus Fault Status Register 0xD38 32 0x00000000 0x00000000 ADDRESS Data Address for a precise BusFault 0 31 read-write AFSR Auxiliary Fault Status Register 0xD3C 32 0x00000000 0xFFFFFFFF CP0 Access Privileges for Coprocessor 0 (n= 0-7, 10, 11) 0 1 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP1 Access Privileges for Coprocessor 1 (n= 0-7, 10, 11) 2 3 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP2 Access Privileges for Coprocessor 2 (n= 0-7, 10, 11) 4 5 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP3 Access Privileges for Coprocessor 3 (n= 0-7, 10, 11) 6 7 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP4 Access Privileges for Coprocessor 4 (n= 0-7, 10, 11) 8 9 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP5 Access Privileges for Coprocessor 5 (n= 0-7, 10, 11) 10 11 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP6 Access Privileges for Coprocessor 6 (n= 0-7, 10, 11) 12 13 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP7 Access Privileges for Coprocessor 7 (n= 0-7, 10, 11) 14 15 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP10 Access Privileges for Coprocessor 10 (n= 0-7, 10, 11) 20 21 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 CP11 Access Privileges for Coprocessor 11 (n= 0-7, 10, 11) 22 23 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault 0b00 value2 Privileged access only. An unprivileged access generates a NOCP UsageFault 0b01 value4 Full access 0b11 DMA DMA 0x50014000 0x0 0x4000 registers STATUS DMA Status 0x00 32 0x000D0000 0xFFFFFFFF CHNLS_MINUS1 Available Channels minus 1 16 20 read-only value1 controller configured to use 14 DMA channels 0b1101 STATE Current State of the Control State Machine 4 7 read-only value1 idle 0b0000 value2 reading channel controller date 0b0001 value3 reading source data end pointer 0b0010 value4 reading destination data end pointer 0b0011 value5 reading source data 0b0100 value6 writing destination data 0b0101 value7 waiting for DMA request to clear 0b0110 value8 writing channel controller data 0b0111 value9 stalled 0b1000 value10 done 0b1001 value11 peripheral scatter-gather transition 0b1010 MASTER_ENABLE Enable Status of the Controller 0 0 read-only DISABLED controller is disabled 0b0 ENABLED controller is enabled 0b1 CFG DMA Configuration 0x04 32 0x00000000 0xFFFFFFFF CHN1_PROT_CTRL CHN1_PROT_CTRL 5 7 write-only MASTER_ENABLE Enable for the Controller 0 0 write-only DISABLE disables the controller 0b0 ENABLE enables the controller 0b1 CTRL_BASE_PTR Channel Control Data Base Pointer 0x08 32 0x00000000 0xFFFFFFFF CTRL_BASE_PTR CTRL_BASE_PTR 9 31 read-write ALT_CTRL_BASE_PTR Channel Alternate Control Data Base Pointer 0x0C 32 0x00000100 0xFFFFFFFF ALT_CTRL_BASE_PTR Base Address of the Alternate Data Structure 0 31 read-only WAITONREQ_STATUS Channel Wait on Request Status 0x10 32 0x00000000 0xFFFFFFFF WAITONREQ_STATUS Channel Wait on Request Status 0 13 read-only LOW dma_waitonreq[C] is LOW. 0b0 HIGH dma_waitonreq[C] is HIGH. 0b1 CHNL_SW_REQUEST Channel Software Request 0x14 32 0x00000000 0xFFFFFFFF CHNL_SW_REQUEST CHNL_SW_REQUEST 0 13 write-only value1 does not create a DMA request for channel C. 0b0 value2 creates a DMA request for channel C. 0b1 CHNL_USEBURST_SET Channel Useburst Set 0x18 32 0x00000000 0xFFFFFFFF CHNL_USEBURST_SET CHNL_USEBURST_SET: 0b0=on read: DMA channel n responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2, or single, bus transfers., 0b1=on read: DMA channel n does not respond to requests that it receives on dma_req[C] or dma_sreq[C]. The controller only reponds to dma_req[C] requests and performs 2 transfers., 0b0=on write: No effect. Use the CHNL_USEBURST_CLR Register to set bit [C] to 0., 0b1=on write: Disables dma_sreq[C] from generating DMA requests. The controller performs 2 transfers., 0 13 read-write CHNL_USEBURST_CLR Channel Useburst Clear 0x1C 32 0x00000000 0xFFFFFFFF CHNL_USEBURST_CLR CHNL_USEBURST_CLR 0 13 write-only value1 No effect. Use the CHNL_USEBURST_SET Register to disable dma_sreq[] from generating requests. 0b0 value2 Enables dma_sreq[C] to generate DMA requests. 0b1 CHNL_REQ_MASK_SET Channel Request Mask Set 0x20 32 0x00000000 0xFFFFFFFF CHNL_REQ_MASK_SET CHNL_REQ_MASK_SET: 0b0=on read: External requests are enabled for channel C., 0b1=on read: External requests are disabled for channel C., 0b0=on write: No effect. Use the CHNL_REQ_MASK_CLR Register to enable DMA requests., 0b1=on write: Disables dma_req[C] and dma_sreq[C] from generating DMA requests., 0 13 read-write CHNL_REQ_MASK_CLR Channel Request Mask Clear 0x24 32 0x00000000 0xFFFFFFFF CHNL_REQ_MASK_CLR CHNL_REQ_MASK_CLR 0 13 write-only value1 No effect. Use the CHNL_REQ_MASK_SET Register to disable dma_req[] and dma_sreq[] from generating requests. 0b0 value2 Enables dma_req[C] or dma_sreq[C] to generate DMA request. 0b1 CHNL_ENABLE_SET Channel Enable Set 0x28 32 0x00000000 0xFFFFFFFF CHNL_ENABLE_SET CHNL_ENABLE_SET: 0b0=on read: Channel C is disabled., 0b1=on read: Channel C is enabled., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to disable a channel., 0b1=on write: Enables channel C., 0 13 read-write CHNL_ENABLE_CLR Channel Enable Clear 0x2C 32 0x00000000 0xFFFFFFFF CHNL_ENABLE_CLR CHNL_ENABLE_CLR 0 13 write-only value1 No effect. Use the CHNL_ENABLE_SET Register to enable DMA channels. 0b0 value2 Disables channel C. 0b1 CHNL_PRI_ALT_SET Channel Primary-Alternate Set 0x30 32 0x00000000 0xFFFFFFFF CHNL_PRI_ALT_SET CHNL_PRI_ALT_SET: 0b0=on read: DMA channel C is using the primary data structure., 0b1=on read: DMA channel C is using the alternate data structure., 0b0=on write: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [C] to 0., 0b1=on write: Selects the alternate data structure for channel C., 0 13 read-write CHNL_PRI_ALT_CLR Channel Primary-Alternate Clear 0x34 32 0x00000000 0xFFFFFFFF CHNL_PRI_ALT_CLR CHNL_PRI_ALT_CLR 0 13 write-only value1 No effect. Use the CHNL_PRI_ALT_SET Register to select the alternate data structure. 0b0 value2 Selects the primary data structure for channel C. 0b1 CHNL_PRIORITY_SET Channel Priority Set 0x38 32 0x00000000 0xFFFFFFFF CHNL_PRIORITY_SET CHNL_PRIORITY_SET: 0b0=on read: DMA channel C is using the default priority level., 0b1=on read: DMA channel C is using a high priority level., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to set channel C to the default priority level., 0b1=on write: Channel C uses the high priority level., 0 13 read-write CHNL_PRIORITY_CLR Channel Priority Clear 0x3C 32 0x00000000 0xFFFFFFFF CHNL_PRIORITY_CLR CHNL_PRIORITY_CLR 0 13 write-only value1 No effect. Use the CHNL_ENABLE_SET Register to set channel C to the high priority level. 0b0 value2 Channel C uses the default priority level. 0b1 ERR_CLR Bus Error Clear 0x4C 32 0x00000000 0xFFFFFFFF ERR_CLR ERR_CLR: 0b0=on read: dma_err is LOW., 0b1=on read: dma_err is HIGH., 0b0=on write: No effect, status of dma_err is unchanged., 0b1=on write: Sets dma_err LOW., 0 0 read-write TIMER3 TIMER3 0x48006000 0x0 0x21 registers T3_TRIGG_CTRL T3 Trigger Control 0x00 32 0x00000000 0xFFFFFFFF RETRIG Retrigger Condition (in mode 1b) for CCU6-T12 ZM and CCU6 PM 6 6 read-write DIS Retrigger disabled 0b0 EN Retrigger enabled 0b1 T3_RES_CONF Timer 3 Trigger Reset Selection for Mode 1b 4 5 read-write No Reset on PWM Edge Counter is not reset while PWM Module is running. 0x0 Reset On Rising Edge Counter is reset on rising edge input 0x1 Reset On Falling Edge Counter is reset on falling edge input. 0x2 Reset on both Edges Counter is reset on both edge inputs. 0x3 T3_TRIGG_INP_SEL Timer 3 Trigger Input Event Selection (only in mode3b) 0 2 read-write CCU6-CC6 0 Capture Compare Unit Channel 0 (CC60). 0x0 CCU6-CC61 Capture Compare Unit Channel 1 (CC61). 0x1 CCU6-CC62 Capture Compare Unit Channel 2 (CC62). 0x2 CCU6-T12 ZM Capture Compare Unit T12 Zero Match. 0x3 CCU6-T12 PM Capture Compare Unit T12 Period Match. 0x4 CCU6-COUT6 0 Capture Compare Unit Channel 0 (COUT60). 0x5 CCU6-COUT61 Capture Compare Unit Channel 1 (COUT61). 0x6 CCU6-COUT62 Capture Compare Unit Channel 2 (COUT62). 0x7 CMP Timer 3 Compare Value 0x04 32 0x00000000 0xFFFFFFFF HI Timer 3 Compare Value High Byte 8 15 read-write TIMER3_CMP_HI holds the compare value of high byte for Measurement Interface Trigger. 0b00000000 LO Timer 3 Compare Value Low Byte 0 7 read-write TIMER3_CMP_LO holds the compare value of low byte for Measurement Interface Trigger. 0b00000000 CNT Timer 3 0x08 32 0x00000000 0xFFFFFFFF HI Timer 3 High Register or Preload Value 8 15 read-write TIMER3_HI holds the higher 8-bit part of the 13-bit timer value. 0b00 TIMER3_HI holds the higher 8-bit part of the 16-bit timer value. 0b01 TIMER3_HI holds the 8-bit reload value. 0b10 TIMER3_HI holds the 8-bit timer value. 0b11 LO Timer 3 Low Register or Preload Value 0 7 read-write TIMER3_LO holds the lower 5-bit part of the 13-bit timer value. 0b00 TIMER3_LO holds the lower 8-bit part of the 16-bit timer value. 0b01 TIMER3_LO holds the 8-bit timer value. 0b10 TIMER3_LO holds the 8-bit timer value. 0b11 CTRL Timer 3 Control Register 0x0C 32 0x00000001 0xFFFFFFFF T3H_OVF_IE Timer 3 Overflow Interrupt Enable (High Byte Timer) 9 9 read-write DIS Interrupt disabled 0b0 EN Interrupt enabled 0b1 T3L_OVF_IE Timer 3 Overflow Interrupt Enable (Low Byte Timer) 8 8 read-write DIS Interrupt disabled. 0b0 EN Interrupt enabled 0b1 T3L_OVF_STS Timer 3 Overflow Flag (Low Byte Timer) 7 7 read-only T3L_OVF_STS No overflow occurred. 0b0 T3L_OVF_STS Overflow occured. Set by hardware when Low Byte of Timer 3 overflows. Cleared by software. 0b1 TR3L Timer 3 Run Control (Low Byte Timer) 6 6 read-write TR3L Timer is halted 0b0 TR3L Timer runs 0b1 T3H_OVF_STS Timer 3 Overflow Flag (High Byte Timer) 5 5 read-only T3H_OVF_STS No Overflow occured. 0b0 T3H_OVF_STS Overflow occured. Set by hardware when High Byte of Timer 3 overflows. Cleared by software. 0b1 TR3H Timer 3 Run Control (High Byte Timer) 4 4 read-write TR3H Timer is halted 0b0 TR3H Timer runs 0b1 CNT_RDY Timer 3 Count Ready 3 3 read-write CNT_RDY Timer hasn't finished counting in Mode 1b, 3b 0b0 CNT_RDY Timer has finished counting in Mode 1b, 3b 0b1 T3_RD_REQ_CONF Timer 3 Read Mode 2 2 read-write T3_RD_REQ_CONF Timer 3 Read Request can be triggered by software 0b0 T3_RD_REQ_CONF Timer 3 Read Request can be triggered by hardware (in mode 3b) 0b1 T3_RD_REQ Timer 3 Value Read Request 1 1 read-write T3_RD_REQ Timer value is not read from Timer 3 0b0 T3_RD_REQ Timer value is read from Timer 3 0b1 T3_PD_N Timer 3 Power Down 0 0 read-write Power Down Timer 3 is in Power Down 0b0 no Power Down Timer 3 is not in Power Down 0b1 ISRCLR Timer 3 Interrupt Status Clear Register 0x14 32 0x00000000 0xFFFFFFFF T3L_OVF_ICLR Timer 3 Overflow Flag (Low Byte Timer) Interrupt Clear 7 7 write-only T3L_OVF_ ICLR Overflow not cleared. 0b0 T3L_OVF_ ICLR Overflow cleared. Set by software, cleared by hardware. 0b1 T3H_OVF_ICLR Timer 3 Overflow Flag (High Byte Timer) Interrupt Clear 5 5 write-only T3H_OVF_ ICLR Overflow not cleared. 0b0 T3H_OVF_ ICLR Overflow cleared. Set by software, cleared by hardware 0b1 MODE_CONF Timer 3 Mode Configuration Register 0x10 32 0x00000001 0xFFFFFFFF T3_SUBM Sub-Mode Select Bits 6 7 read-write No Sub-Mode no Sub-Mode enabled 0b00 Mode 1b enables 16 bit Timer triggered by an event. This mode has only an effect with Mode 1 (16 Bit Mode) 0b01 Mode 3b enables two 8-Bit Timers for clock measurement. This Mode has only an effect with Mode 3. 0b10 T3M Mode Select Bits 0 1 read-write T3M 13-bit timer 0b00 T3M 16-bit timer 0b01 T3M 8-bit auto-reload timer 0b10 T3M Timer 3 is split into two halves. TL3 is an 8bit timer controlled by the standard Timer 3 low byte control bits, and TH3 is the other 8-bit timer controlled by the standard Timer 3 high byte control bits. 0b11 LIN LIN 0x4801E000 0x0 0x8 registers CTRL_STS LIN Transceiver Control and Status 0x00 32 #00000000000110000000001000000111 #11111111111110000001101111111111 M_SM_ERR_CLR LIN Transceiver Mode or Slope Mode Error Clear 24 24 write-only Mode or Slope Mode Error Status not clear 0b0 Mode or Slope Mode Error Status clear 0b1 HV_MODE LIN Transceiver High Voltage Input - Output Mode 21 21 read-write DISABLE High Voltage Mode Entry is disabled 0b0 ENABLE High Voltage Mode Entry is enabled 0b1 MODE_FB Feedback Signals for LIN Transmitter Mode Settings 16 18 read-only FB_SM3 Feedback Signal 3 for Slope Mode Setting 15 15 read-only FB_SM2 Feedback Signal 2 for Slope Mode Setting 14 14 read-only FB_SM1 Feedback Signal 1 for Slope Mode Setting 13 13 read-only SM LIN Transmitter Slope mode control 11 12 read-write Normal Slope Mode for max. 20 kBaud 0b00 Fast Slope Mode for max. 40 kBaud 0b01 Low Slope Mode for max. 10.4 kBaud 0b10 Flash Mode for max. 150 kBaud# 0b11 RXD Output Signal of Receiver 10 10 read-only TXD LIN Transmitter switch on (only used when LIN_HV_MODE is set) 9 9 read-write Pull Down LIN Line Transmitter is switched on 0b0 Pull Up Resistor is active Transmitter is switched off 0b1 TXD_TMOUT_STS LIN TXD time-out status 6 6 read-only NO_TIMEOUT no time-out occured 0b0 TIMEOUT time-out occured 0b1 OC_STS LIN Receiver Overcurrent Status 5 5 read-only no Overcurrent overcurrent status occured 0b0 Overcurrent overcurrent status occured 0b1 OT_STS LIN Receiver Overtemperature Status 4 4 read-only no Overtemperature overtemperature occured 0b0 Overtemperature overtemperature occured 0b1 M_SM_ERR LIN Transceiver Mode or Slope Mode Error 3 3 read-only no Mode or Slope Mode Error Status (see corresponding Feedback registers) 0b0 Mode or Slope Mode Error Status (see corresponding Feedback registers) 0b1 MODE LIN transceiver power mode control 1 2 read-write LIN Sleep Mode LIN module switched to LIN Sleep Mode 0b00 LIN Receive-Only Mode LIN module switched to LIN Receive Only Mode 0b01 n.u. not used 0b10 LIN Normal Mode LIN module switched to LIN Normal Mode 0b11 MF MF 0x48018000 0x0 0x4000 registers P2_ADCSEL_CTRL Port 2 ADC Selection Control Register 0x00 32 0x00000000 0xFFFFFFFF ADC1_CH1_SEL ADC1 Channel 1 Input Selection 10 10 read-write CS_AMP Current Sense Amplifier is conncted to Ch1 of ADC1 0b1 VMON_SEN_CTRL Supply Sense Control Register 0x04 32 0x00000000 0xFFFFFFFF VMON_SEN_SEL_INRANGE Monitoring Input Attenuator Select Inputrange 5 5 read-write 0 - 18V Range is selected 0b0 0 - 28V Range is selected 0b1 VMON_SEN_HRESO_5V Monitoring Input Attenuator High Impedance Output Control 4 4 read-write High Resistive Output Disable Connection to ADC input low ohmic 0b0 High Resistive Output Enable Connection to ADC input high ohmic 0b1 VMON_SEN_PD_N Monitoring Input Attenuator enable 0 0 read-write DISABLE Attenuator switched off 0b0 ENABLE Attenuator switched on 0b1 TEMPSENSE_CTRL Temperature Sensor Control Register 0x10 32 0x00000003 0xFFFFFFFF SYS_OT_STS System Overtemperature (MU) Status 7 7 read-only INACTIVE write clears status 0b0 ACTIVE interrupt status set 0b1 SYS_OTWARN_STS System Overtemperature Warning (MU) Status 6 6 read-only INACTIVE write clears status 0b0 ACTIVE interrupt status set 0b1 PMU_OT_STS PMU Regulator Overtemperature (MU) Status 5 5 read-only INACTIVE write clears status 0b0 ACTIVE interrupt status set 0b1 PMU_OTWARN_STS PMU Regulator Overtemperature Warning (MU) Status 4 4 read-only INACTIVE write clears status 0b0 ACTIVE interrupt status set 0b1 REF1_STS Reference 1 Status Register 0x14 32 0x000000C1 0xFFFFFFFF REFBG_UPTHWARN_STS Status for Overvoltage Threshold Measurement of internal VAREF 5 5 read-only UPPER_TRIG_RESET write clears status 0b0 UPPER_TRIG_SET trigger status set 0b1 REFBG_LOTHWARN_STS Status for Undervoltage Threshold Measurement of internal VAREF 4 4 read-only UPPER_TRIG_RESET write clears status 0b0 UPPER_TRIG_SET trigger status set 0b1 REF2_CTRL Reference 2 Control Register 0x18 32 0x00000001 0xFFFFFFFF VREF5V_OV_STS ADC1 Bit Reference Voltage Generation Overvoltage Bit 3 3 read-only no Overvoltage no Overvoltage detected 0b0 Overvoltage Overvoltage detected 0b1 VREF5V_UV_STS ADC1 Bit Reference Voltage Generation Undervoltage Bit 2 2 read-only no Undervoltage no Undervoltage detected 0b0 Undervoltage Undervoltage detected 0b1 VREF5V_OVL_STS ADC1 Bit Reference Voltage Generation Over Load Bit 1 1 read-only no OVERLOAD no OVERLOAD detected 0b0 OVERLOAD OVERLOAD detected 0b1 VREF5V_PD_N ADC1 Bit Reference Voltage Generation Power Down Bit 0 0 read-write DISABLED Power Down 0b0 ACTIVE no Power Down 0b1 CSA_CTRL Current Sense Amplifier Control Register 0x0C 32 0x00000000 0xFFFFFFFF VZERO Current Sense Output Voltage Level to Ground 8 8 read-write VOUT Output Voltage is VOUT of Amplifier 0b0 GROUND Output Voltage is Ground of Feedback Network 0b1 GAIN OPA gain setting 1 4 read-write GMIN TBD 0x0 GMAX TBD 0xF EN OPA enable 0 0 read-write DISABLE OPA switched off 0b0 ENABLE OPA switched on 0b1 ADC2 ADC2 0x4801C000 0x0 0x2000 registers CTRL_STS ADC2 Control and Status Register 0x00 32 0x00000001 0xFFFFFFFF VS_RANGE ADC2 Channel 1 Range Selection 17 17 read-write Range 1 Range from 3 to 22 V is selected 0b0 Range 2 Range from 3 to 28 V is selected 0b1 VBAT_RANGE ADC2 Channel 0 Range Selection 16 16 read-write Range 1 Range from 3 to 22 V is selected 0b0 Range 2 Range from 3 to 28 V is selected 0b1 HV_STS ADC2 HV Status Register 0xBC 32 0x00000000 0xFFFFFFFF READY HVADC Ready bit 1 1 read-only Not ready Module in power down or in init phase 0b0 Ready set automatically 5 ADC clock cycles after module is enabled 0b1 CTRL1 Measurement Unit Control Register 1 0x14 32 0x00000000 0xFFFFFFFF CALIB_EN Calibration Enable for Channels 0 to 5 0 5 read-write CH0_EN Channel 0 calibration enable 0b000001 CH1_EN Channel 1 calibration enable 0b000010 CH2_EN Channel 2 calibration enable 0b000100 CH3_EN Channel 3 calibration enable 0b001000 CH4_EN Channel 4 calibration enable 0b010000 CH5_EN Channel 5 calibration enable 0b100000 CTRL2 Measurement Unit Control Register 2 0x18 32 0x000F0805 0xFFFFFFFF SAMPLE_TIME_int Sample time of ADC2 8 11 read-write MICLK4 4 MI_CLK clock periods 0x0 MICLK6 6 MI_CLK clock periods 0x1 MICLK8 8 MI_CLK clock periods 0x2 MICLK10 10 MI_CLK clock periods 0x3 MICLK12 12 MI_CLK clock periods (default) 0x4 MICLK14 14 MI_CLK clock periods 0x5 MICLK16 16 MI_CLK clock periods 0x6 MICLK18 18 MI_CLK clock periods 0x7 MICLK20 20 MI_CLK clock periods 0x8 MICLK22 22 MI_CLK clock periods 0x9 n.u. not used 0xA n.u. not used 0xB n.u. not used 0xC n.u. not used 0xD n.u. not used 0xE n.u. not used 0xF MCM_RDY Ready Signal for MCM after Power On or Reset 7 7 read-only MCM Not Ready Measurement Core Module in startup phase 0b0 MCM Ready Measurement Core Module start-up phase finished 0b1 MCM_PD_N Power Down Signal for MCM 0 0 read-write MCM Disabled Measurement Core Module Disabled 0b0 MCM Enabled Measurement Core Module Enabled 0b1 CTRL4 Measurement Unit Control Register 4 0x1C 32 0x00000000 0xFFFFFFFF FILT_OUT_SEL_9_6 Output Filter Selection for Channels 6 to 9 8 11 read-write ADC2 Unfiltered Data can be monitored in the corresponding ADC2_FILT_OUTx Registers. 0b0000 Channel 6 IIR Data enabled for ADC2_FILT_OUT6 Register . 0b0001 Channel 7 IIR Data enabled for ADC2_FILT_OUT7 Register . 0b0010 Channel 8 IIR Data enabled for ADC2_FILT_OUT8 Register . 0b0100 Channel 9 IIR Data enabled for ADC2_FILT_OUT9 Register . 0b1000 For Channels 9-6 IIR Data is enabled for ADC2_FILT_OUTx Registers . 0b1111 FILT_OUT_SEL_5_0 Output Filter Selection for Channels 0 to 5 0 5 read-write ADC2 Unfiltered D ata can be monitored in the corresponding ADC2_FILT_OUTx Registers . 0b000000 Channel 0 IIR Data enabled for ADC2_FILT_OUT0 Register . 0b000001 Channel 1 IIR Data enabled for ADC2_FILT_OUT1 Register . 0b000010 Channel 2 IIR Data enabled for ADC2_FILT_OUT2 Register . 0b000100 Channel 3 IIR Data enabled for ADC2_FILT_OUT3 Register . 0b001000 Channel 4 IIR Data enabled for ADC2_FILT_OUT4 Register . 0b010000 Channel 5 IIR Data enabled for ADC2_FILT_OUT5 Register . 0b100000 For Channels 5-0 IIR Data is enabled for ADC2_FILT_OUTx Registers . 0b111111 SQ1_4 Measurement Channel Enable Bits for Cycle 1-4 0x20 32 0x29362837 0xFFFFFFFF SQ4 Sequence 4 channel enable 24 29 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ3 Sequence 3 channel enable 16 21 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ2 Sequence 2 channel enable 8 13 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ1 Sequence 1 channel enable 0 5 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ1_8_int Measurement Channel Enable Bits for Cycle 1 - 8 0x2C 32 0x7B7B7B1B 0xFFFFFFFF SQ8_int Sequence 8 channel enable 28 31 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ7_int Sequence 7 channel enable 24 27 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ6_int Sequence 6 channel enable 20 23 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ5_int Sequence 5 channel enable 16 19 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ4_int Sequence 4 channel enable 12 15 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ3_int Sequence 3 channel enable 8 11 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ2_int Sequence 2 channel enable 4 7 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ1_int Sequence 1 channel enable 0 3 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ5_8 Measurement Channel Enable Bits for Cycle 5 - 8 0x24 32 0x28372836 0xFFFFFFFF SQ8 Sequence 8 channel enable 24 29 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ7 Sequence 7 channel enable 16 21 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ6 Sequence 6 channel enable 8 13 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ5 Sequence 5 channel enable 0 5 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ9_10 Measurement Channel Enable Bits for Cycle 9 - 10 0x28 32 0x00002936 0xFFFFFFFF SQ10 Sequence 10 channel enable 8 13 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ9 Sequence 9 channel enable 0 5 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 SQ9_10_int Measurement Channel Enable Bits for Cycle 9 and 10 0x30 32 0x0000007B 0xFFFFFFFF SQ10_int Sequence 10 channel enable 4 7 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ9_int Sequence 9 channel enable 0 3 read-only CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 SQ_FB Sequencer Feedback Register 0x04 32 #00000000000000000000000000000000 #11111111111000001000000011110000 CHx Current ADC2 Channel 16 20 read-only CH0 Channel 0 enable 0b00000 CH1 Channel 1 enable 0b00001 CH2 Channel 2 enable 0b00010 CH3 Channel 3 enable 0b00011 CH4 Channel 4 enable 0b00100 CH5 Channel 5 enable 0b00101 CH6 Channel 6 enable 0b00110 CH7 Channel 7 enable 0b11101 CH8 Channel 8 enable 0b11110 CH9 Channel 9 enable 0b11111 SQx Current Active Sequencer 11 14 read-only SQ0 Sequence 0 enable 0b0000 SQ1 Sequence 1 enable 0b0001 SQ2 Sequence 2 enable 0b0010 SQ3 Sequence 3 enable 0b0011 SQ4 Sequence 4 enable 0b0100 SQ5 Sequence 5 enable 0b0101 SQ6 Sequence 6 enable 0b0110 SQ7 Sequence 7 enable 0b0111 SQ8 Sequence 8 enable 0b1000 SQ9 Sequence 9 enable 0b1001 ESM_ACTIVE ADC2 ESM active 10 10 read-only not active ESM not active 0b0 active ESM active 0b1 EIM_ACTIVE ADC2 EIM active 9 9 read-only not active EIM not active 0b0 active EIM active 0b1 SQ_STOP ADC2 Sequencer Stop Signal for DPP 8 8 read-only DPP Running Postprocessing Sequencer in running mode 0b0 DPP Stopped Postprocessing Sequencer stopped / Software Mode entered 0b1 SQ_FB Current Sequence that caused software mode 0 3 read-only SQ1 Sequence 1 0b0000 SQ2 Sequence 2 0b0001 SQ3 Sequence 3 0b0010 SQ4 Sequence 4 0b0011 SQ5 Sequence 5 0b0100 SQ6 Sequence 6 0b0101 SQ7 Sequence 7 0b0110 SQ8 Sequence 8 0b0111 SQ9 Sequence 9 0b1000 SQ10 Sequence 10 0b1001 ESM ESM 0b1010 CH_MASK Channel Mask = 0 0b1011 SUSPEND Debug Suspend Mode 0b1100 CHx_EIM Channel Settings Bits for Exceptional Interrupt Measurement 0x08 32 0x00000000 0xFFFFFFFF SEL Exceptional interrupt measurement (EIM) Trigger Trigger select 12 12 read-write CCU6_SEL ccu6_int triggers EIM 0b0 CP_SEL cp_clk triggers EIM 0b1 EN Exceptional interrupt measurement (EIM) Trigger Event enable 11 11 read-write DISABLE start of EIM disabled 0b0 ENABLE start of IEM enabled 0b1 REP Repeat count for exceptional interrupt measurement (EIM) 8 10 read-write 1 Measurements 0b000 2 Measurements 0b001 4 Measurements 0b010 8 Measurements 0b011 16 Measurements 0b100 32 Measurements 0b101 64 Measurements 0b110 128 Measurements 0b111 CHx Channel set for exceptional interrupt measurement (EIM) 0 4 read-write CH0_EN Channel 0 enable 0b00000 CH1_EN Channel 1 enable 0b00001 CH2_EN Channel 2 enable 0b00010 CH3_EN Channel 3 enable 0b00011 CH4_EN Channel 4 enable 0b00100 CH5_EN Channel 5 enable 0b00101 CH6_EN Channel 6 enable 0b00110 CH7_EN Channel 7 enable 0b11101 CH8_EN Channel 8 enable 0b11110 CH9_EN Channel 9 enable 0b11111 CHx_ESM Channel Settings Bits for Exceptional Sequence Measurement 0x0C 32 0x00000000 0xFFFFFFFF STS Exceptional Sequence Measurement is finished 17 17 read-only not active Exceptional Sequence Measurement not done 0b0 done Exceptional Sequence Measurement done 0b1 EN Enable for Exceptional Sequence Measurement Trigger Event 16 16 read-write Disable start of ESM disabled 0b0 Enable start of ESM enabled 0b1 SEL Exceptional Sequence Measurement Trigger Select 10 10 read-write CCU6_SEL ccu6_int starts ESM 0b0 CP_SEL cp_clk starts ESM 0b1 ESM_1 Channel Sequence for Exceptional Sequence Measurement (ESM) 6 9 read-write CH6_EN Channel 6 enable 0b0001 CH7_EN Channel 7 enable 0b0010 CH8_EN Channel 8 enable 0b0100 CH9_EN Channel 9 enable 0b1000 ESM_0 Channel Sequence for Exceptional Sequence Measurement (ESM) 0 5 read-write CH0_EN Channel 0 enable 0b000001 CH1_EN Channel 1 enable 0b000010 CH2_EN Channel 2 enable 0b000100 CH3_EN Channel 3 enable 0b001000 CH4_EN Channel 4 enable 0b010000 CH5_EN Channel 5 enable 0b100000 CAL_CH0_1 Calibration for Channel 0 & 1 0x34 32 0x00000000 0xFFFFFFFF GAIN_CH1 Gain Calibration for channel 1 24 31 read-write OFFS_CH1 Offset Calibration for channel 1 16 23 read-write GAIN_CH0 Gain Calibration for channel 0 8 15 read-write OFFS_CH0 Offset Calibration for channel 0 0 7 read-write CAL_CH2_3 Calibration for Channel 2 & 3 0x38 32 0x00000000 0xFFFFFFFF GAIN_CH3 Gain Calibration for channel 3 24 31 read-write OFFS_CH3 Offset Calibration for channel 3 16 23 read-write GAIN_CH2 Gain Calibration for channel 2 8 15 read-write OFFS_CH2 Offset Calibration for channel 2 0 7 read-write CAL_CH4_5 Calibration for Channel 4 & 5 0x3C 32 0x00000000 0xFFFFFFFF GAIN_CH5 Gain Calibration for channel 5 24 31 read-write OFFS_CH5 Offset Calibration for channel 5 16 23 read-write GAIN_CH4 Gain Calibration for channel 4 8 15 read-write OFFS_CH4 Offset Calibration for channel 4 0 7 read-write CAL_CH6_7 Calibration for Channel 6 & 7 0x40 32 0x00000000 0xFFFFFFFF GAIN_CH7 Gain Calibration for channel 7 24 31 read-only OFFS_CH7 Offset Calibration for channel 7 16 23 read-only GAIN_CH6 Gain Calibration for channel 6 8 15 read-only OFFS_CH6 Offset Calibration for channel 6 0 7 read-only CAL_CH8_9 Calibration for Channel 8 & 9 0x44 32 0x00000000 0xFFFFFFFF GAIN_CH9 Gain Calibration for channel 9 24 31 read-only OFFS_CH9 Offset Calibration for channel 9 16 23 read-only GAIN_CH8 Gain Calibration for channel 8 8 15 read-only OFFS_CH8 Offset Calibration for channel 8 0 7 read-only FILTCOEFF0_5 Filter Coefficients ADC Channel 0-5 0x48 32 0x00000AAA 0xFFFFFFFF CH5 Filter Coefficients ADC channel 5 10 11 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH4 Filter Coefficients ADC channel 4 8 9 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH3 Filter Coefficients ADC channel 3 6 7 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH2 Filter Coefficients ADC channel 2 4 5 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH1 Filter Coefficients ADC channel 1 2 3 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH0 Filter Coefficients ADC channel 0 0 1 read-write 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 FILTCOEFF6_9 Filter Coefficents ADC Channel 6-9 0x4C 32 0x000000D5 0xFFFFFFFF CH9 Filter Coefficients ADC channel 9 6 7 read-only 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH8 Filter Coefficients ADC channel 8 4 5 read-only 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH7 Filter Coefficients ADC channel 7 2 3 read-only 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 CH6 Filter Coefficients ADC channel 6 0 1 read-only 1/2 weight of current sample 0b00 1/4 weight of current sample 0b01 1/8 weight of current sample 0b10 1/16 weight of current sample 0b11 FILT_OUT0 ADC or Filter Output Channel 0 0x50 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH0 ADC or filter output value channel 0 0 9 read-only FILT_OUT1 ADC or Filter Output Channel 1 0x54 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH1 ADC or filter output value channel 1 0 9 read-only FILT_OUT2 ADC or Filter Output Channel 2 0x58 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH2 ADC or filter output value channel 2 0 9 read-only FILT_OUT3 ADC or Filter Output Channel 3 0x5C 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH3 ADC or filter output value channel 3 0 9 read-only FILT_OUT4 ADC or Filter Output Channel 4 0x60 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH4 ADC or filter output value channel 4 0 9 read-only FILT_OUT5 ADC or Filter Output Channel 5 0x64 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH5 ADC or filter output value channel 5 0 9 read-only FILT_OUT6 ADC or Filter Output Channel 6 0x68 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH6 ADC or filter output value channel 6 0 9 read-only FILT_OUT7 ADC or Filter Output Channel 7 0x6C 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH7 ADC or filter output value channel 7 0 9 read-only FILT_OUT8 ADC or Filter Output Channel 8 0x70 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH8 ADC or filter output value channel 8 0 9 read-only FILT_OUT9 ADC or Filter Output Channel 9 0x74 32 #00000000000000000000000000000000 #11111111111111111111110000000000 OUT_CH9 ADC or filter output value channel 9 0 9 read-only FILT_UP_CTRL Upper Threshold Filter Enable 0x78 32 0x00000F3F 0xFFFFFFFF Ch5_EN Upper threshold IIR filter enable ch 5 5 5 read-write value1 disable 0b0 value2 enable 0b1 Ch4_EN Upper threshold IIR filter enable ch 4 4 4 read-write value1 disable 0b0 value2 enable 0b1 Ch3_EN Upper threshold IIR filter enable ch 3 3 3 read-write value1 disable 0b0 value2 enable 0b1 Ch2_EN Upper threshold IIR filter enable ch 2 2 2 read-write value1 disable 0b0 value2 enable 0b1 Ch1_EN Upper threshold IIR filter enable ch 1 1 1 read-write value1 disable 0b0 value2 enable 0b1 Ch0_EN Upper threshold IIR filter enable ch 0 0 0 read-write value1 disable 0b0 value2 enable 0b1 FILT_LO_CTRL Lower Threshold Filter Enable 0x7C 32 0x00000F3F 0xFFFFFFFF Ch5_EN Lower threshold IIR filter enable ch 5 5 5 read-write value1 disable 0b0 value2 enable 0b1 Ch4_EN Lower threshold IIR filter enable ch 4 4 4 read-write value1 disable 0b0 value2 enable 0b1 Ch3_EN Lower threshold IIR filter enable ch 3 3 3 read-write value1 disable 0b0 value2 enable 0b1 Ch2_EN Lower threshold IIR filter enable ch 2 2 2 read-write value1 disable 0b0 value2 enable 0b1 Ch1_EN Lower threshold IIR filter enable ch 1 1 1 read-write value1 disable 0b0 value2 enable 0b1 Ch0_EN Lower threshold IIR filter enable ch 0 0 0 read-write value1 disable 0b0 value2 enable 0b1 MMODE0_5 Overvoltage Measurement Mode of Ch 0-5 0xB0 32 0x00000000 0xFFFFFFFF Ch5 Measurement mode ch 5 10 11 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 Ch4 Measurement mode ch 4 8 9 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 Ch3 Measurement mode ch 3 6 7 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 Ch2 Measurement mode ch 2 4 5 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 Ch1 Measurement mode ch 1 2 3 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 Ch0 Measurement mode ch 0 0 1 read-write MMODE0 upper & lower voltage/limit measurement 0b00 MMODEUV undervoltage/-limit measurement 0b01 MMODEOV overvoltage/-limit measurement 0b10 TH0_3_UPPER Upper Comparator Trigger Level Channel 0-3 0x8C 32 0xA8ABDAE2 0xFFFFFFFF CH3 Channel 3 upper trigger level 24 31 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH2 Channel 2 upper trigger level 16 23 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH1 Channel 1 upper trigger level 8 15 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH0 Channel 0 upper trigger level 0 7 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF TH4_5_UPPER Upper Comparator Trigger Level Channel 4 -5 0x90 32 0x0000BC42 0xFFFFFFFF CH5 Channel 5 upper trigger level 8 15 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH4 Channel 4 upper trigger level 0 7 read-write value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF TH6_9_UPPER Upper Comparator Trigger Level Channel 6 -9 0x94 32 0xE2FAC6EE 0xFFFFFFFF CH9 Channel 9 upper trigger level 24 31 read-only value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH8 Channel 8 upper trigger level 16 23 read-only value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH7 Channel 7 upper trigger level 8 15 read-only value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CH6 Channel 6 upper trigger level 0 7 read-only value1 min. threshold value = 0 0x00 value2 max. threshold value = 255 0xFF CNT0_3_UPPER Upper Counter Trigger Level Channel 0 - 3 0xA4 32 0x12131B1A 0xFFFFFFFF HYST_UP_CH3 Channel 3 upper hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH3 Upper timer trigger threshold channel 3 24 26 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH2 Channel 2 upper hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH2 Upper timer trigger threshold channel 2 16 18 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH1 Channel 1 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH1 Upper timer trigger threshold channel 1 8 10 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH0 Channel 0 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH0 Upper timer trigger threshold channel 0 0 2 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 CNT4_5_UPPER Upper Counter Trigger Level Channel 4 & 5 0xA8 32 0x00001212 0xFFFFFFFF HYST_UP_CH5 Channel 5 upper hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH5 Upper timer trigger threshold channel 5 8 10 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH4 Channel 4 upper hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH4 Upper timer trigger threshold channel 4 0 2 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 TH0_3_LOWER Lower Comparator Trigger Level Channel 0 -3 0x80 32 0x3C2C3A42 0xFFFFFFFF CH3 Channel 3 lower trigger level 24 31 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH2 Channel 2 lower trigger level 16 23 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH1 Channel 1 lower trigger level 8 15 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH0 Channel 0 lower trigger level 0 7 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF TH4_5_LOWER Lower Comparator Trigger Level Channel 4 & 5 0x84 32 0x00009A2C 0xFFFFFFFF CH5 Channel 5 lower trigger level 8 15 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH4 Channel 4 lower trigger level 0 7 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF TH6_9_LOWER Lower Comparator Trigger Level Channel 6 -9 0x88 32 0xC7D3BBDB 0xFFFFFFFF CH9 Channel 9 lower trigger level 24 31 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH8 Channel 8 lower trigger level 16 23 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH7 Channel 7 lower trigger level 8 15 read-only value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CH6 Channel 6 lower trigger level 0 7 read-write value1 Min. threshold value 0x00 value2 Max. threshold value 0xFF CNT0_3_LOWER Lower Counter Trigger Level Channel 0 - 3 0x98 32 0x12131312 0xFFFFFFFF HYST_LO_CH3 Channel 3 lower hysteresis 27 28 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH3 Lower timer trigger threshold channel 3 24 26 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH2 Channel 2 lower hysteresis 19 20 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH2 Lower timer trigger threshold channel 2 16 18 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH1 Channel 1 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH1 Lower timer trigger threshold channel 1 8 10 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH0 Channel 0 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH0 Lower timer trigger threshold channel 0 0 2 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 CNT4_5_LOWER Lower Counter Trigger Level Channel 4 & 5 0x9C 32 0x00000A0A 0xFFFFFFFF HYST_LO_CH5 Channel 5 lower hysteresis 11 12 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH5 Lower timer trigger threshold channel 5 8 10 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH4 Channel 4 lower hysteresis 3 4 read-write HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH4 Lower timer trigger threshold channel 4 0 2 read-write value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 CNT6_9_UPPER Upper Counter Trigger Level Channel 6 -9 0xAC 32 0x1A1A1911 0xFFFFFFFF HYST_UP_CH9 Channel 9 upper hysteresis 27 28 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH9 Upper timer trigger threshold channel 9 24 26 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH8 Channel 8 upper hysteresis 19 20 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH8 Upper timer trigger threshold channel 8 16 18 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH7 Channel 7 upper hysteresis 11 12 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH7 Upper timer trigger threshold channel 7 8 10 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_UP_CH6 Channel 6 upper hysteresis 3 4 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_UP_CH6 Upper timer trigger threshold channel 6 0 2 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 CNT6_9_LOWER Lower Counter Trigger Level Channel 6 - 9 0xA0 32 0x0A0A0A0A 0xFFFFFFFF HYST_LO_CH9 Channel 9 lower hysteresis 27 28 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH9 Lower timer trigger threshold channel 9 24 26 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH8 Channel 8 lower hysteresis 19 20 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH8 Lower timer trigger threshold channel 8 16 18 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH7 Channel 7 lower hysteresis 11 12 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH7 Lower timer trigger threshold channel 7 8 10 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 HYST_LO_CH6 Channel 6 lower hysteresis 3 4 read-only HYSTOFF hysteresis switched off 0x0 HYST4 hysteresis = 4 0x1 HYST8 hysteresis = 8 0x2 HYST16 hysteresis = 16 0x3 CNT_LO_CH6 Lower timer trigger threshold channel 6 0 2 read-only value1 1 measurement 0x0 value2 2 measurements 0x1 value3 4 measurements 0x2 value4 8 measurements 0x3 value5 16 measurements 0x4 value6 32 measurements 0x5 value7 64 measurements 0x6 value8 128 measurements 0x7 ADC1 ADC1 0x40004000 0x0 0x4000 registers GLOBCTR Global Control Register 0x04 32 0x00000000 0xFFFFFFFF ANON Analog Part Switched On 8 9 read-write OFF ADC1 switched off 0b00 S_STANDBY Slow standby mode 0b01 F_STANDBY Fast standby mode 0b10 NORMAL Normal Operation 0b11 DIVA Divide Factor for the Analog internal clock: 0x00=Fadci = Fadc, 0x01=Fadci = Fadc/2, 0x02=Fadci = Fadc/3, 0x02=..., 0x3F=Fadci = Fadc/64, 0 5 read-write GLOBSTR Global Status Register 0x74 32 0x00000000 0xFFFFFFFF ANON_ST Analog Part Switched On 8 9 read-only OFF ADC1 switched off 0b00 S_STANDBY Slow standby mode 0b01 F_STANDBY Fast standby mode 0b10 NORMAL Normal Operation 0b11 CHNR Channel Number 3 5 read-only SAMPLE Sample Phase Indication 1 1 read-only IDLE ADC1 is idle or converting 0b0 ACTIVE The Input signal is being sampled 0b1 BUSY Analog Part Busy 0 0 read-only IDLE ADC1 idle 0b0 ACTIVE ADC1 Conversion is currently running 0b1 CTRL_STS ADC1 Control and Status Register 0x00 32 0x00000000 0xFFFFFFFF IN_MUX_SEL Channel for software mode 4 6 read-write CH0_EN Channel 0 enable 0b000 CH1_EN Channel 1 enable 0b001 CH2_EN Channel 2 enable 0b010 CH3_EN Channel 3 enable 0b011 CH4_EN Channel 4 enable 0b100 CH5_EN Channel 5 enable 0b101 CH6_EN Channel 6 enable 0b110 CH7_EN Channel 7 enable 0b111 EOC ADC1 End of Conversion (software mode) 3 3 read-only Pending conversion still running 0b0 Finished conversion has finished 0b1 SOC ADC1 Start of Conversion (software mode) 2 2 read-write Disable no conversion is started 0b0 Enable conversion is started 0b1 PD_N ADC1 Power Down Signal 0 0 read-write POWER DOWN ADC1 is powered down 0b0 ACTIVE ADC1 is switched on 0b1 SQ1_4 Measurement Channel Enable Bits for Cycle 1 - 4 0x18 32 0x00000000 0xFFFFFFFF SQ4 Sequence 4 channel enable 24 31 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ3 Sequence 3 channel enable 16 23 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ2 Sequence 2 channel enable 8 15 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ1 Sequence 1 channel enable 0 7 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7enable 0b10000000 SQ5_8 Measurement Channel Enable Bits for Cycle 5 - 8 0x1C 32 0x00000000 0xFFFFFFFF SQ8 Sequence 8 channel enable 24 31 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ7 Sequence 7 channel enable 16 23 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ6 Sequence 6 channel enable 8 15 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 SQ5 Sequence 5 channel enable 0 7 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 DWSEL Measurement Channel Data Width Selection 0x24 32 0x00000000 0xFFFFFFFF ch7 Data Width channel 7 7 7 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch6 Data Width channel 6 6 6 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch5 Data Width channel 5 5 5 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch4 Data Width channel 4 4 4 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch3 Data Width channel 3 3 3 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch2 Data Width channel 2 2 2 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch1 Data Width channel 1 1 1 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 ch0 Data Width channel 0 0 0 read-write 10BIT The result is 10 bits wide (bits 11 .. 2) 0b0 8BIT The result is 8 bits wide (bits 9 .. 4) 0b1 STC_0_3 Measurement Channel Sample Time Control 0 - 3 0x28 32 0x00000000 0xFFFFFFFF ch3 Sample Time Control for Channel 3 24 31 read-write ch2 Sample Time Control for Channel 2 16 23 read-write ch1 Sample Time Control for Channel 1 8 15 read-write ch0 Sample Time Control for Channel 0 0 7 read-write STC_4_7 Measurement Channel Sample Time Control 4 - 7 0x2C 32 0x00000000 0xFFFFFFFF ch7 Sample Time Control for Channel 7 24 31 read-write ch6 Sample Time Control for Channel 6 16 23 read-write ch5 Sample Time Control for Channel 5 8 15 read-write ch4 Sample Time Control for Channel 4 0 7 read-write SQ_FB Sequencer Feedback Register 0x50 32 0x00000000 0xFFFFFFFF CHx Current Channel 16 18 read-only CH0 Channel 0 0b000 CH1 Channel 1 0b001 CH2 Channel 2 0b010 CH3 Channel 3 0b011 CH4 Channel 4 0b100 CH5 Channel 5 0b101 CH6 Channel 6 0b110 CH7 Channel 7 0b111 SQx Current Active Sequence in Sequencer Mode 11 13 read-only SQ0 Sequence 0 0b000 SQ1 Sequence 1 0b001 SQ2 Sequence 2 0b010 SQ3 Sequence 3 0b011 SQ4 Sequence 4 0b100 SQ5 Sequence 5 0b101 SQ6 Sequence 6 0b110 SQ7 Sequence 7 0b111 ESM_ACTIVE ADC1 ESM active 10 10 read-only not active ESM not active 0b0 active ESM active 0b1 EIM_ACTIVE ADC1 EIM active 9 9 read-only not active EIM not active 0b0 active EIM active 0b1 SQ_RUN ADC1 Sequencer RUN 8 8 read-write SQ Stopped Postprocessing Sequencer in stopped / Software mode 0b0 SQ Running Postprocessing Sequencer is running 0b1 CHx_EIM Channel Settings Bits for Exceptional Interrupt Measurement 0x08 32 0x00000000 0xFFFFFFFF TRIG_SEL Trigger selection for exceptional interrupt measurement (EIM) 16 18 read-write NONE . 0b000 COUT63 . 0b001 GPT12_T6OUT . 0b010 GPT12_T3OUT . 0b011 T2 t2_adc_trigger 0b100 T21 t21_adc_trigger 0b101 CCU_6_INT ccu6_int 0b110 REP Repeat count for exceptional interrupt measurement (EIM) 4 6 read-write 1 Measurement 0b000 2 Measurements 0b001 4 Measurements 0b010 8 Measurements 0b011 16 Measurements 0b100 32 Measurements 0b101 64 Measurements 0b110 128 Measurements 0b111 CHx Channel set for exceptional interrupt measurement (EIM) 0 2 read-write CH0_EN Channel 0 enable 0b000 CH1_EN Channel 1 enable 0b001 CH2_EN Channel 2 enable 0b010 CH3_EN Channel 3 enable 0b011 CH4_EN Channel 4 enable 0b100 CH5_EN Channel 5 enable 0b101 CH6_EN Channel 6 enable 0b110 CH7_EN Channel 7 enable 0b111 CHx_ESM Channel Settings Bits for Exceptional Sequence Measurement 0x0C 32 0x00000000 0xFFFFFFFF TRIG_SEL Trigger selection for exceptional interrupt measurement (ESM) 16 18 read-write NONE . 0b000 COUT63 . 0b001 GPT12_T6OUT . 0b010 GPT12_T3OUT . 0b011 T2 t2_adc_trigger 0b100 T21 t21_adc_trigger 0b101 CCU_6_INT ccu6_int 0b110 ESM_0 Channel Sequence for Exceptional Sequence Measurement (ESM) 0 7 read-write CH0_EN Channel 0 enable 0b00000001 CH1_EN Channel 1 enable 0b00000010 CH2_EN Channel 2 enable 0b00000100 CH3_EN Channel 3 enable 0b00001000 CH4_EN Channel 4 enable 0b00010000 CH5_EN Channel 5 enable 0b00100000 CH6_EN Channel 6 enable 0b01000000 CH7_EN Channel 7 enable 0b10000000 RES_OUT0 ADC1 Output Channel 0 0x70 32 0x00000000 0xFFFFF000 OF0 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF0 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR0 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH0 ADC1 output reset value channel 0 0 11 read-only RES_OUT1 ADC1 Output Channel 1 0x6C 32 0x00000000 0xFFFFF000 OF1 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF1 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR1 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH1 ADC1 output result value channel 1 0 11 read-only RES_OUT2 ADC1 Output Channel 2 0x68 32 0x00000000 0xFFFFF000 OF2 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF2 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR2 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH2 ADC1 output result value channel 2 0 11 read-only RES_OUT3 ADC1 Output Channel 3 0x64 32 0x00000000 0xFFFFF000 OF3 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF3 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR3 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH3 ADC1 output result value channel 3 0 11 read-only RES_OUT4 ADC1 Output Channel 4 0x60 32 0x00000000 0xFFFFF000 OF4 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF4 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR4 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH4 ADC1 output result value channel 4 0 11 read-only RES_OUT5 ADC1 Output Channel 5 0x5C 32 0x00000000 0xFFFFF000 OF5 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF5 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR5 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH5 ADC1 output result value channel 5 0 11 read-only RES_OUT6 ADC1 Output Channel 6 0x58 32 0x00000000 0xFFFFF000 OF6 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF6 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR6 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH6 ADC1 output result value channel 6 0 11 read-only RES_OUT7 ADC1 Output Channel 7 0x54 32 0x00000000 0xFFFFF000 OF7 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF7 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR7 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH7 ADC1 output result value channel 7 0 11 read-only RES_OUT_EIM ADC1 Output Channel EIM 0x40 32 0x00000000 0xFFFFF000 OF8 Overrun Flag 18 18 read-only NO OVERRUN Result register not overwritten 0b0 OVERRUN Result register overwritten 0b1 VF8 Valid Flag 17 17 read-only NOT VALID No new valid data available 0b0 VALID Result register contains valid data and has not yet been read 0b1 WFR8 Wait for Read Mode 16 16 read-write DISABLE overwrite mode 0b0 ENABLE wait for read mode enabled 0b1 OUT_CH_EIM ADC1 output result value EIM 0 11 read-only IS ADC1 Interrupt Status Register 0x78 32 0x00000000 0xFFFFFFFF ESM_STS Exceptional Sequence Measurement (ESM) Status 9 9 read-only INACTIVE No ESM has occurred 0b0 ACTIVE ESM occurred 0b1 EIM_STS Exceptional Interrupt Measurement (EIM) Status 8 8 read-only INACTIVE No EIM occurred 0b0 ACTIVE EIM occurred 0b1 CH7_STS ADC1 Channel 7 Interrupt Status 7 7 read-only INACTIVE No Channel 7 Interrupt has occurred 0b0 ACTIVE Channel 7 Interrupt has occurred 0b1 CH6_STS ADC1 Channel 6 Interrupt Status 6 6 read-only INACTIVE No Channel 6 Interrupt has occurred 0b0 ACTIVE Channel 6 Interrupt has occurred 0b1 CH5_STS ADC1 Channel 5 Interrupt Status 5 5 read-only INACTIVE No Channel 5 Interrupt has occurred 0b0 ACTIVE Channel 5 Interrupt has occurred 0b1 CH4_STS ADC1 Channel 4 Interrupt Status 4 4 read-only INACTIVE No Channel 4 Interrupt has occurred 0b0 ACTIVE Channel 4 Interrupt has occurred 0b1 CH3_STS ADC1 Channel 3 Interrupt Status 3 3 read-only INACTIVE No Channel 3 Interrupt has occurred 0b0 ACTIVE Channel 3 Interrupt has occurred 0b1 CH2_STS ADC1 Channel 2 Interrupt Status 2 2 read-only INACTIVE No Channel 2 Interrupt has occurred 0b0 ACTIVE Channel 2 Interrupt has occurred 0b1 CH1_STS ADC1 Channel 1 Interrupt Status 1 1 read-only INACTIVE No Channel 1 Interrupt has occurred 0b0 ACTIVE Channel 1 Interrupt has occurred 0b1 CH0_STS ADC1 Channel 0 Interrupt Status 0 0 read-only INACTIVE No Channel 0 Interrupt has occurred 0b0 ACTIVE Channel 0 Interrupt has occurred 0b1 ICLR ADC1 Interrupt Status Clear Register 0x80 32 0x00000000 0xFFFFFFFF ESM_ICLR Exceptional Sequence Measurement (ESM) Status Clear 9 9 write-only INACTIVE No ESM has cleared 0b0 ACTIVE ESM cleared 0b1 EIM_ICLR Exceptional Interrupt Measurement (EIM) Status Clear 8 8 write-only INACTIVE No EIM cleared 0b0 ACTIVE EIM cleared 0b1 CH7_ICLR ADC1 Channel 7 Interrupt Status Clear 7 7 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH6_ICLR ADC1 Channel 6 Interrupt Status Clear 6 6 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH5_ICLR ADC1 Channel 5 Interrupt Status Clear 5 5 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH4_ICLR ADC1 Channel 4 Interrupt Status Clear 4 4 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH3_ICLR ADC1 Channel 3 Interrupt Status Clear 3 3 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH2_ICLR ADC1 Channel 2 Interrupt Status Clear 2 2 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH1_ICLR ADC1 Channel 1 Interrupt Status Clear 1 1 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 CH0_ICLR ADC1 Channel 0 Interrupt Status Clear 0 0 write-only INACTIVE interrupt status is not cleared 0b0 ACTIVE interrupt status is cleared 0b1 IE ADC1 Interrupt Enable Register 0x7C 32 0x00000000 0xFFFFFFFF ESM_IE Exceptional Sequence Measurement (ESM) Interrupt Enable 9 9 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 EIM_IE Exceptional Interrupt Measurement (EIM) Interrupt Enable 8 8 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH7_IE ADC1 Channel 7 Interrupt Enable 7 7 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH6_IE ADC1 Channel 6 Interrupt Enable 6 6 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH5_IE ADC1 Channel 5 Interrupt Enable 5 5 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH4_IE ADC1 Channel 4 Interrupt Enable 4 4 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH3_IE ADC1 Channel 3 Interrupt Enable 3 3 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH2_IE ADC1 Channel 2 Interrupt Enable 2 2 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH1_IE ADC1 Channel 1 Interrupt Enable 1 1 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 CH0_IE ADC1 Channel 0 Interrupt Enable 0 0 read-write DISABLED Interrupt disabled 0b0 ENABLED Interrupt enabled 0b1 BDRV BDRV 0x40034000 0x0 0x4000 registers CTRL1 H-Bridge Driver Control 1 0x00 32 0x01010101 0xFFFFFFFF HS2_OC_DIS High Side Driver Overcurrent Shutdown Disable 31 31 read-write ENABLE enable overcurrent shutdown of driver 0x0 DISABLE disable overcurrent shutdown of driver 0x1 HS2_OC_STS External High Side 2 FET Over-current Status 30 30 read-only no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown; write clear status. 0b1 HS2_SUPERR_STS High Side Driver 2 Supply Error Status 29 29 read-only NORMAL supply is in required range. 0b0 SUPPLY ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 HS2_DS_STS High Side Driver 2 Drain Source Monitoring Status in OFF-State 28 28 read-only no short on external FET no short detected. 0b0 short on external FET detected short detected; write clear status. 0b1 HS2_DCS_EN High Side Driver 2 Diagnosis Current Source Enable 27 27 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_DS_STS Flag 0x1 HS2_ON High Side Driver 2 On 26 26 read-write OFF Driver off 0b0 ON Driver on 0b1 HS2_PWM High Side Driver 2 PWM Enable 25 25 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 HS2_EN High Side Driver 2 Enable 24 24 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 HS1_OC_DIS High Side Driver Overcurrent Shutdown Disable 23 23 read-write ENABLE enable overcurrent shutdown of driver 0x0 DISABLE disable overcurrent shutdown of driver 0x1 HS1_OC_STS External High Side 1 FET Over-current Status 22 22 read-only no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown; write clear status. 0b1 HS1_SUPERR_STS High Side Driver 1 Supply Error Status 21 21 read-only NORMAL supply is in required range. 0b0 SUPPLY ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 HS1_DS_STS High Side Driver 1 Drain Source Monitoring Status in OFF-State 20 20 read-only no short on external FET no short detected. 0b0 short on external FET detected short detected; write clear status. 0b1 HS1_DCS_EN High Side Driver 1 Diagnosis Current Source Enable 19 19 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_SD_STS Flag 0x1 HS1_ON High Side Driver 1 On 18 18 read-write OFF Driver off 0b0 ON Driver on 0b1 HS1_PWM High Side Driver 1 PWM Enable 17 17 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 HS1_EN High Side Driver 1 Enable 16 16 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 LS2_OC_DIS Low Side Driver Overcurrent Shutdown Disable 15 15 read-write ENABLE enable overcurrent shutdown of driver 0x0 DISABLE disable overcurrent shutdown of driver 0x1 LS2_OC_STS External Low Side 2 FET Over-current Status 14 14 read-only no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown; write clear status. 0b1 LS2_SUPERR_STS Low Side Driver 2 Supply Error Status 13 13 read-only NORMAL supply is in required range. 0b0 SUPPLY ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 LS2_DS_STS Low Side Driver 2 Drain Source Monitoring Status in OFF-State 12 12 read-only no short on external FET no short detected. 0b0 short on external FET detected short detected; write clear status. 0b1 LS2_DCS_EN Low Side Driver 2 Diagnosis Current Source Enable 11 11 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_SD_STS Flag 0x1 LS2_ON Low Side Driver 2 On 10 10 read-write OFF Driver off 0b0 ON Driver on 0b1 LS2_PWM Low Side Driver 2 PWM Enable 9 9 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 LS2_EN Low Side Driver 2 Enable 8 8 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 LS1_OC_DIS Low Side Driver 1 Overcurrent Shutdown Disable 7 7 read-write ENABLE enable overcurrent shutdown of driver 0x0 DISABLE disable overcurrent shutdown of driver 0x1 LS1_OC_STS External Low Side 1 FET Over-current Status 6 6 read-only no Over-current no over-current Condition occurred. 0b0 Over-current over-current occurred; switch is automatically shutdown; write clear status. 0b1 LS1_SUPERR_STS Low Side Driver 1 Supply Error Status 5 5 read-only NORMAL supply is in required range. 0b0 SUPPLY ERROR detected; this flag is an OR of the VDS_x_STS and VCP_x_STS flags. 0b1 LS1_DS_STS Low Side Driver 1 Drain Source Monitoring Status in OFF-State 4 4 read-only no short on external FET no short detected. 0b0 short on external FET detected short detected; write clear status. 0b1 LS1_DCS_EN Low Side Driver 1 Diagnosis Current Source Enable 3 3 read-write DISABLE disable current source 0x0 ENABLE enable current source; short diagnosis can be performed by evaluating the LSx/HSx_SD_STS Flag 0x1 LS1_ON Low Side Driver 1 On 2 2 read-write OFF Driver off 0b0 ON Driver on 0b1 LS1_PWM Low Side Driver 1 PWM Enable 1 1 read-write DISABLE disables control by PWM input 0b0 ENABLE enables control by PWM input 0b1 LS1_EN Low Side Driver 1 Enable 0 0 read-write DISABLE Driver circuit power off 0b0 ENABLE Driver circuit power on 0b1 CTRL2 H-Bridge Driver Control 2 0x04 32 0x00000000 0xFFFFFFFF DLY_DIAG_DIRSEL Ext. power diag timer on / off select 31 31 read-write TURN OFF measure turn on time 0b0 TURN ON measure turn off time 0b1 DLY_DIAG_CHSEL Ext. power on/off timer channel select 28 30 read-write DISABLE diag timer deactivated. 0b000 HB1 LS select measure LS1 on/off delay time. 0b001 HB2 LS select measure LS2 on/off delay time. 0b010 DISABLE diag timer deactivated. 0b100 HB1 HS select measure HS1 on/off delay time. 0b101 HB2 HS select measure HS2 on/off delay time. 0b110 DLY_DIAG_STS Ext. power diag timer valid flag 27 27 read-only Diag timer invalid diag timer measurement ongoing 0b0 Diag timer valid diag timer measurement finished 0b1 DLY_DIAG_SCLR Ext. power diag timer valid flag clear 26 26 write-only Diag timer valid not clear . 0b0 Diag timer valid clear . 0b1 DLY_DIAG_TIM Ext. power on/off diag timer result register 16 25 read-only CTRL3 H-Bridge Driver Control 3 0x08 32 0x00011111 0xFFFFFFFF SEQ_ERR_STS Driver Sequence Error Status 31 31 read-only Driver Sequence ok no cross current 0b0 Driver Sequence fail HS and LS of same bridge concurrently activated, output protection activated 0b1 SEQ_ERR_SCLR Driver Sequence Error Status Clear 30 30 write-only Driver Sequence Status no clear . 0b0 Driver Sequence Status clear . 0b1 DRV_CCP_DIS Dynamic cross conduction protection Disable 26 26 read-write CCP Enable dynamic ccp is active. 0b0 CCP Disable dynamic ccp is disabled, delayed gate clamp remains active. 0b1 DRV_CCP_TIMSEL minimum cross conduction protection time setting 24 25 read-write 0.2us 200ns cross conduction protection time 0b00 0.4us 400ns cross conduction protection time 0b01 0.8us 800ns cross conduction protection time 0b10 1.6us 1.6us cross conduction protection time 0b11 DSMONVTH Voltage Threshold for Drain-Source Monitoring of external FETs 16 18 read-write 0.5_V Threshold 0 for VDS at 0.5 V 0b000 0.75_V Threshold 1 for VDS at 0.75 V 0b001 1.0_V Threshold 2 for VDS at 1.0 V 0b010 1.25_V Threshold 3 for VDS at 1.25 V 0b011 1.5_V Threshold 4 for VDS at 1.5 V 0b100 1.75_V Threshold 5 for VDS at 1.75 V 0b101 2.0_V Threshold 6 for VDS at 2.0 V 0b110 2.25_V Threshold 7 for VDS at 2.25 V 0b111 OFF_SEQ_EN Turn Off Slewrate Sequencer enable 15 15 read-write Disabled Turn Off Slewrate Sequencer disabled 0b0 Enabled Turn Off Slewrate Sequencer enabled 0b1 IDISCHARGEDIV2_N IDISCHARGE Current divide by 2 not 14 14 read-write Half Range available for charge current (max. is 150 mA) 0b0 Full Range available for charge current (max. is 300 mA) 0b1 IDISCHARGE_TRIM Trimming of the internal driver dis-charge current 8 12 read-write HiZ Slew Rate Control is inactive 0b00000 min discharge rate lowest gate charge current selected 0b00001 max discharge rate max gate charge current is selected 0b11111 ON_SEQ_EN Turn On SlewrateSequencer enable 7 7 read-write Disabled Turn On Slewrate Sequencer disabled 0b0 Enabled Turn On Slewrate Sequencer enabled 0b1 ICHARGEDIV2_N ICHARGE Current divide by 2 not 6 6 read-write Half Range available for charge current (max. is 150 mA) 0b0 Full Range available for charge current (max. is 300 mA) 0b1 ICHARGE_TRIM Trimming of the internal driver charge current 0 4 read-write HiZ Slew Rate Control is inactive 0b00000 min charge rate lowest gate discharge current selected 0b00001 max charge rate max gate discharge current is selected 0b11111 OFF_SEQ_CTRL Turn on Slewrate Sequencer Control 0x10 32 0x00000000 0xFFFFFFFF DRV_OFF_I_1 Slew rate sequencer off phase 1 current 27 31 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_OFF_t_1 Slew rate sequencer off phase 1 time 24 26 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_OFF_I_2 Slew rate sequencer off phase 2 current 19 23 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_OFF_t_2 Slew rate sequencer off phase 2 time 16 18 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_OFF_I_3 Slew rate sequencer off phase 3 current 11 15 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_OFF_t_3 Slew rate sequencer off phase 3 time 8 10 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_OFF_I_4 Slew rate sequencer off phase 4 current 3 7 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_OFF_t_4 Slew rate sequencer off phase 4 time 0 2 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 ON_SEQ_CTRL Turn off Slewrate Sequencer Control 0x14 32 0x00000000 0xFFFFFFFF DRV_ON_I_1 Slew rate sequencer on phase 1 current 27 31 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_ON_t_1 Slew rate sequencer on phase 1 time 24 26 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_ON_I_2 Slew rate sequencer on phase 2 current 19 23 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_ON_t_2 Slew rate sequencer on phase 2 time 16 18 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_ON_I_3 Slew rate sequencer on phase 3 current 11 15 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_ON_t_3 Slew rate sequencer on phase 3 time 8 10 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 DRV_ON_I_4 Slew rate sequencer on phase 4 current 3 7 read-write Disabled Slew Rate Control is disabled 0x0 Maximum maximum output discharge current 0x1f DRV_ON_t_4 Slew rate sequencer on phase 4 time 0 2 read-write 50ns 50ns phase duration 0x0 400ns 400ns phase duration 0x7 TRIM_DRVx Trimming of Driver 0x18 32 0x80000000 0xFFFFFFFF CPLOW_TFILT_SEL Filter Time for Charge Pump Voltage Low Diagnosis 24 25 read-write 4_us 4 us filter time 0b00 8_us 8 us filter time 0b01 16_us 16 us filter time 0b10 32_us 32 us filter time 0b11 HS2DRV_OCSDN_DIS High Side 2 Predriver in overcurrent situation disable 22 22 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HS1DRV_OCSDN_DIS High Side 1 Predriver in overcurrent situation disable 21 21 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HS2DRV_FDISCHG_DIS High Side 2 Predriver in overcurrent situation disable 19 19 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HS1DRV_FDISCHG_DIS High Side 1 Predriver in overcurrent situation disable 18 18 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 HSDRV_DS_TFILT_SEL Filter Time for Drain-Source Monitoring of High Side Drivers 16 17 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 LS2DRV_OCSDN_DIS Low Side 2 Predriver in overcurrent situation disable 14 14 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LS1DRV_OCSDN_DIS Low Side 1 Predriver in overcurrent situation disable 13 13 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LS2DRV_FDISCHG_DIS Low Side 2 Predriver in overcurrent situation disable 11 11 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LS1DRV_FDISCHG_DIS Low Side 1 Predriver in overcurrent situation disable 10 10 read-write Enable Predriver shutdown in overcurrent situation enable 0b0 Disable Predriver shutdown in overcurrent situation disable 0b1 LSDRV_DS_TFILT_SEL Filter Time for Drain-Source Monitoring of Low Side Drivers 8 9 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 LS_HS_BT_TFILT_SEL Blanking Time for Drain-Source Monitoring of Low / High Side Drivers 0 1 read-write 1_us 1 us filter time 0b00 2_us 2 us filter time 0b01 4_us 4 us filter time 0b10 8_us 8 us filter time 0b11 CP_CTRL_STS Charge Pump Control and Status Register 0x20 32 0x00000004 0xFFFFFFFF VTHVCP9V_TRIM Charge Pump Output Voltage 9V Trimming 26 27 read-write 7.5_V Threshold 0 0b00 8.0_V Threshold 1 0b01 8.5_V Threshold 2 0b10 9.0_V Threshold 3 0b11 VCP9V_SET Charge Pump 9 V Output Voltage Set 25 25 read-write 14V Set output voltage set to 14V 0b0 9V Set output voltage set to 9V 0b1 CPLOPWRM_EN Charge Pump Low Power Mode Enable 24 24 read-write Low Power Mode Disable low power mode inactive 0b0 Low Power Mode Enable low power mode active 0b1 VSD_UPTH_STS Driver Supply MU High Status 23 23 read-only Driver Supply Voltage ok no overvoltage detected 0b0 Driver Supply Voltage too high overvoltage on VSD Pin detected 0b1 DRVx_VSDUP_DIS Driver shutdown on VSD Upper Voltage 22 22 read-write Shutdown Enable DRVx shutdown on VSD overvoltage enable. 0b0 Shutdown Disable DRVx shutdown on VSD overvoltage disable. 0b1 VSD_LOTH_STS Driver Supply MU Low Status 21 21 read-only Driver Supply Voltage ok no undervoltage detected. 0b0 Driver Supply Voltage too low undervoltage on VSD Pin detected. 0b1 DRVx_VSDLO_DIS Driver shutdown on VSD Lower Voltage 20 20 read-write Shutdown Enable DRVx shutdown on VSD undervoltage enable. 0b0 Shutdown Disable DRVx shutdown on VSD undervoltage disable. 0b1 VCP_UPTH_STS Charge Pump MU High Status 19 19 read-only Charge Pump Output Voltage ok no overvoltage detected 0b0 Charge Pump Output Voltage too high overvoltage on charge pump output detected 0b1 DRVx_VCPUP_DIS Driver shutdown on Charge Pump Upper Voltage 18 18 read-write Shutdown Enable DRVx shutdown on Charge Pumpe overvoltage enable. 0b0 Shutdown Disable DRVx shutdown on Charge Pump overvoltage disable. 0b1 VCP_LOTH1_STS Charge Pump MU Low Status 17 17 read-only Charge Pump Output Voltage ok no undervoltage detected. 0b0 Charge Pump Output Voltage too low undervoltage on chargepump output detected. 0b1 DRVx_VCPLO_DIS Driver Shutdown on Charge Pump Low Voltage 16 16 read-write Shutdown Enable DRVx shutdown on Charge Pump undervoltage enable. 0b0 Driver Disable DRVx shutdown on Charge Pump undervoltage disable. 0b1 VCP_LOWTH2 Charge Pump Output Voltage Lower Threshold Detection Level 8 10 read-write 7.325_V Threshold 0 0b000 7.654_V Threshold 1 0b001 7.982_V Threshold 2 0b010 8.309_V Threshold 3 0b011 8.638_V Threshold 4 0b100 8.966_V Threshold 5 0b101 9.293_V Threshold 6 0b110 9.620_V Threshold 7 0b111 VCP_LOTH2_STS Charge Pump Low Status 5 5 read-only Charge Pump Output Voltage ok no undervoltage detected. 0b0 Charge Pump Output Voltage too low undervoltage on chargepump output detected. 0b1 CP_RDY_EN Bridge Driver on Charge Pump Ready Enable 2 2 read-write OFF Bridge Driver can be immediately enabled 0b0 ON Bridge Driver can only be enabled when Charge Pump is ready 0b1 CP_EN Charge Pump Enable 0 0 read-write DISABLE Charge Pump, circuit power off 0b0 ENABLE Charge Pump, circuit power on 0b1 CP_CLK_CTRL Charge Pump Clock Control Register 0x24 32 0x0000CA16 0xFFFFFFFF CPCLK_EN Charge Pump Clock Enable 15 15 read-write DISABLE Charge Pump Clock is switched off and has value of 0 0b0 ENABLE Charge Pump Clock is running 0b1 F_CP MSB of CP_CLK divider 13 14 read-write DITH_UPPER CP_CLK upper frequency boundary during dithering 8 12 read-write DITH_LOWER CP_CLK lower frequency boundary during dithering 0 4 read-write