420 lines
21 KiB
ArmAsm
420 lines
21 KiB
ArmAsm
/*********************************************************************************************************************
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* @file startup_XMC4100.S
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* @brief CMSIS Core Device Startup File for Infineon XMC4100 Device Series
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* @version V1.0
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* @date 01 June 2016
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2012-2016, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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**************************** Change history ********************************
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* V0.1,Sep, 13, 2012 ES : initial version
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* V0.2,Oct, 12, 2012 PKB: C++ support
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* V0.3,Jan, 26, 2013 PKB: Workaround for prefetch bug
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* V0.4,Jul, 29, 2013 PKB: AAPCS violation in V0.3 fixed
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* V0.5,Feb, 05, 2014 PKB: Removed redundant alignment code from copy+clear funcs
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* V0.6,May, 05, 2014 JFT: Added ram_code section
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* V0.7,Nov, 25, 2014 JFT: CPU workaround disabled. Single default handler.
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* Removed DAVE3 dependency
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* V0.8,Jan, 05, 2016 JFT: Fix .reset section attributes
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* V0.9,March,04,2016 JFT: Fix weak definition of Veneers.
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* Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND
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* V1.0,June ,01,2016 JFT: Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND
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* Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND
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* @endcond
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*/
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/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
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.macro Entry Handler
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#if defined(ENABLE_PMU_CM_001_WORKAROUND)
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.long \Handler\()_Veneer
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#else
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.long \Handler
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#endif
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.endm
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.macro Insert_ExceptionHandler Handler_Func
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.weak \Handler_Func
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.thumb_set \Handler_Func, Default_Handler
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#if defined(ENABLE_PMU_CM_001_WORKAROUND)
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.weak \Handler_Func\()_Veneer
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.type \Handler_Func\()_Veneer, %function
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\Handler_Func\()_Veneer:
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push {r0, lr}
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ldr r0, =\Handler_Func
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blx r0
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pop {r0, pc}
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.size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer
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#endif
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.endm
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/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
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/* ================== START OF VECTOR TABLE DEFINITION ====================== */
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/* Vector Table - This gets programed into VTOR register by onchip BootROM */
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.syntax unified
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.section .reset, "a", %progbits
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.align 2
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.globl __Vectors
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.type __Vectors, %object
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__Vectors:
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.long __initial_sp /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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Entry NMI_Handler /* NMI Handler */
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Entry HardFault_Handler /* Hard Fault Handler */
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Entry MemManage_Handler /* MPU Fault Handler */
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Entry BusFault_Handler /* Bus Fault Handler */
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Entry UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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Entry SVC_Handler /* SVCall Handler */
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Entry DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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Entry PendSV_Handler /* PendSV Handler */
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Entry SysTick_Handler /* SysTick Handler */
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/* Interrupt Handlers for Service Requests (SR) from XMC4100 Peripherals */
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Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
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Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
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Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
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Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
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Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
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Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
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Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
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Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
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Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
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.long 0 /* Not Available */
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Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
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Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
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Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
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Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
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Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
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Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
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Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
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Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
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Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
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Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
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Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
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Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
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Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */
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Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
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Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
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Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
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Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
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Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
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Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
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Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
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Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
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Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
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Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
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Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
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Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */
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Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */
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Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */
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Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */
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Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
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Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
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Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
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Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
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Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
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Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
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Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
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Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
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Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
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Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
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Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
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Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
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Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
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Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
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Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
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Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
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Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
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Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
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Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
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Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
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.long 0 /* Not Available */
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Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
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Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
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.long 0 /* Not Available */
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Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.long 0 /* Not Available */
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.size __Vectors, . - __Vectors
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/* ================== END OF VECTOR TABLE DEFINITION ======================= */
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/* ================== START OF VECTOR ROUTINES ============================= */
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.align 1
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.thumb
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/* Reset Handler */
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.thumb_func
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp,=__initial_sp
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#ifndef __SKIP_SYSTEM_INIT
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ldr r0, =SystemInit
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blx r0
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#endif
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/* Initialize data
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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ittt ge
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ldrge r0, [r1, r3]
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strge r0, [r2, r3]
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bge .L_loop0_0
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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/* Zero initialized data
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* Between symbol address __zero_table_start__ and __zero_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*
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* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
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*/
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#ifndef __SKIP_BSS_CLEAR
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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itt ge
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strge r0, [r1, r2]
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bge .L_loop2_0
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#endif /* __SKIP_BSS_CLEAR */
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#ifndef __SKIP_LIBC_INIT_ARRAY
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ldr r0, =__libc_init_array
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blx r0
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#endif
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ldr r0, =main
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blx r0
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.align 2
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__copy_table_start__:
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.long __data_load, __data_start, __data_size
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.long __ram_code_load, __ram_code_start, __ram_code_size
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__copy_table_end__:
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__zero_table_start__:
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.long __bss_start, __bss_size
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.long USB_RAM_start, USB_RAM_size
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__zero_table_end__:
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.pool
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.size Reset_Handler,.-Reset_Handler
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/* ======================================================================== */
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/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
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/* Default exception Handlers - Users may override this default functionality by
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defining handlers of the same name in their C code */
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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Insert_ExceptionHandler NMI_Handler
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Insert_ExceptionHandler HardFault_Handler
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Insert_ExceptionHandler MemManage_Handler
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Insert_ExceptionHandler BusFault_Handler
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Insert_ExceptionHandler UsageFault_Handler
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Insert_ExceptionHandler SVC_Handler
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Insert_ExceptionHandler DebugMon_Handler
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Insert_ExceptionHandler PendSV_Handler
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Insert_ExceptionHandler SysTick_Handler
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Insert_ExceptionHandler SCU_0_IRQHandler
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Insert_ExceptionHandler ERU0_0_IRQHandler
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Insert_ExceptionHandler ERU0_1_IRQHandler
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Insert_ExceptionHandler ERU0_2_IRQHandler
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Insert_ExceptionHandler ERU0_3_IRQHandler
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Insert_ExceptionHandler ERU1_0_IRQHandler
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Insert_ExceptionHandler ERU1_1_IRQHandler
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Insert_ExceptionHandler ERU1_2_IRQHandler
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Insert_ExceptionHandler ERU1_3_IRQHandler
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Insert_ExceptionHandler PMU0_0_IRQHandler
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Insert_ExceptionHandler VADC0_C0_0_IRQHandler
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Insert_ExceptionHandler VADC0_C0_1_IRQHandler
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Insert_ExceptionHandler VADC0_C0_2_IRQHandler
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Insert_ExceptionHandler VADC0_C0_3_IRQHandler
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Insert_ExceptionHandler VADC0_G0_0_IRQHandler
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Insert_ExceptionHandler VADC0_G0_1_IRQHandler
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Insert_ExceptionHandler VADC0_G0_2_IRQHandler
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Insert_ExceptionHandler VADC0_G0_3_IRQHandler
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Insert_ExceptionHandler VADC0_G1_0_IRQHandler
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Insert_ExceptionHandler VADC0_G1_1_IRQHandler
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Insert_ExceptionHandler VADC0_G1_2_IRQHandler
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Insert_ExceptionHandler VADC0_G1_3_IRQHandler
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Insert_ExceptionHandler DAC0_0_IRQHandler
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Insert_ExceptionHandler DAC0_1_IRQHandler
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Insert_ExceptionHandler CCU40_0_IRQHandler
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Insert_ExceptionHandler CCU40_1_IRQHandler
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Insert_ExceptionHandler CCU40_2_IRQHandler
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Insert_ExceptionHandler CCU40_3_IRQHandler
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Insert_ExceptionHandler CCU41_0_IRQHandler
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Insert_ExceptionHandler CCU41_1_IRQHandler
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Insert_ExceptionHandler CCU41_2_IRQHandler
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Insert_ExceptionHandler CCU41_3_IRQHandler
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Insert_ExceptionHandler CCU80_0_IRQHandler
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Insert_ExceptionHandler CCU80_1_IRQHandler
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Insert_ExceptionHandler CCU80_2_IRQHandler
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Insert_ExceptionHandler CCU80_3_IRQHandler
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Insert_ExceptionHandler POSIF0_0_IRQHandler
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Insert_ExceptionHandler POSIF0_1_IRQHandler
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Insert_ExceptionHandler HRPWM_0_IRQHandler
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Insert_ExceptionHandler HRPWM_1_IRQHandler
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Insert_ExceptionHandler HRPWM_2_IRQHandler
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Insert_ExceptionHandler HRPWM_3_IRQHandler
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Insert_ExceptionHandler CAN0_0_IRQHandler
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Insert_ExceptionHandler CAN0_1_IRQHandler
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Insert_ExceptionHandler CAN0_2_IRQHandler
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Insert_ExceptionHandler CAN0_3_IRQHandler
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Insert_ExceptionHandler CAN0_4_IRQHandler
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Insert_ExceptionHandler CAN0_5_IRQHandler
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Insert_ExceptionHandler CAN0_6_IRQHandler
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Insert_ExceptionHandler CAN0_7_IRQHandler
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Insert_ExceptionHandler USIC0_0_IRQHandler
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Insert_ExceptionHandler USIC0_1_IRQHandler
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Insert_ExceptionHandler USIC0_2_IRQHandler
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Insert_ExceptionHandler USIC0_3_IRQHandler
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Insert_ExceptionHandler USIC0_4_IRQHandler
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Insert_ExceptionHandler USIC0_5_IRQHandler
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Insert_ExceptionHandler USIC1_0_IRQHandler
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Insert_ExceptionHandler USIC1_1_IRQHandler
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Insert_ExceptionHandler USIC1_2_IRQHandler
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Insert_ExceptionHandler USIC1_3_IRQHandler
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Insert_ExceptionHandler USIC1_4_IRQHandler
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Insert_ExceptionHandler USIC1_5_IRQHandler
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Insert_ExceptionHandler LEDTS0_0_IRQHandler
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Insert_ExceptionHandler FCE0_0_IRQHandler
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Insert_ExceptionHandler GPDMA0_0_IRQHandler
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Insert_ExceptionHandler USB0_0_IRQHandler
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/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */
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.end
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