657 lines
22 KiB
C
657 lines
22 KiB
C
/*********************************************************************************************************************
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* @file system_XMC4200.c
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4200 Device Series
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* @version V3.1.2
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* @date 19. Jun 2017
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*
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* @cond
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*********************************************************************************************************************
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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********************** Version History ***************************************
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* V3.1.0, Dec 2014, Added options to configure clock settings
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* V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value
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* V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK
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* Added support for ARM Compiler 6 (armclang)
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******************************************************************************
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* @endcond
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*/
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/*******************************************************************************
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* HEADER FILES
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*******************************************************************************/
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#include <string.h>
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#include <XMC4200.h>
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#include "system_XMC4200.h"
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/*******************************************************************************
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* MACROS
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*******************************************************************************/
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#define CHIPID_LOC ((uint8_t *)0x20000000UL)
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#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
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#define PMU_FLASH_WS (0x2U)
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#define FPLL_FREQUENCY (80000000U)
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#define FOSCREF (2500000U)
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#define DELAY_CNT_50US_50MHZ (2500UL)
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#define DELAY_CNT_150US_50MHZ (7500UL)
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#define DELAY_CNT_50US_60MHZ (3000UL)
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#define DELAY_CNT_50US_80MHZ (4000UL)
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#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \
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SCU_PLL_PLLSTAT_PLLLV_Msk | \
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SCU_PLL_PLLSTAT_PLLSP_Msk)
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*
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// <h> Clock configuration
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*/
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/*
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// <o> External crystal frequency [Hz]
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// <8000000=> 8MHz
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// <12000000=> 12MHz
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// <16000000=> 16MHz
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// <i> Defines external crystal frequency
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// <i> Default: 8MHz
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*/
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#define OSCHP_FREQUENCY (12000000U)
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#if OSCHP_FREQUENCY == 8000000U
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#define USB_PDIV (1U)
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#define USB_NDIV (95U)
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#define USB_DIV (3U)
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#elif OSCHP_FREQUENCY == 12000000U
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#define USB_PDIV (1U)
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#define USB_NDIV (63U)
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#define USB_DIV (3U)
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#elif OSCHP_FREQUENCY == 16000000U
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#define USB_PDIV (1U)
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#define USB_NDIV (47U)
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#define USB_DIV (3U)
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#else
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#error "External crystal frequency not supported"
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#endif
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/*
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// <o> System clock (fSYS) source selection
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// <0=> Backup clock (24MHz)
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// <1=> Maximum clock frequency using PLL (80MHz)
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// <i> Default: Maximum clock frequency using PLL (80MHz)
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*/
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#define SYS_CLOCK_SRC 1
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#define SYS_CLOCK_SRC_OFI 0
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#define SYS_CLOCK_SRC_PLL 1
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/*
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// <o> Backup clock calibration mode
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// <0=> Factory calibration
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// <1=> Automatic calibration
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// <i> Default: Automatic calibration
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*/
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#define FOFI_CALIBRATION_MODE 1
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#define FOFI_CALIBRATION_MODE_FACTORY 0
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#define FOFI_CALIBRATION_MODE_AUTOMATIC 1
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/*
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// <o> Standby clock (fSTDBY) source selection
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// <0=> Internal slow oscillator (32768Hz)
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// <1=> External crystal (32768Hz)
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// <i> Default: Internal slow oscillator (32768Hz)
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*/
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#define STDBY_CLOCK_SRC 0
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#define STDBY_CLOCK_SRC_OSI 0
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#define STDBY_CLOCK_SRC_OSCULP 1
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/*
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// <o> PLL clock source selection
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// <0=> External crystal
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// <1=> External direct input
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// <2=> Internal fast oscillator
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// <i> Default: External crystal
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*/
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#define PLL_CLOCK_SRC 0
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#define PLL_CLOCK_SRC_EXT_XTAL 0
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#define PLL_CLOCK_SRC_EXT_DIRECT 1
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#define PLL_CLOCK_SRC_OFI 2
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#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
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#if OSCHP_FREQUENCY == 8000000U
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#define PLL_PDIV (1U)
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#define PLL_NDIV (79U)
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#define PLL_K2DIV (3U)
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#elif OSCHP_FREQUENCY == 12000000U
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#define PLL_PDIV (2U)
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#define PLL_NDIV (79U)
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#define PLL_K2DIV (3U)
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#elif OSCHP_FREQUENCY == 16000000U
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#define PLL_PDIV (1U)
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#define PLL_NDIV (39U)
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#define PLL_K2DIV (3U)
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#else
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#error "External crystal frequency not supported"
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#endif
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#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
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#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
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#define PLL_PDIV (5U)
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#define PLL_NDIV (79U)
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#define PLL_K2DIV (3U)
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#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
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#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
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#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
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#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
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#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
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#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
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#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
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#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
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#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
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#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
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#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
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#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
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#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
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#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
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#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
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#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
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#define EXTCLK_PIN_P0_8 (0)
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#define EXTCLK_PIN_P1_15 (1)
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/*
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// <h> Clock tree
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// <o1.0> CPU clock divider
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// <0=> fCPU = fSYS
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// <1=> fCPU = fSYS / 2
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// <o2.0> Peripheral clock divider
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// <0=> fPB = fCPU
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// <1=> fPB = fCPU / 2
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// <e.4> Enable CCU clock
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// <o3.0> CCU clock divider
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// <0=> fCCU = fCPU
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// <1=> fCCU = fCPU / 2
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// </e>
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// <e.5> Enable WDT clock
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// <o4.0..7> WDT clock divider <1-256><#-1>
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// <o4.16..17> WDT clock source <0=> fOFI
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// <1=> fSTDBY
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// <2=> fPLL
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// </e>
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// <e.0> Enable USB clock
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// <o5.16> USB clock source <0=> USBPLL
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// <1=> PLL
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// </e>
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// <e6> External Clock configuration
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// <o7.0..2> External clock source selection
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// <0=> System clock
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// <2=> USB PLL clock
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// <3=> PLL clock
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// <4=> Standby clock
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// <o7.16..24> External clock divider <1-512><#-1>
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// <i> Only valid for USB PLL and PLL clocks
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// <o8.0> External Pin Selection
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// <0=> P0.8
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// <1=> P1.15
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// </e>
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// </h>
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*/
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#define ENABLE_SCUCLK (0U)
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#define CPUCLKDIV (0U)
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#define PBCLKDIV (0U)
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#define CCUCLKDIV (0U)
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#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
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#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
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#define ENABLE_EXTCLK (0U)
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#define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
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#define EXTCLK_PIN (0U)
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#define ENABLE_PLL \
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(SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
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(((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
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(((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
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/*
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// </h>
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*/
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/*
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//-------- <<< end of configuration section >>> ------------------
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*/
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/*******************************************************************************
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* GLOBAL VARIABLES
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*******************************************************************************/
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#if defined ( __CC_ARM )
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uint32_t SystemCoreClock __attribute__((at(0x20005FC0)));
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uint8_t g_chipid[16] __attribute__((at(0x20005FC4)));
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uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4)));
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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uint32_t SystemCoreClock __attribute__((section(".ARM.__at_0x20005FC0")));
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uint8_t g_chipid[16] __attribute__((section(".ARM.__at_0x20005FC4")));
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uint32_t g_hrpwm_char_data[3] __attribute__((section(".ARM.__at_0x20005FD4")));
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#elif defined ( __ICCARM__ )
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__no_init uint32_t SystemCoreClock;
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__no_init uint8_t g_chipid[16];
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__no_init uint32_t g_hrpwm_char_data[3];
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#elif defined ( __GNUC__ )
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uint32_t SystemCoreClock __attribute__((section(".no_init")));
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uint8_t g_chipid[16] __attribute__((section(".no_init")));
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uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
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#elif defined ( __TASKING__ )
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uint32_t SystemCoreClock __at( 0x20005FC0 );
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uint8_t g_chipid[16] __at( 0x20005FC4 );
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uint32_t g_hrpwm_char_data[3] __at( 0x20005FD4 );
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#endif
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extern uint32_t __Vectors;
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/*******************************************************************************
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* LOCAL FUNCTIONS
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*******************************************************************************/
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static void delay(uint32_t cycles)
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{
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volatile uint32_t i;
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for(i = 0UL; i < cycles ;++i)
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{
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__NOP();
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}
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}
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/*******************************************************************************
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* API IMPLEMENTATION
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*******************************************************************************/
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__WEAK void SystemInit(void)
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{
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memcpy(g_chipid, CHIPID_LOC, 16);
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memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
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SystemCoreSetup();
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SystemCoreClockSetup();
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}
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__WEAK void SystemCoreSetup(void)
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{
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uint32_t temp;
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/* relocate vector table */
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__disable_irq();
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SCB->VTOR = (uint32_t)(&__Vectors);
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__DSB();
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__enable_irq();
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
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(3UL << 11*2) ); /* set CP11 Full Access */
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#endif
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/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
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SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
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temp = FLASH0->FCON;
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temp &= ~FLASH_FCON_WSPFLASH_Msk;
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temp |= PMU_FLASH_WS;
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FLASH0->FCON = temp;
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}
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__WEAK void SystemCoreClockSetup(void)
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{
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#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
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/* Enable factory calibration */
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SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
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#else
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/* Automatic calibration uses the fSTDBY */
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/* Enable HIB domain */
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/* Power up HIB domain if and only if it is currently powered down */
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if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
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{
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SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
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while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
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{
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/* wait until HIB domain is enabled */
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}
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}
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/* Remove the reset only if HIB domain were in a state of reset */
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if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
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{
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SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
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delay(DELAY_CNT_150US_50MHZ);
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}
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#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
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/* Enable OSC_ULP */
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if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
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{
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/*enable OSC_ULP*/
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while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
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{
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/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
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}
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SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
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/* Check if the clock is OK using OSCULP Oscillator Watchdog*/
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while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
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{
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/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
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}
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SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
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/* wait till clock is stable */
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do
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{
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while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
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{
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/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
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}
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SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
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delay(DELAY_CNT_50US_50MHZ);
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} while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
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}
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/* now OSC_ULP is running and can be used*/
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/* Select OSC_ULP as the clock source for RTC and STDBY*/
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while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
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{
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/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
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}
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SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
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#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
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/* Enable automatic calibration of internal fast oscillator */
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SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
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#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
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delay(DELAY_CNT_50US_50MHZ);
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#if ENABLE_PLL
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/* enable PLL */
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SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
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#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
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/* enable OSC_HP */
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if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
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{
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SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
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SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
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/* select OSC_HP clock as PLL input */
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SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
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/* restart OSC Watchdog */
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SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
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while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
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{
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/* wait till OSC_HP output frequency is usable */
|
|
}
|
|
}
|
|
#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
|
|
|
|
/* select backup clock as PLL input */
|
|
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
|
|
#endif
|
|
|
|
/* Go to bypass the Main PLL */
|
|
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
|
|
|
|
/* disconnect Oscillator from PLL */
|
|
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
|
|
|
|
/* Setup divider settings for main PLL */
|
|
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
|
(PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
|
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
|
|
|
/* Set OSCDISCDIS */
|
|
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
|
|
|
|
/* connect Oscillator to PLL */
|
|
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
|
|
|
|
/* restart PLL Lock detection */
|
|
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
|
|
|
|
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
|
{
|
|
/* wait for PLL Lock */
|
|
}
|
|
|
|
/* Disable bypass- put PLL clock back */
|
|
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
|
|
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
|
|
{
|
|
/* wait for normal mode */
|
|
}
|
|
#endif /* ENABLE_PLL */
|
|
|
|
#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
|
|
/* Switch system clock to PLL */
|
|
SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
|
|
#else
|
|
/* Switch system clock to backup clock */
|
|
SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
|
|
#endif
|
|
|
|
/* Before scaling to final frequency we need to setup the clock dividers */
|
|
SCU_CLK->PBCLKCR = PBCLKDIV;
|
|
SCU_CLK->CPUCLKCR = CPUCLKDIV;
|
|
SCU_CLK->CCUCLKCR = CCUCLKDIV;
|
|
SCU_CLK->WDTCLKCR = WDTCLKDIV;
|
|
SCU_CLK->USBCLKCR = USBCLKDIV;
|
|
|
|
#if ENABLE_PLL
|
|
/* PLL frequency stepping...*/
|
|
/* Reset OSCDISCDIS */
|
|
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
|
|
|
|
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
|
(PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
|
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
|
|
|
|
|
delay(DELAY_CNT_50US_60MHZ);
|
|
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
|
{
|
|
/* wait for PLL Lock */
|
|
}
|
|
|
|
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
|
|
(PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
|
|
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
|
|
|
|
|
|
delay(DELAY_CNT_50US_80MHZ);
|
|
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
|
|
{
|
|
/* wait for PLL Lock */
|
|
}
|
|
|
|
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
|
|
#endif /* ENABLE_PLL */
|
|
|
|
#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
|
|
/* enable USB PLL first */
|
|
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
|
|
|
|
/* USB PLL uses as clock input the OSC_HP */
|
|
/* check and if not already running enable OSC_HP */
|
|
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
|
|
{
|
|
/* check if Main PLL is switched on for OSC WDG*/
|
|
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
|
|
{
|
|
/* enable PLL first */
|
|
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
|
|
}
|
|
|
|
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
|
|
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
|
|
|
|
/* restart OSC Watchdog */
|
|
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
|
|
|
|
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
|
|
{
|
|
/* wait till OSC_HP output frequency is usable */
|
|
}
|
|
}
|
|
|
|
/* Setup USB PLL */
|
|
/* Go to bypass the USB PLL */
|
|
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
|
|
|
|
/* disconnect Oscillator from USB PLL */
|
|
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
|
|
|
|
/* Setup Divider settings for USB PLL */
|
|
SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
|
|
(USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
|
|
|
|
/* Set OSCDISCDIS */
|
|
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
|
|
|
|
/* connect Oscillator to USB PLL */
|
|
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
|
|
|
|
/* restart PLL Lock detection */
|
|
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
|
|
|
|
while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
|
|
{
|
|
/* wait for PLL Lock */
|
|
}
|
|
#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
|
|
|
|
/* Enable selected clocks */
|
|
SCU_CLK->CLKSET = ENABLE_SCUCLK;
|
|
|
|
#if ENABLE_EXTCLK == 1
|
|
/* Configure external clock */
|
|
SCU_CLK->EXTCLKCR = EXTCLKDIV;
|
|
|
|
#if EXTCLK_PIN == EXTCLK_PIN_P1_15
|
|
/* P1.15 */
|
|
PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
|
|
PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
|
|
#else
|
|
/* P0.8 */
|
|
PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
|
|
PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
|
|
PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
|
|
#endif
|
|
|
|
#endif /* ENABLE_EXTCLK == 1 */
|
|
|
|
SystemCoreClockUpdate();
|
|
}
|
|
|
|
__WEAK void SystemCoreClockUpdate(void)
|
|
{
|
|
uint32_t pdiv;
|
|
uint32_t ndiv;
|
|
uint32_t kdiv;
|
|
uint32_t temp;
|
|
|
|
if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
|
|
{
|
|
/* fPLL is clock source for fSYS */
|
|
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
|
|
{
|
|
/* PLL input clock is the backup clock (fOFI) */
|
|
temp = OFI_FREQUENCY;
|
|
}
|
|
else
|
|
{
|
|
/* PLL input clock is the high performance osicllator (fOSCHP) */
|
|
temp = OSCHP_GetFrequency();
|
|
}
|
|
|
|
/* check if PLL is locked */
|
|
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
|
|
{
|
|
/* PLL normal mode */
|
|
/* read back divider settings */
|
|
pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
|
|
ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
|
|
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
|
|
|
|
temp = (temp / (pdiv * kdiv)) * ndiv;
|
|
}
|
|
else
|
|
{
|
|
/* PLL prescalar mode */
|
|
/* read back divider settings */
|
|
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
|
|
|
|
temp = (temp / kdiv);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* fOFI is clock source for fSYS */
|
|
temp = OFI_FREQUENCY;
|
|
}
|
|
|
|
temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
|
|
temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
|
|
|
|
SystemCoreClock = temp;
|
|
}
|
|
|
|
__WEAK uint32_t OSCHP_GetFrequency(void)
|
|
{
|
|
return OSCHP_FREQUENCY;
|
|
}
|