487 lines
24 KiB
ArmAsm
487 lines
24 KiB
ArmAsm
;*******************************************************************************
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;* @file startup_XMC4700.s
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;* @brief CMSIS Core Device Startup File for
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;* Infineon XMC4700 Device Series
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;* @version V1.0
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;* @date 03 Sep 2015
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;*
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;* @cond
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;*********************************************************************************************************************
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;* Copyright (c) 2015-2016, Infineon Technologies AG
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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;* following conditions are met:
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;*
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;* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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;* disclaimer.
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;*
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;* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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;* disclaimer in the documentation and/or other materials provided with the distribution.
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;*
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;* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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;* products derived from this software without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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;* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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;* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;*
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;* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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;* Infineon Technologies AG dave@infineon.com).
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;*********************************************************************************************************************
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;*
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;************************** Version History ************************************
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; V1.00, 03 Sep 2015, First version
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;*******************************************************************************
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;* @endcond
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; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000800
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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MACRO
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Entry $Handler
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DCD $Handler
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MEND
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; 0 Top of Stack
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DCD Reset_Handler ; 1 Reset Handler
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Entry NMI_Handler ; 2 NMI Handler
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Entry HardFault_Handler ; 3 Hard Fault Handler
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Entry MemManage_Handler ; 4 MPU Fault Handler
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Entry BusFault_Handler ; 5 Bus Fault Handler
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Entry UsageFault_Handler ; 6 Usage Fault Handler
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DCD 0 ; 7 Reserved
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DCD 0 ; 8 Reserved
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DCD 0 ; 9 Reserved
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DCD 0 ; 10 Reserved
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Entry SVC_Handler ; 11 SVCall Handler
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Entry DebugMon_Handler ; 12 Debug Monitor Handler
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DCD 0 ; 13 Reserved
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Entry PendSV_Handler ; 14 PendSV Handler
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Entry SysTick_Handler ; 15 SysTick Handler
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; Interrupt Handlers for Service Requests (SR) from XMC4700 Peripherals */
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Entry SCU_0_IRQHandler ; Handler name for SR SCU_0
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Entry ERU0_0_IRQHandler ; Handler name for SR ERU0_0
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Entry ERU0_1_IRQHandler ; Handler name for SR ERU0_1
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Entry ERU0_2_IRQHandler ; Handler name for SR ERU0_2
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Entry ERU0_3_IRQHandler ; Handler name for SR ERU0_3
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Entry ERU1_0_IRQHandler ; Handler name for SR ERU1_0
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Entry ERU1_1_IRQHandler ; Handler name for SR ERU1_1
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Entry ERU1_2_IRQHandler ; Handler name for SR ERU1_2
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Entry ERU1_3_IRQHandler ; Handler name for SR ERU1_3
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DCD 0 ; Not Available
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DCD 0 ; Not Available
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DCD 0 ; Not Available
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Entry PMU0_0_IRQHandler ; Handler name for SR PMU0_0
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DCD 0 ; Not Available
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Entry VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
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Entry VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
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Entry VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
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Entry VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
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Entry VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
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Entry VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
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Entry VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
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Entry VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
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Entry VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
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Entry VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
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Entry VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
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Entry VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
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Entry VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0
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Entry VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1
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Entry VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2
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Entry VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3
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Entry VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0
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Entry VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1
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Entry VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2
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Entry VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3
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Entry DSD0_0_IRQHandler ; Handler name for SR DSD_SRM_0
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Entry DSD0_1_IRQHandler ; Handler name for SR DSD_SRM_1
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Entry DSD0_2_IRQHandler ; Handler name for SR DSD_SRM_2
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Entry DSD0_3_IRQHandler ; Handler name for SR DSD_SRM_3
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Entry DSD0_4_IRQHandler ; Handler name for SR DSD_SRA_0
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Entry DSD0_5_IRQHandler ; Handler name for SR DSD_SRA_1
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Entry DSD0_6_IRQHandler ; Handler name for SR DSD_SRA_2
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Entry DSD0_7_IRQHandler ; Handler name for SR DSD_SRA_3
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Entry DAC0_0_IRQHandler ; Handler name for SR DAC0_0
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Entry DAC0_1_IRQHandler ; Handler name for SR DAC0_1
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Entry CCU40_0_IRQHandler ; Handler name for SR CCU40_0
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Entry CCU40_1_IRQHandler ; Handler name for SR CCU40_1
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Entry CCU40_2_IRQHandler ; Handler name for SR CCU40_2
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Entry CCU40_3_IRQHandler ; Handler name for SR CCU40_3
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Entry CCU41_0_IRQHandler ; Handler name for SR CCU41_0
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Entry CCU41_1_IRQHandler ; Handler name for SR CCU41_1
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Entry CCU41_2_IRQHandler ; Handler name for SR CCU41_2
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Entry CCU41_3_IRQHandler ; Handler name for SR CCU41_3
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Entry CCU42_0_IRQHandler ; Handler name for SR CCU42_0
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Entry CCU42_1_IRQHandler ; Handler name for SR CCU42_1
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Entry CCU42_2_IRQHandler ; Handler name for SR CCU42_2
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Entry CCU42_3_IRQHandler ; Handler name for SR CCU42_3
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Entry CCU43_0_IRQHandler ; Handler name for SR CCU43_0
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Entry CCU43_1_IRQHandler ; Handler name for SR CCU43_1
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Entry CCU43_2_IRQHandler ; Handler name for SR CCU43_2
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Entry CCU43_3_IRQHandler ; Handler name for SR CCU43_3
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Entry CCU80_0_IRQHandler ; Handler name for SR CCU80_0
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Entry CCU80_1_IRQHandler ; Handler name for SR CCU80_1
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Entry CCU80_2_IRQHandler ; Handler name for SR CCU80_2
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Entry CCU80_3_IRQHandler ; Handler name for SR CCU80_3
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Entry CCU81_0_IRQHandler ; Handler name for SR CCU81_0
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Entry CCU81_1_IRQHandler ; Handler name for SR CCU81_1
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Entry CCU81_2_IRQHandler ; Handler name for SR CCU81_2
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Entry CCU81_3_IRQHandler ; Handler name for SR CCU81_3
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Entry POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
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Entry POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
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Entry POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0
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Entry POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1
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DCD 0 ; Not Available
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DCD 0 ; Not Available
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DCD 0 ; Not Available
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DCD 0 ; Not Available
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Entry CAN0_0_IRQHandler ; Handler name for SR CAN0_0
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Entry CAN0_1_IRQHandler ; Handler name for SR CAN0_1
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Entry CAN0_2_IRQHandler ; Handler name for SR CAN0_2
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Entry CAN0_3_IRQHandler ; Handler name for SR CAN0_3
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Entry CAN0_4_IRQHandler ; Handler name for SR CAN0_4
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Entry CAN0_5_IRQHandler ; Handler name for SR CAN0_5
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Entry CAN0_6_IRQHandler ; Handler name for SR CAN0_6
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Entry CAN0_7_IRQHandler ; Handler name for SR CAN0_7
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Entry USIC0_0_IRQHandler ; Handler name for SR USIC0_0
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Entry USIC0_1_IRQHandler ; Handler name for SR USIC0_1
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Entry USIC0_2_IRQHandler ; Handler name for SR USIC0_2
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Entry USIC0_3_IRQHandler ; Handler name for SR USIC0_3
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Entry USIC0_4_IRQHandler ; Handler name for SR USIC0_4
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Entry USIC0_5_IRQHandler ; Handler name for SR USIC0_5
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Entry USIC1_0_IRQHandler ; Handler name for SR USIC1_0
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Entry USIC1_1_IRQHandler ; Handler name for SR USIC1_1
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Entry USIC1_2_IRQHandler ; Handler name for SR USIC1_2
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Entry USIC1_3_IRQHandler ; Handler name for SR USIC1_3
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Entry USIC1_4_IRQHandler ; Handler name for SR USIC1_4
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Entry USIC1_5_IRQHandler ; Handler name for SR USIC1_5
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Entry USIC2_0_IRQHandler ; Handler name for SR USIC2_0
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Entry USIC2_1_IRQHandler ; Handler name for SR USIC2_1
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Entry USIC2_2_IRQHandler ; Handler name for SR USIC2_2
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Entry USIC2_3_IRQHandler ; Handler name for SR USIC2_3
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Entry USIC2_4_IRQHandler ; Handler name for SR USIC2_4
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Entry USIC2_5_IRQHandler ; Handler name for SR USIC2_5
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Entry LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
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DCD 0 ; Not Available
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Entry FCE0_0_IRQHandler ; Handler name for SR FCE0_0
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Entry GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
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Entry SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0
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Entry USB0_0_IRQHandler ; Handler name for SR USB0_0
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Entry ETH0_0_IRQHandler ; Handler name for SR ETH0_0
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DCD 0 ; Not Available
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Entry GPDMA1_0_IRQHandler ; Handler name for SR GPDMA0_1
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DCD 0 ; Not Available
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR SP, =__initial_sp
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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Default_Handler PROC
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EXPORT NMI_Handler [WEAK]
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EXPORT HardFault_Handler [WEAK]
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EXPORT MemManage_Handler [WEAK]
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EXPORT BusFault_Handler [WEAK]
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EXPORT UsageFault_Handler [WEAK]
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EXPORT SVC_Handler [WEAK]
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EXPORT DebugMon_Handler [WEAK]
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EXPORT PendSV_Handler [WEAK]
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EXPORT SysTick_Handler [WEAK]
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EXPORT SCU_0_IRQHandler [WEAK]
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EXPORT ERU0_0_IRQHandler [WEAK]
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EXPORT ERU0_1_IRQHandler [WEAK]
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EXPORT ERU0_2_IRQHandler [WEAK]
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EXPORT ERU0_3_IRQHandler [WEAK]
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EXPORT ERU1_0_IRQHandler [WEAK]
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EXPORT ERU1_1_IRQHandler [WEAK]
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EXPORT ERU1_2_IRQHandler [WEAK]
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EXPORT ERU1_3_IRQHandler [WEAK]
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EXPORT PMU0_0_IRQHandler [WEAK]
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EXPORT VADC0_C0_0_IRQHandler [WEAK]
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EXPORT VADC0_C0_1_IRQHandler [WEAK]
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EXPORT VADC0_C0_2_IRQHandler [WEAK]
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EXPORT VADC0_C0_3_IRQHandler [WEAK]
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EXPORT VADC0_G0_0_IRQHandler [WEAK]
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EXPORT VADC0_G0_1_IRQHandler [WEAK]
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EXPORT VADC0_G0_2_IRQHandler [WEAK]
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EXPORT VADC0_G0_3_IRQHandler [WEAK]
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EXPORT VADC0_G1_0_IRQHandler [WEAK]
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EXPORT VADC0_G1_1_IRQHandler [WEAK]
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EXPORT VADC0_G1_2_IRQHandler [WEAK]
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EXPORT VADC0_G1_3_IRQHandler [WEAK]
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EXPORT VADC0_G2_0_IRQHandler [WEAK]
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EXPORT VADC0_G2_1_IRQHandler [WEAK]
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EXPORT VADC0_G2_2_IRQHandler [WEAK]
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EXPORT VADC0_G2_3_IRQHandler [WEAK]
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EXPORT VADC0_G3_0_IRQHandler [WEAK]
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EXPORT VADC0_G3_1_IRQHandler [WEAK]
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EXPORT VADC0_G3_2_IRQHandler [WEAK]
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EXPORT VADC0_G3_3_IRQHandler [WEAK]
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EXPORT DSD0_0_IRQHandler [WEAK]
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EXPORT DSD0_1_IRQHandler [WEAK]
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EXPORT DSD0_2_IRQHandler [WEAK]
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EXPORT DSD0_3_IRQHandler [WEAK]
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EXPORT DSD0_4_IRQHandler [WEAK]
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EXPORT DSD0_5_IRQHandler [WEAK]
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EXPORT DSD0_6_IRQHandler [WEAK]
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EXPORT DSD0_7_IRQHandler [WEAK]
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EXPORT DAC0_0_IRQHandler [WEAK]
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EXPORT DAC0_1_IRQHandler [WEAK]
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EXPORT CCU40_0_IRQHandler [WEAK]
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EXPORT CCU40_1_IRQHandler [WEAK]
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EXPORT CCU40_2_IRQHandler [WEAK]
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EXPORT CCU40_3_IRQHandler [WEAK]
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EXPORT CCU41_0_IRQHandler [WEAK]
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EXPORT CCU41_1_IRQHandler [WEAK]
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EXPORT CCU41_2_IRQHandler [WEAK]
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EXPORT CCU41_3_IRQHandler [WEAK]
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EXPORT CCU42_0_IRQHandler [WEAK]
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EXPORT CCU42_1_IRQHandler [WEAK]
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EXPORT CCU42_2_IRQHandler [WEAK]
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EXPORT CCU42_3_IRQHandler [WEAK]
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EXPORT CCU43_0_IRQHandler [WEAK]
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EXPORT CCU43_1_IRQHandler [WEAK]
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EXPORT CCU43_2_IRQHandler [WEAK]
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EXPORT CCU43_3_IRQHandler [WEAK]
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EXPORT CCU80_0_IRQHandler [WEAK]
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EXPORT CCU80_1_IRQHandler [WEAK]
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EXPORT CCU80_2_IRQHandler [WEAK]
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EXPORT CCU80_3_IRQHandler [WEAK]
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EXPORT CCU81_0_IRQHandler [WEAK]
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EXPORT CCU81_1_IRQHandler [WEAK]
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EXPORT CCU81_2_IRQHandler [WEAK]
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EXPORT CCU81_3_IRQHandler [WEAK]
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EXPORT POSIF0_0_IRQHandler [WEAK]
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EXPORT POSIF0_1_IRQHandler [WEAK]
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EXPORT POSIF1_0_IRQHandler [WEAK]
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EXPORT POSIF1_1_IRQHandler [WEAK]
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EXPORT CAN0_0_IRQHandler [WEAK]
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EXPORT CAN0_1_IRQHandler [WEAK]
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EXPORT CAN0_2_IRQHandler [WEAK]
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EXPORT CAN0_3_IRQHandler [WEAK]
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EXPORT CAN0_4_IRQHandler [WEAK]
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EXPORT CAN0_5_IRQHandler [WEAK]
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EXPORT CAN0_6_IRQHandler [WEAK]
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EXPORT CAN0_7_IRQHandler [WEAK]
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EXPORT USIC0_0_IRQHandler [WEAK]
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EXPORT USIC0_1_IRQHandler [WEAK]
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EXPORT USIC0_2_IRQHandler [WEAK]
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EXPORT USIC0_3_IRQHandler [WEAK]
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EXPORT USIC0_4_IRQHandler [WEAK]
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EXPORT USIC0_5_IRQHandler [WEAK]
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EXPORT USIC1_0_IRQHandler [WEAK]
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EXPORT USIC1_1_IRQHandler [WEAK]
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EXPORT USIC1_2_IRQHandler [WEAK]
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EXPORT USIC1_3_IRQHandler [WEAK]
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EXPORT USIC1_4_IRQHandler [WEAK]
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EXPORT USIC1_5_IRQHandler [WEAK]
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EXPORT USIC2_0_IRQHandler [WEAK]
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EXPORT USIC2_1_IRQHandler [WEAK]
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EXPORT USIC2_2_IRQHandler [WEAK]
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EXPORT USIC2_3_IRQHandler [WEAK]
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EXPORT USIC2_4_IRQHandler [WEAK]
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EXPORT USIC2_5_IRQHandler [WEAK]
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EXPORT LEDTS0_0_IRQHandler [WEAK]
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EXPORT FCE0_0_IRQHandler [WEAK]
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EXPORT GPDMA0_0_IRQHandler [WEAK]
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EXPORT SDMMC0_0_IRQHandler [WEAK]
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EXPORT USB0_0_IRQHandler [WEAK]
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EXPORT ETH0_0_IRQHandler [WEAK]
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EXPORT GPDMA1_0_IRQHandler [WEAK]
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NMI_Handler
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HardFault_Handler
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MemManage_Handler
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BusFault_Handler
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UsageFault_Handler
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SVC_Handler
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DebugMon_Handler
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PendSV_Handler
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SysTick_Handler
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SCU_0_IRQHandler
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ERU0_0_IRQHandler
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ERU0_1_IRQHandler
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ERU0_2_IRQHandler
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ERU0_3_IRQHandler
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ERU1_0_IRQHandler
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ERU1_1_IRQHandler
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ERU1_2_IRQHandler
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ERU1_3_IRQHandler
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PMU0_0_IRQHandler
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VADC0_C0_0_IRQHandler
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VADC0_C0_1_IRQHandler
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VADC0_C0_2_IRQHandler
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VADC0_C0_3_IRQHandler
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VADC0_G0_0_IRQHandler
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VADC0_G0_1_IRQHandler
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VADC0_G0_2_IRQHandler
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VADC0_G0_3_IRQHandler
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VADC0_G1_0_IRQHandler
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VADC0_G1_1_IRQHandler
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VADC0_G1_2_IRQHandler
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VADC0_G1_3_IRQHandler
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VADC0_G2_0_IRQHandler
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VADC0_G2_1_IRQHandler
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VADC0_G2_2_IRQHandler
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VADC0_G2_3_IRQHandler
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VADC0_G3_0_IRQHandler
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VADC0_G3_1_IRQHandler
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VADC0_G3_2_IRQHandler
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VADC0_G3_3_IRQHandler
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DSD0_0_IRQHandler
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DSD0_1_IRQHandler
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DSD0_2_IRQHandler
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DSD0_3_IRQHandler
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DSD0_4_IRQHandler
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DSD0_5_IRQHandler
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DSD0_6_IRQHandler
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DSD0_7_IRQHandler
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DAC0_0_IRQHandler
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DAC0_1_IRQHandler
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CCU40_0_IRQHandler
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CCU40_1_IRQHandler
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CCU40_2_IRQHandler
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CCU40_3_IRQHandler
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CCU41_0_IRQHandler
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CCU41_1_IRQHandler
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CCU41_2_IRQHandler
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CCU41_3_IRQHandler
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CCU42_0_IRQHandler
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CCU42_1_IRQHandler
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CCU42_2_IRQHandler
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CCU42_3_IRQHandler
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CCU43_0_IRQHandler
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CCU43_1_IRQHandler
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CCU43_2_IRQHandler
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CCU43_3_IRQHandler
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CCU80_0_IRQHandler
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CCU80_1_IRQHandler
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CCU80_2_IRQHandler
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CCU80_3_IRQHandler
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CCU81_0_IRQHandler
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CCU81_1_IRQHandler
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CCU81_2_IRQHandler
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CCU81_3_IRQHandler
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POSIF0_0_IRQHandler
|
|
POSIF0_1_IRQHandler
|
|
POSIF1_0_IRQHandler
|
|
POSIF1_1_IRQHandler
|
|
CAN0_0_IRQHandler
|
|
CAN0_1_IRQHandler
|
|
CAN0_2_IRQHandler
|
|
CAN0_3_IRQHandler
|
|
CAN0_4_IRQHandler
|
|
CAN0_5_IRQHandler
|
|
CAN0_6_IRQHandler
|
|
CAN0_7_IRQHandler
|
|
USIC0_0_IRQHandler
|
|
USIC0_1_IRQHandler
|
|
USIC0_2_IRQHandler
|
|
USIC0_3_IRQHandler
|
|
USIC0_4_IRQHandler
|
|
USIC0_5_IRQHandler
|
|
USIC1_0_IRQHandler
|
|
USIC1_1_IRQHandler
|
|
USIC1_2_IRQHandler
|
|
USIC1_3_IRQHandler
|
|
USIC1_4_IRQHandler
|
|
USIC1_5_IRQHandler
|
|
USIC2_0_IRQHandler
|
|
USIC2_1_IRQHandler
|
|
USIC2_2_IRQHandler
|
|
USIC2_3_IRQHandler
|
|
USIC2_4_IRQHandler
|
|
USIC2_5_IRQHandler
|
|
LEDTS0_0_IRQHandler
|
|
FCE0_0_IRQHandler
|
|
GPDMA0_0_IRQHandler
|
|
SDMMC0_0_IRQHandler
|
|
USB0_0_IRQHandler
|
|
ETH0_0_IRQHandler
|
|
GPDMA1_0_IRQHandler
|
|
|
|
B .
|
|
|
|
ENDP
|
|
|
|
ALIGN
|
|
|
|
; User Initial Stack & Heap
|
|
|
|
IF :DEF:__MICROLIB
|
|
|
|
EXPORT __initial_sp
|
|
EXPORT __heap_base
|
|
EXPORT __heap_limit
|
|
|
|
ELSE
|
|
|
|
IMPORT __use_two_region_memory
|
|
EXPORT __user_initial_stackheap
|
|
__user_initial_stackheap
|
|
|
|
LDR R0, = Heap_Mem
|
|
LDR R1, =(Stack_Mem + Stack_Size)
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
|
LDR R3, = Stack_Mem
|
|
BX LR
|
|
|
|
ALIGN
|
|
|
|
ENDIF
|
|
|
|
|
|
END
|