290 lines
12 KiB
C
290 lines
12 KiB
C
/* =========================================================================== *
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* Copyright (c) 2014, Infineon Technologies AG *
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* All rights reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* Redistributions of source code must retain the above copyright notice, this *
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* list of conditions and the following disclaimer. Redistributions in binary *
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* form must reproduce the above copyright notice, this list of conditions and *
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* the following disclaimer in the documentation and/or other materials *
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* provided with the distribution. Neither the name of the copyright holders *
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* nor the names of its contributors may be used to endorse or promote *
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* products derived from this software without specific prior written *
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* permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, *
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR *
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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* To improve the quality of the software, users are encouraged to share *
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* modifications, enhancements or bug fixes with *
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* Infineon Technologies AG (dave@infineon.com). *
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* *
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* ========================================================================== */
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/*******************************************************************************
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** **
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** **
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** PLATFORM : Infineon XMC1000 Series **
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** **
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** AUTHOR : Application Engineering Team **
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** **
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** Project version update to v 1.0.0 Initial Version **
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** **
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** MODIFICATION DATE : Aug 01, 2014 **
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** **
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*******************************************************************************/
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/*
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* file : Main.c
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* brief : This is an example depicting usage of the low level SCU and ADC driver.
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* The SCU driver is used to set up the clocks and take ADC out of reset.
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* The ADC driver is used to configure various functional blocks of the
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* peripheral, setting up of a single entry queue and converting the lone
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* entry by means of a software generated queue conversion request.
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*/
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/*********************************************************************************************************************
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* HEADER FILES
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********************************************************************************************************************/
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#include <xmc_vadc.h>
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#include <xmc_scu.h>
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#include <xmc_gpio.h>
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/*********************************************************************************************************************
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* MACROS
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********************************************************************************************************************/
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#define RES_REG_NUMBER (0)
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#define CHANNEL_NUMBER (7U)
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#define VADC_GROUP_PTR (VADC_G1) /* P2.5 */
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#define VADC_GROUP_ID (1)
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#define IRQ_PRIORITY (10U)
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#define DELAY_COUNT (500U)
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/*********************************************************************************************************************
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* GLOBAL DATA
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********************************************************************************************************************/
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volatile uint32_t g_num_interrupts;
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volatile bool g_int_flag;
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/* Initialization data of the SCU driver */
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XMC_SCU_CLOCK_CONFIG_t g_clock_object =
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{
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XMC_SCU_CLOCK_PCLKSRC_DOUBLE_MCLK,
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XMC_SCU_CLOCK_RTCCLKSRC_DCO2,
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0U, /* fdiv = 0 */
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1U, /* idiv = 1 */
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};
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/* Initialization data of VADC Global resources */
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XMC_VADC_GLOBAL_CONFIG_t g_global_handle =
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{
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.disable_sleep_mode_control = 0,
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.class0 =
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{
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.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
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.sample_time_std_conv = 3U,
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.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
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.sampling_phase_emux_channel = 0,
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},
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.class1 =
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{
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.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
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.sample_time_std_conv = 3U,
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.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
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.sampling_phase_emux_channel = 3U
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},
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.data_reduction_control = 0,
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.wait_for_read_mode = true,
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.event_gen_enable = false,
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.boundary0 = 0,
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.boundary1 = 0
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};
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/* Initialization data of a VADC group */
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XMC_VADC_GROUP_CONFIG_t g_group_handle =
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{
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.class0 =
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{
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.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
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.sample_time_std_conv = 3U,
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.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
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.sampling_phase_emux_channel = 3U,
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},
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.class1 =
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{
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.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
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.sample_time_std_conv = 3U,
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.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
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.sampling_phase_emux_channel = 3U,
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},
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.arbitration_round_length = 0x0,
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.arbiter_mode = XMC_VADC_GROUP_ARBMODE_ALWAYS,
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.boundary0 = 0, /* Boundary-0 */
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.boundary1 = 0, /* Boundary-1 */
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.emux_config =
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{
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.emux_mode = XMC_VADC_GROUP_EMUXMODE_SWCTRL,
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.stce_usage = 0,
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.emux_coding = XMC_VADC_GROUP_EMUXCODE_BINARY,
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.starting_external_channel = 0,
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.connected_channel = 0
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}
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};
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/* Identifier of the hardware group */
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XMC_VADC_GROUP_t *g_group_identifier =VADC_GROUP_PTR;
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/* Channel configuration data */
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XMC_VADC_CHANNEL_CONFIG_t g_channel_handle =
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{
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.channel_priority = 1U,
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.input_class = XMC_VADC_CHANNEL_CONV_GROUP_CLASS1,
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.alias_channel = XMC_VADC_CHANNEL_ALIAS_DISABLED,
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.bfl = 0,
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.event_gen_criteria = XMC_VADC_CHANNEL_EVGEN_ALWAYS,
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.alternate_reference = XMC_VADC_CHANNEL_REF_INTREF,
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.result_reg_number = (uint8_t) RES_REG_NUMBER,
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.sync_conversion = false, /* Sync Feature disabled*/
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.result_alignment = XMC_VADC_RESULT_ALIGN_RIGHT,
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.use_global_result = false,
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.broken_wire_detect_channel = false,
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.broken_wire_detect = false
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};
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/* Result configuration data */
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XMC_VADC_RESULT_CONFIG_t g_result_handle =
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{
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.post_processing_mode = XMC_VADC_DMM_REDUCTION_MODE,
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.data_reduction_control = 0,
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.part_of_fifo = false, /* No FIFO */
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.wait_for_read_mode = true, /* WFS */
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.event_gen_enable = false /* No result event */
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};
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/* Queue hardware configuration data */
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XMC_VADC_QUEUE_CONFIG_t g_queue_handle =
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{
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.req_src_priority = (uint8_t)3, /* Highest Priority = 3, Lowest = 0 */
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.conv_start_mode = XMC_VADC_STARTMODE_WFS,
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.external_trigger = (bool) false, /* No external trigger */
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.trigger_signal = XMC_VADC_REQ_TR_A, /* Irrelevant */
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.trigger_edge = XMC_VADC_TRIGGER_EDGE_NONE,
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.gate_signal = XMC_VADC_REQ_GT_A, /* Irrelevant */
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.timer_mode = (bool) false, /* No timer mode */
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};
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/* Queue Entry */
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XMC_VADC_QUEUE_ENTRY_t g_queue_entry =
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{
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.channel_num = CHANNEL_NUMBER,
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.refill_needed = true, /* Refill is needed */
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.generate_interrupt = true, /* Interrupt generation is needed */
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.external_trigger = true /* External trigger is required */
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};
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XMC_GPIO_CONFIG_t gpio_input =
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{
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.mode = XMC_GPIO_MODE_INPUT_TRISTATE
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};
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/*********************************************************************************************************************
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* MAIN APPLICATION
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********************************************************************************************************************/
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/* Interrupt handler */
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void VADC0_G1_0_IRQHandler(void)
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{
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XMC_VADC_RESULT_SIZE_t result;
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/* Read the result register */
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result = XMC_VADC_GROUP_GetResult(g_group_identifier,RES_REG_NUMBER);
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/* Clear result event */
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XMC_VADC_GROUP_ClearResultEvent(g_group_identifier,RES_REG_NUMBER);
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/* Acknowledge the interrupt */
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XMC_VADC_GROUP_QueueClearReqSrcEvent(g_group_identifier);
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/* Bump up the interrupt count */
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g_num_interrupts++;
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/* Signal to the main application that the interrupt has occured */
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g_int_flag = true;
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result = result;
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}
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/* Application entry point */
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int main(void)
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{
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/* Initialize clock */
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XMC_SCU_CLOCK_Init(&g_clock_object);
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/* Initialize the VADC global registers */
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XMC_VADC_GLOBAL_Init(VADC, &g_global_handle);
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/* Configure a conversion kernel */
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XMC_VADC_GROUP_Init(g_group_identifier, &g_group_handle);
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/* Configure the queue request source of the aforesaid conversion kernel */
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XMC_VADC_GROUP_QueueInit(g_group_identifier, &g_queue_handle);
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/* Configure a channel belonging to the aforesaid conversion kernel */
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XMC_VADC_GROUP_ChannelInit(g_group_identifier,CHANNEL_NUMBER, &g_channel_handle);
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/* Configure a result resource belonging to the aforesaid conversion kernel */
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XMC_VADC_GROUP_ResultInit(g_group_identifier, RES_REG_NUMBER, &g_result_handle);
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/* Add the channel to the queue */
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XMC_VADC_GROUP_QueueInsertChannel(g_group_identifier, g_queue_entry);
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/* Set priority of NVIC node meant to e connected to Kernel Request source event */
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NVIC_SetPriority(VADC0_G1_0_IRQn, IRQ_PRIORITY);
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/* Connect RS Event to the NVIC nodes */
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XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(g_group_identifier, XMC_VADC_SR_GROUP_SR0);
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/* Enable IRQ */
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NVIC_EnableIRQ(VADC0_G1_0_IRQn);
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/* Enable the analog converters */
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XMC_VADC_GROUP_SetPowerMode(g_group_identifier, XMC_VADC_GROUP_POWERMODE_NORMAL);
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/* Perform calibration of the converter */
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XMC_VADC_GLOBAL_StartupCalibration(VADC);
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/* Start conversion by generating a conversion request (Simulating external trigger) */
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XMC_VADC_GROUP_QueueTriggerConversion(g_group_identifier);
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XMC_GPIO_Init(XMC_GPIO_PORT2,5,&gpio_input);
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while(1)
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{
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/* Spin until ISR is executed */
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while(g_int_flag == false)
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{
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}
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/* Clear the ISR flag */
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g_int_flag = false;
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/* Create an artificial delay */
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for(volatile uint32_t delay = 0; delay < DELAY_COUNT; delay++)
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{
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}
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/* Restart the conversion by regenerating a conversion request */
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XMC_VADC_GROUP_QueueTriggerConversion(g_group_identifier);
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}
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}
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