203 lines
8.6 KiB
C
203 lines
8.6 KiB
C
/* =========================================================================== *
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* Copyright (c) 2015, Infineon Technologies AG *
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* All rights reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* Redistributions of source code must retain the above copyright notice, this *
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* list of conditions and the following disclaimer. Redistributions in binary *
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* form must reproduce the above copyright notice, this list of conditions and *
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* the following disclaimer in the documentation and/or other materials *
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* provided with the distribution. Neither the name of the copyright holders *
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* nor the names of its contributors may be used to endorse or promote *
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* products derived from this software without specific prior written *
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* permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, *
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR *
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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* To improve the quality of the software, users are encouraged to share *
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* modifications, enhancements or bug fixes with *
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* Infineon Technologies AG (dave@infineon.com). *
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* *
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* ========================================================================== */
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/**
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* @file
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* @date 08 October, 2015
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* @version 1.0.0
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*
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* @brief CCU4 demo example
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*
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* Synchronous start of CC4 slices using SCU and CCU4 drivers.
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* In this example, a CCU4 Slice is operated in a Single-shot Timer mode.
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* The start of the timer is triggered by an external event mapped to EVENT-1 of the slice.
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* The external event is generated by the SCU.
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* The timer generates 2 interrupts, one each for Compare match and Period match. The
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* interrupt counters for the respective interrupts are incremented in the ISRs.
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*
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* History <br>
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*
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* Version 1.0.0 Initial <br>
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*
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*/
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/*********************************************************************************************************************
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* HEADER FILES
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********************************************************************************************************************/
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#include <xmc_ccu4.h>
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#include <xmc_scu.h>
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/*********************************************************************************************************************
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* MACROS
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********************************************************************************************************************/
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#define SLICE_PTR CCU40_CC41
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#define MODULE_PTR CCU40
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#define MODULE_NUMBER (0U)
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#define SLICE_NUMBER (1U)
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#define CAPCOM_MASK (1U) /**< Only CCU40 */
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/*********************************************************************************************************************
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* GLOBAL DATA
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********************************************************************************************************************/
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XMC_CCU4_SLICE_COMPARE_CONFIG_t g_timer_object =
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{
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.timer_mode = XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA,
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.monoshot = true,
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.shadow_xfer_clear = 0U,
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.dither_timer_period = 0U,
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.dither_duty_cycle = 0U,
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.prescaler_mode = XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL,
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.mcm_enable = 0U,
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.prescaler_initval = 0U,
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.float_limit = 0U,
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.dither_limit = 0U,
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.passive_level = XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW,
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.timer_concatenation = 0U
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};
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/* CCU Slice Capture Initialization Data */
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XMC_CCU4_SLICE_CAPTURE_CONFIG_t g_capture_object =
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{
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.fifo_enable = (uint32_t) false,
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.timer_clear_mode = (uint32_t) XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER,
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.same_event = (uint32_t) false,
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.ignore_full_flag = (uint32_t) false,
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.prescaler_mode = (uint32_t) XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL,
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.prescaler_initval = (uint32_t) 0,
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.float_limit = (uint32_t) 0,
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.timer_concatenation = (uint32_t) false
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};
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/* Interrupt counters */
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volatile uint32_t g_num_period_interrupts;
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volatile uint32_t g_num_compare_interrupts;
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volatile bool period_match;
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/*********************************************************************************************************************
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* MAIN APPLICATION
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********************************************************************************************************************/
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/* Interrupt handlers */
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void IRQ0_Handler(void)
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{
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g_num_period_interrupts++;
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XMC_CCU4_SLICE_ClearEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);
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period_match = true;
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}
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void IRQ7_Handler(void)
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{
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g_num_compare_interrupts++;
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XMC_SCU_SetCcuTriggerLow(CAPCOM_MASK);
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XMC_CCU4_SLICE_ClearEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP);
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}
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int main(void)
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{
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/* Local variable which holds configuration of Event-1 */
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XMC_CCU4_SLICE_EVENT_CONFIG_t config;
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config.duration = XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES;
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config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE;
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config.level = XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH; /* Not needed */
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config.mapped_input = 8;
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/* Ensure fCCU reaches CCU42 */
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XMC_CCU4_SetModuleClock(MODULE_PTR, XMC_CCU4_CLOCK_SCU);
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XMC_CCU4_Init(MODULE_PTR, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR);
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/* Get the slice out of idle mode */
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XMC_CCU4_EnableClock(MODULE_PTR, SLICE_NUMBER);
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/* Start the prescaler and restore clocks to slices */
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XMC_CCU4_StartPrescaler(MODULE_PTR);
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/* Initialize the Slice */
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XMC_CCU4_SLICE_CompareInit(SLICE_PTR, &g_timer_object);
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/* Enable compare match and period match events */
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XMC_CCU4_SLICE_EnableEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);
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XMC_CCU4_SLICE_EnableEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP);
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/* Connect period match event to SR0 */
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XMC_CCU4_SLICE_SetInterruptNode(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH, XMC_CCU4_SLICE_SR_ID_0);
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/* Connect compare match event to SR1 */
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XMC_CCU4_SLICE_SetInterruptNode(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP, XMC_CCU4_SLICE_SR_ID_1);
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/* Configure NVIC */
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/* Interrupt Multiplexer configuration */
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XMC_SCU_SetInterruptControl(0, XMC_SCU_IRQCTRL_CCU40_SR0_IRQ0);
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XMC_SCU_SetInterruptControl(7, XMC_SCU_IRQCTRL_CCU40_SR1_IRQ7);
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/* Set priority */
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NVIC_SetPriority(IRQ0_IRQn, 3U);
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NVIC_SetPriority(IRQ7_IRQn, 3U);
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/* Enable IRQ */
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NVIC_EnableIRQ(IRQ0_IRQn);
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NVIC_EnableIRQ(IRQ7_IRQn);
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/* Program a very large value into PR and CR */
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XMC_CCU4_SLICE_SetTimerPeriodMatch(SLICE_PTR, 65500U);
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XMC_CCU4_SLICE_SetTimerCompareMatch(SLICE_PTR, 32000U);
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/* Enable shadow transfer */
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XMC_CCU4_EnableShadowTransfer(MODULE_PTR, XMC_CCU4_SHADOW_TRANSFER_SLICE_1);
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/* Configure Event-1 and map it to Input-I */
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XMC_CCU4_SLICE_ConfigureEvent(SLICE_PTR, XMC_CCU4_SLICE_EVENT_1, &config);
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/* Map Event-1 to Start function */
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XMC_CCU4_SLICE_StartConfig(SLICE_PTR, XMC_CCU4_SLICE_EVENT_1, XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR);
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/* Generate an external start trigger */
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XMC_SCU_SetCcuTriggerHigh(CAPCOM_MASK);
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period_match = false;
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while(1U)
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{
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while(false == period_match);
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period_match = false;
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/* Generate an external start trigger */
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XMC_SCU_SetCcuTriggerHigh(CAPCOM_MASK);
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}
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}
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