252 lines
12 KiB
C
252 lines
12 KiB
C
/* =========================================================================== *
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* Copyright (c) 2014, Infineon Technologies AG *
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* All rights reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* Redistributions of source code must retain the above copyright notice, this *
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* list of conditions and the following disclaimer. Redistributions in binary *
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* form must reproduce the above copyright notice, this list of conditions and *
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* the following disclaimer in the documentation and/or other materials *
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* provided with the distribution. Neither the name of the copyright holders *
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* nor the names of its contributors may be used to endorse or promote *
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* products derived from this software without specific prior written *
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* permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, *
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR *
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
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* To improve the quality of the software, users are encouraged to share *
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* modifications, enhancements or bug fixes with *
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* Infineon Technologies AG (dave@infineon.com). *
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* *
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* ========================================================================== */
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/*******************************************************************************
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** **
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** **
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** PLATFORM : Infineon XMC4000 Series **
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** **
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** AUTHOR : Application Engineering Team **
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** **
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** Project version update to v 1.0.0 Initial Version **
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** v 1.0.1 Updated with error status check ** **
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** **
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** MODIFICATION DATE : Sep 05, 2014 **
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** **
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*******************************************************************************/
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/*
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* file : XMC4_FCE_Example1
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* brief : This example uses the XMC_FCE Low Level Driver to perform
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* CRC8, CRC16 and CRC32 operation
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*/
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#include <xmc_fce.h>
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/*********************************************************************************************************************
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* GLOBAL DATA
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********************************************************************************************************************/
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/*Data Packet 1 */
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int8_t usecase1_Data1[] = "Lorem ipsum dolor sit amet, ";
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/*Data Packet 2 */
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int8_t usecase1_Data2[] = "consectetur adipiscing elit. Donec metus eros, a";
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/*Data Packet 3 */
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int8_t usecase1_Data3[] = "ccumsan ut vestibulum id, suscipit nec augue. Aenean et lectus ut libero lacinia faucibus ut vel lectus. Pellentesque iaculis libero ac lectus blandit accumsan. Pellentesque at nulla eget metus aliquam tincidunt. Aenean cursus purus vitae lacus cursus pharetra. In hac habitasse platea dictumst. Curabitur nulla odio, porttitor eu pharetra at, pulvinar gravida velit. Aenean eu dapibus purus. Proin blandit feugiat urna, at iaculis elit accumsan ut. Pellentesque molestie pharetra erat, eget semper urna vehicula nec. Nam tristique sollicitudin diam, faucibus aliquet velit pharetra a. Duis a placerat risus. Phasellus vel diam nibh, quis elementum nisl. Phasellus lectus quam, mollis eu consequat ut, bibendum eget arcu. Nullam at felis a elit auctor suscipit eu quis ipsum. Mauris luctus, diam sit amet iaculis malesuada, urna orci convallis tellus, vitae molestie diam justo sed metus. Etiam volutpat volutpat justo, vel facilisis mi eleifend ut. Aenean egestas, sem eu vulputate lacinia, odio ligula mollis risus, a semper eros risus sed arcu. Sed feugiat augue eget erat bibendum vitae consequat purus tempus. Morbi lobortis nunc eget ligula vehicula non pharetra dolor commodo. Pellentesque ligula nibh, eleifend blandit aliquam vel, euismod non tellus. Quisque dictum laoreet feugiat. Maecenas a varius sapien. Ut semper nulla id turpis cursus ornare. Nullam quis erat et augue imperdiet pharetra nec a sem. Vestibulum ante ipsum primis in faucibus orci luctus et ultrices posuere cubilia Curae; Aenean feugiat, orci ultricies pellentesque viverra, nisl elit molestie augue, et scelerisque risus felis nec nulla. Maecenas congue arcu ac lectus bibendum at lacinia elit tristique. Cras fringilla vestibulum lectus. Praesent quis nisi turpis, sed tristique sem. Nam adipiscing posuere faucibus. In iaculis placerat semper. Curabitur in nunc quis enim vehicula aliquam quis at sapien. In hac habitasse platea orci aliquam...";
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/* FCE configuration for CRC32 operation using Kernal 0
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* Algorithm: IR Byte Wise Reflection disabled
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* : CRC 32-Bit Wise Reflection disabled
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* : XOR with final CRC enabled
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* Initial seedvalue: 0U
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*/
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XMC_FCE_t FCE_config0 =
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{
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.kernel_ptr = XMC_FCE_CRC32_0, /**< FCE Kernel Pointer */
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.fce_cfg_update.config_refin = XMC_FCE_REFIN_RESET,
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.fce_cfg_update.config_refout = XMC_FCE_REFOUT_RESET,
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.fce_cfg_update.config_xsel = XMC_FCE_INVSEL_SET,
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.seedvalue = 0U
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};
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/* FCE configuration for CRC32 operation using Kernal 1
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* Algorithm: IR Byte Wise Reflection disabled
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* : CRC 32-Bit Wise Reflection disabled
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* : XOR with final CRC disabled
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* Initial seedvalue: 0U
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*/
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XMC_FCE_t FCE_config1 =
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{
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.kernel_ptr = XMC_FCE_CRC32_1, /**< FCE Kernel Pointer */
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.fce_cfg_update.config_refin = XMC_FCE_REFIN_RESET,
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.fce_cfg_update.config_refout = XMC_FCE_REFOUT_RESET,
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.fce_cfg_update.config_xsel = XMC_FCE_INVSEL_RESET,
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.seedvalue = 0U
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};
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/* FCE configuration for CRC16 operation using Kernal 2
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* Algorithm: IR Byte Wise Reflection enabled
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* : CRC 32-Bit Wise Reflection disabled
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* : XOR with final CRC disabled
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* Initial seedvalue: 0U
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*/
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XMC_FCE_t FCE_config2 =
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{
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.kernel_ptr = XMC_FCE_CRC16, /**< FCE Kernel Pointer */
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.fce_cfg_update.config_refin = XMC_FCE_REFIN_SET,
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.fce_cfg_update.config_refout = XMC_FCE_REFOUT_RESET,
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.fce_cfg_update.config_xsel = XMC_FCE_INVSEL_RESET,
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.seedvalue = 0U
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};
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/* FCE configuration for CRC8 operation using Kernal 3
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* Algorithm: IR Byte Wise Reflection disabled
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* : CRC 32-Bit Wise Reflection disabled
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* : XOR with final CRC disabled
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* Initial seedvalue: 0U
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*/
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XMC_FCE_t FCE_config3 =
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{
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.kernel_ptr = XMC_FCE_CRC8, /**< FCE Kernel Pointer */
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.fce_cfg_update.config_refin = XMC_FCE_REFIN_RESET,
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.fce_cfg_update.config_refout = XMC_FCE_REFOUT_RESET,
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.fce_cfg_update.config_xsel = XMC_FCE_INVSEL_RESET,
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.seedvalue = 0U
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};
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/*********************************************************************************************************************
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* MAIN APPLICATION
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********************************************************************************************************************/
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int main(void)
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{
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uint32_t Read_CRCResult32;
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uint16_t Read_CRCResult16;
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uint8_t Read_CRCResult8;
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uint32_t temp_length;
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uint32_t temp_mismatch;
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uint32_t CRC_result;
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bool flagstatus;
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XMC_FCE_STATUS_t fce_status;
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/* Enable FCE module */
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XMC_FCE_Enable();
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/* Initialize the FCE Configuration */
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XMC_FCE_Init(&FCE_config0);
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XMC_FCE_Init(&FCE_config1);
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XMC_FCE_Init(&FCE_config2);
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XMC_FCE_Init(&FCE_config3);
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/* Initialize error counter*/
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temp_mismatch = 0;
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/* Step 1: Performs a CRC32 check using Kernel 0 on Usecase1_Data1
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* Seed value is set to 0.
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* => CRC = 0xbb8d49a6, RES = 0x4472b659
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*/
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XMC_FCE_InitializeSeedValue(&FCE_config0, 0);
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fce_status = XMC_FCE_CalculateCRC32(&FCE_config0, (uint32_t *) usecase1_Data1, strlen((const char *)(usecase1_Data1)), &Read_CRCResult32);
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while(fce_status== XMC_FCE_STATUS_ERROR)
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{
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/* endless loop if error */
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}
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XMC_FCE_GetCRCResult(&FCE_config0, &CRC_result);
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/* Step 2: Performs a CRC32 check using Kernel 1 on Usecase1_Data1
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* Seed value is set to 0. CRC check comparison is enabled
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* CRC checksum is using result from earlier CRC check
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* No CRC mismatch found.
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* CRC = 0xbb8d49a6, RES = 0xbb8d49a6
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*/
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XMC_FCE_EnableOperation(&FCE_config1,XMC_FCE_CFG_CONFIG_CCE);
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/* Used in 32bit FCE, therefore temp_length is divided by 4*/
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temp_length = (strlen((char *)(usecase1_Data1)))>>2;
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XMC_FCE_UpdateCRCCheck(&FCE_config1, Read_CRCResult32);
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XMC_FCE_UpdateLength(&FCE_config1, temp_length);
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XMC_FCE_InitializeSeedValue(&FCE_config1, 0);
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fce_status = XMC_FCE_CalculateCRC32(&FCE_config1, (uint32_t *) usecase1_Data1, strlen((const char *)(usecase1_Data1)), &Read_CRCResult32);
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while(fce_status== XMC_FCE_STATUS_ERROR)
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{
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/* endless loop if error */
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}
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XMC_FCE_GetCRCResult(&FCE_config1, &CRC_result);
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if(XMC_FCE_GetEventStatus(&FCE_config1,XMC_FCE_STS_MISMATCH_CRC))
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{
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temp_mismatch += 1U;
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}
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/* Step 3: Performs a CRC32 check using Kernel 1 on Usecase1_Data2
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* Seed value is set to 0. CRC check comparison is enabled
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* CRC checksum is using result from earlier CRC check
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* CRC mismatch found and Length Error found.
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* CRC = 0x8f2d7440, RES = 0x8f2d7440
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*/
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XMC_FCE_InitializeSeedValue(&FCE_config1, 0);
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XMC_FCE_UpdateLength(&FCE_config1, temp_length);
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fce_status = XMC_FCE_CalculateCRC32(&FCE_config1, (uint32_t *) usecase1_Data2, strlen((const char *)(usecase1_Data2)), &Read_CRCResult32);
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while(fce_status== XMC_FCE_STATUS_ERROR)
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{
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/* endless loop if error */
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}
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XMC_FCE_GetCRCResult(&FCE_config1, &CRC_result);
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if (XMC_FCE_GetEventStatus(&FCE_config1,XMC_FCE_STS_MISMATCH_CRC))
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{
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temp_mismatch += 2U;
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}
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/* Step 4: Performs a CRC16 check using Kernel 2 on Usecase1_Data3
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* Seed value is set to 0.
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* CRC = 0x191e, RES = 0x191e
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*/
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XMC_FCE_InitializeSeedValue(&FCE_config2, 0);
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fce_status = XMC_FCE_CalculateCRC16(&FCE_config2, (uint16_t *) usecase1_Data3, strlen((const char *)(usecase1_Data3)), &Read_CRCResult16);
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while(fce_status== XMC_FCE_STATUS_ERROR)
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{
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/* endless loop if error */
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}
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XMC_FCE_GetCRCResult(&FCE_config2, &CRC_result);
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/* Step 5: Performs a CRC8 check using Kernel 3 on Usecase1_Data4
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* Seed value is set to 0. CRC = 0xbe, RES = 0xbe
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*/
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XMC_FCE_InitializeSeedValue(&FCE_config3, 0);
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fce_status = XMC_FCE_CalculateCRC8(&FCE_config3, (uint8_t *)usecase1_Data3, strlen((const char *)(usecase1_Data3)), &Read_CRCResult8);
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while(fce_status== XMC_FCE_STATUS_ERROR)
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{
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/* endless loop if error */
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}
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XMC_FCE_GetCRCResult(&FCE_config3, &CRC_result);
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/* Step 6: Trigger a mismatch flag
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*/
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flagstatus = XMC_FCE_GetEventStatus(&FCE_config3, XMC_FCE_STS_MISMATCH_CRC);
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while(flagstatus)
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{
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/* endless loop if mismatch flag is triggered */
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}
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XMC_FCE_TriggerMismatch(&FCE_config3, XMC_FCE_CTR_MISMATCH_CRC);
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flagstatus = XMC_FCE_GetEventStatus(&FCE_config3, XMC_FCE_STS_MISMATCH_CRC);
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while(flagstatus)
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{
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/* endless loop if mismatch flag is triggered */
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}
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while(1)
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{
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}
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}
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