894 lines
79 KiB
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894 lines
79 KiB
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 <span id="projectnumber">Version 2.05</span>
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<div id="projectbrief">Peripheral Interface for Middleware and Application Code</div>
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<a href="#nested-classes">Data Structures</a> |
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
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Data Structures</h2></td></tr>
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<tr class="memitem:structARM__NAND__ECC__INFO"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">ARM_NAND_ECC_INFO</a></td></tr>
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<tr class="memdesc:structARM__NAND__ECC__INFO"><td class="mdescLeft"> </td><td class="mdescRight">NAND ECC (Error Correction Code) Information. <a href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">More...</a><br/></td></tr>
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<tr class="separator:structARM__NAND__ECC__INFO"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structARM__NAND__STATUS"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__STATUS">ARM_NAND_STATUS</a></td></tr>
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<tr class="memdesc:structARM__NAND__STATUS"><td class="mdescLeft"> </td><td class="mdescRight">NAND Status. <a href="group__nand__interface__gr.html#structARM__NAND__STATUS">More...</a><br/></td></tr>
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<tr class="separator:structARM__NAND__STATUS"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structARM__NAND__CAPABILITIES"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">ARM_NAND_CAPABILITIES</a></td></tr>
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<tr class="memdesc:structARM__NAND__CAPABILITIES"><td class="mdescLeft"> </td><td class="mdescRight">NAND Driver Capabilities. <a href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">More...</a><br/></td></tr>
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<tr class="separator:structARM__NAND__CAPABILITIES"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:structARM__DRIVER__NAND"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#structARM__DRIVER__NAND">ARM_DRIVER_NAND</a></td></tr>
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<tr class="memdesc:structARM__DRIVER__NAND"><td class="mdescLeft"> </td><td class="mdescRight">Access structure of the NAND Driver. <a href="group__nand__interface__gr.html#structARM__DRIVER__NAND">More...</a><br/></td></tr>
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<tr class="separator:structARM__DRIVER__NAND"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a121ff96c31275cef4bb7e86007665e1c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a121ff96c31275cef4bb7e86007665e1c">ARM_NAND_API_VERSION</a>   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td></tr>
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<tr class="separator:a121ff96c31275cef4bb7e86007665e1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a848a27ec9ebf0a13a82a1d9760f39d90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a848a27ec9ebf0a13a82a1d9760f39d90">ARM_NAND_POWER_VCC_Pos</a>   0</td></tr>
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<tr class="separator:a848a27ec9ebf0a13a82a1d9760f39d90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad898ef5cd4ffe3b6b09d69e224aa0912"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad898ef5cd4ffe3b6b09d69e224aa0912">ARM_NAND_POWER_VCC_Msk</a>   (0x07UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
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<tr class="separator:ad898ef5cd4ffe3b6b09d69e224aa0912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a323c320a6195b78c2c79f5c6e85f02e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a323c320a6195b78c2c79f5c6e85f02e1">ARM_NAND_POWER_VCC_OFF</a>   (0x01UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
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<tr class="memdesc:a323c320a6195b78c2c79f5c6e85f02e1"><td class="mdescLeft"> </td><td class="mdescRight">VCC Power off. <a href="#a323c320a6195b78c2c79f5c6e85f02e1">More...</a><br/></td></tr>
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<tr class="separator:a323c320a6195b78c2c79f5c6e85f02e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad15355d67bc239ff49cceac69c2024b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad15355d67bc239ff49cceac69c2024b3">ARM_NAND_POWER_VCC_3V3</a>   (0x02UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
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<tr class="memdesc:ad15355d67bc239ff49cceac69c2024b3"><td class="mdescLeft"> </td><td class="mdescRight">VCC = 3.3V. <a href="#ad15355d67bc239ff49cceac69c2024b3">More...</a><br/></td></tr>
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<tr class="separator:ad15355d67bc239ff49cceac69c2024b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7b9d5a71125b745caba5c1d7aff6385"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa7b9d5a71125b745caba5c1d7aff6385">ARM_NAND_POWER_VCC_1V8</a>   (0x03UL << ARM_NAND_POWER_VCC_Pos)</td></tr>
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<tr class="memdesc:aa7b9d5a71125b745caba5c1d7aff6385"><td class="mdescLeft"> </td><td class="mdescRight">VCC = 1.8V. <a href="#aa7b9d5a71125b745caba5c1d7aff6385">More...</a><br/></td></tr>
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<tr class="separator:aa7b9d5a71125b745caba5c1d7aff6385"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac38023b94cd8a68295d48a1019a386e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac38023b94cd8a68295d48a1019a386e0">ARM_NAND_POWER_VCCQ_Pos</a>   3</td></tr>
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<tr class="separator:ac38023b94cd8a68295d48a1019a386e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a453227301d7c08d09b22dc8afafbe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a7a453227301d7c08d09b22dc8afafbe7">ARM_NAND_POWER_VCCQ_Msk</a>   (0x07UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
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<tr class="separator:a7a453227301d7c08d09b22dc8afafbe7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca7679e8269ee986559f4218816937c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aca7679e8269ee986559f4218816937c3">ARM_NAND_POWER_VCCQ_OFF</a>   (0x01UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
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<tr class="memdesc:aca7679e8269ee986559f4218816937c3"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ I/O Power off. <a href="#aca7679e8269ee986559f4218816937c3">More...</a><br/></td></tr>
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<tr class="separator:aca7679e8269ee986559f4218816937c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6d5a8a33a0fdaaff2e57e1ac53c984c2">ARM_NAND_POWER_VCCQ_3V3</a>   (0x02UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
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<tr class="memdesc:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ = 3.3V. <a href="#a6d5a8a33a0fdaaff2e57e1ac53c984c2">More...</a><br/></td></tr>
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<tr class="separator:a6d5a8a33a0fdaaff2e57e1ac53c984c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a653d9b4d7bee173beb49d8fec0469476"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a653d9b4d7bee173beb49d8fec0469476">ARM_NAND_POWER_VCCQ_1V8</a>   (0x03UL << ARM_NAND_POWER_VCCQ_Pos)</td></tr>
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<tr class="memdesc:a653d9b4d7bee173beb49d8fec0469476"><td class="mdescLeft"> </td><td class="mdescRight">VCCQ = 1.8V. <a href="#a653d9b4d7bee173beb49d8fec0469476">More...</a><br/></td></tr>
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<tr class="separator:a653d9b4d7bee173beb49d8fec0469476"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2d278901881ffc73d3e0b48717b22f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae2d278901881ffc73d3e0b48717b22f0">ARM_NAND_POWER_VPP_OFF</a>   (1UL << 6)</td></tr>
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<tr class="memdesc:ae2d278901881ffc73d3e0b48717b22f0"><td class="mdescLeft"> </td><td class="mdescRight">VPP off. <a href="#ae2d278901881ffc73d3e0b48717b22f0">More...</a><br/></td></tr>
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<tr class="separator:ae2d278901881ffc73d3e0b48717b22f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aeb0d50e30bbcd8ab59c3b78db634aad5">ARM_NAND_POWER_VPP_ON</a>   (1Ul << 7)</td></tr>
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<tr class="memdesc:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="mdescLeft"> </td><td class="mdescRight">VPP on. <a href="#aeb0d50e30bbcd8ab59c3b78db634aad5">More...</a><br/></td></tr>
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<tr class="separator:aeb0d50e30bbcd8ab59c3b78db634aad5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a>   (0x01)</td></tr>
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<tr class="memdesc:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Mode as specified with arg. <a href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">More...</a><br/></td></tr>
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<tr class="separator:ga9b063c3078e86b50d4aa892518b2e2d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d3356f5b47871c465ae7136a2c533f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga2d3356f5b47871c465ae7136a2c533f4">ARM_NAND_BUS_DATA_WIDTH</a>   (0x02)</td></tr>
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<tr class="memdesc:ga2d3356f5b47871c465ae7136a2c533f4"><td class="mdescLeft"> </td><td class="mdescRight">Set Bus Data Width as specified with arg. <a href="group__nand__control__codes.html#ga2d3356f5b47871c465ae7136a2c533f4">More...</a><br/></td></tr>
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<tr class="separator:ga2d3356f5b47871c465ae7136a2c533f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5d1d46198404fe115b013bdae7af2a2f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga5d1d46198404fe115b013bdae7af2a2f">ARM_NAND_DRIVER_STRENGTH</a>   (0x03)</td></tr>
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<tr class="memdesc:ga5d1d46198404fe115b013bdae7af2a2f"><td class="mdescLeft"> </td><td class="mdescRight">Set Driver Strength as specified with arg. <a href="group__nand__control__codes.html#ga5d1d46198404fe115b013bdae7af2a2f">More...</a><br/></td></tr>
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<tr class="separator:ga5d1d46198404fe115b013bdae7af2a2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bffc9f341e704ee0e845d86a2989921"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#ga1bffc9f341e704ee0e845d86a2989921">ARM_NAND_DEVICE_READY_EVENT</a>   (0x04)</td></tr>
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<tr class="memdesc:ga1bffc9f341e704ee0e845d86a2989921"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">ARM_NAND_EVENT_DEVICE_READY</a>; arg: 0=disabled (default), 1=enabled. <a href="group__nand__control__codes.html#ga1bffc9f341e704ee0e845d86a2989921">More...</a><br/></td></tr>
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<tr class="separator:ga1bffc9f341e704ee0e845d86a2989921"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab6dea1b565aeb53e360876a4e50783c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__control__codes.html#gaab6dea1b565aeb53e360876a4e50783c">ARM_NAND_DRIVER_READY_EVENT</a>   (0x05)</td></tr>
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<tr class="memdesc:gaab6dea1b565aeb53e360876a4e50783c"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">ARM_NAND_EVENT_DRIVER_READY</a>; arg: 0=disabled (default), 1=enabled. <a href="group__nand__control__codes.html#gaab6dea1b565aeb53e360876a4e50783c">More...</a><br/></td></tr>
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<tr class="separator:gaab6dea1b565aeb53e360876a4e50783c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a372fc9b9cc1315046ceaffd6fd99e12c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>   4</td></tr>
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<tr class="separator:a372fc9b9cc1315046ceaffd6fd99e12c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea213eb1ba9c67beb6216a630d81b91f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aea213eb1ba9c67beb6216a630d81b91f">ARM_NAND_BUS_INTERFACE_Msk</a>   (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
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<tr class="separator:aea213eb1ba9c67beb6216a630d81b91f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">ARM_NAND_BUS_SDR</a>   (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
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<tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default) <a href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">More...</a><br/></td></tr>
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<tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>   (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
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<tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate) <a href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">More...</a><br/></td></tr>
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<tr class="separator:ga82b8261b3d0d85881535adada318a7df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga13c102201d6021db184a2f068656c518"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">ARM_NAND_BUS_DDR2</a>   (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
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<tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft"> </td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate) <a href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">More...</a><br/></td></tr>
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<tr class="separator:ga13c102201d6021db184a2f068656c518"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acc98e42d23656734c7f9a8a5421842d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>   0</td></tr>
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<tr class="separator:acc98e42d23656734c7f9a8a5421842d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57f6c319265b00878661656103abe660"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a57f6c319265b00878661656103abe660">ARM_NAND_BUS_TIMING_MODE_Msk</a>   (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="separator:a57f6c319265b00878661656103abe660"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga971e574ac412bbba445055e9afc384ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">ARM_NAND_BUS_TIMING_MODE_0</a>   (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 0 (default) <a href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">More...</a><br/></td></tr>
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<tr class="separator:ga971e574ac412bbba445055e9afc384ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga475a339e929eca46e11bc8a7b330aa45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">ARM_NAND_BUS_TIMING_MODE_1</a>   (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 1. <a href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">More...</a><br/></td></tr>
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<tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>   (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 2. <a href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">More...</a><br/></td></tr>
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<tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>   (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 3. <a href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">More...</a><br/></td></tr>
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<tr class="separator:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga709d51a5215cd23ce2d85aec57141456"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">ARM_NAND_BUS_TIMING_MODE_4</a>   (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 4 (SDR EDO capable) <a href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">More...</a><br/></td></tr>
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<tr class="separator:ga709d51a5215cd23ce2d85aec57141456"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>   (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 5 (SDR EDO capable) <a href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">More...</a><br/></td></tr>
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<tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>   (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only) <a href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">More...</a><br/></td></tr>
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<tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>   (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
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<tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft"> </td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only) <a href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">More...</a><br/></td></tr>
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<tr class="separator:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a57b282c0818c87b79ea4f11d03cc4f3c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>   8</td></tr>
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<tr class="separator:a57b282c0818c87b79ea4f11d03cc4f3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad30dfdbdc50a7ff72a5bb173c5f549dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad30dfdbdc50a7ff72a5bb173c5f549dc">ARM_NAND_BUS_DDR2_DO_WCYC_Msk</a>   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
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<tr class="separator:ad30dfdbdc50a7ff72a5bb173c5f549dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">ARM_NAND_BUS_DDR2_DO_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default) <a href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">More...</a><br/></td></tr>
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<tr class="separator:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">ARM_NAND_BUS_DDR2_DO_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1. <a href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">More...</a><br/></td></tr>
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<tr class="separator:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">ARM_NAND_BUS_DDR2_DO_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2. <a href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">More...</a><br/></td></tr>
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<tr class="separator:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">ARM_NAND_BUS_DDR2_DO_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4. <a href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">More...</a><br/></td></tr>
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<tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa80b898cdf665aa14ff0e181e4ff31f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>   12</td></tr>
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<tr class="separator:aa80b898cdf665aa14ff0e181e4ff31f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9ab38101de68a1bc186f5687f63f7c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ad9ab38101de68a1bc186f5687f63f7c3">ARM_NAND_BUS_DDR2_DI_WCYC_Msk</a>   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
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<tr class="separator:ad9ab38101de68a1bc186f5687f63f7c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">ARM_NAND_BUS_DDR2_DI_WCYC_0</a>   (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
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<tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default) <a href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">More...</a><br/></td></tr>
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<tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>   (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1. <a href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">More...</a><br/></td></tr>
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<tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>   (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
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<tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2. <a href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">More...</a><br/></td></tr>
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<tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>   (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
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<tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4. <a href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">More...</a><br/></td></tr>
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<tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>   (1UL << 16)</td></tr>
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<tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable external VREFQ as reference. <a href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">More...</a><br/></td></tr>
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<tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>   (1UL << 17)</td></tr>
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<tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal. <a href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">More...</a><br/></td></tr>
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<tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>   (1UL << 18)</td></tr>
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<tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft"> </td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal. <a href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">More...</a><br/></td></tr>
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<tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga578051cc193ae0b7125aec8007071d21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__data__bus__width__codes.html#ga578051cc193ae0b7125aec8007071d21">ARM_NAND_BUS_DATA_WIDTH_8</a>   (0x00)</td></tr>
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<tr class="memdesc:ga578051cc193ae0b7125aec8007071d21"><td class="mdescLeft"> </td><td class="mdescRight">Bus Data Width: 8 bit (default) <a href="group__nand__data__bus__width__codes.html#ga578051cc193ae0b7125aec8007071d21">More...</a><br/></td></tr>
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<tr class="separator:ga578051cc193ae0b7125aec8007071d21"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__data__bus__width__codes.html#ga49e0e3a946a4d9f26dbd5b32ccc3b2f3">ARM_NAND_BUS_DATA_WIDTH_16</a>   (0x01)</td></tr>
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<tr class="memdesc:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="mdescLeft"> </td><td class="mdescRight">Bus Data Width: 16 bit. <a href="group__nand__data__bus__width__codes.html#ga49e0e3a946a4d9f26dbd5b32ccc3b2f3">More...</a><br/></td></tr>
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<tr class="separator:ga49e0e3a946a4d9f26dbd5b32ccc3b2f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga942e20df12022f3bbd0e9a558ec1c7a0">ARM_NAND_DRIVER_STRENGTH_18</a>   (0x00)</td></tr>
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<tr class="memdesc:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 2.0x = 18 Ohms. <a href="group__nand__driver__strength__codes.html#ga942e20df12022f3bbd0e9a558ec1c7a0">More...</a><br/></td></tr>
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<tr class="separator:ga942e20df12022f3bbd0e9a558ec1c7a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga17188e039f5f87c581033327399a057d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga17188e039f5f87c581033327399a057d">ARM_NAND_DRIVER_STRENGTH_25</a>   (0x01)</td></tr>
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<tr class="memdesc:ga17188e039f5f87c581033327399a057d"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 1.4x = 25 Ohms. <a href="group__nand__driver__strength__codes.html#ga17188e039f5f87c581033327399a057d">More...</a><br/></td></tr>
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<tr class="separator:ga17188e039f5f87c581033327399a057d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga33562a66a5bf328eea82b2f1893a7874"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#ga33562a66a5bf328eea82b2f1893a7874">ARM_NAND_DRIVER_STRENGTH_35</a>   (0x02)</td></tr>
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<tr class="memdesc:ga33562a66a5bf328eea82b2f1893a7874"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 1.0x = 35 Ohms (default) <a href="group__nand__driver__strength__codes.html#ga33562a66a5bf328eea82b2f1893a7874">More...</a><br/></td></tr>
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<tr class="separator:ga33562a66a5bf328eea82b2f1893a7874"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa502e2c995447037d266f939faa43223"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__strength__codes.html#gaa502e2c995447037d266f939faa43223">ARM_NAND_DRIVER_STRENGTH_50</a>   (0x03)</td></tr>
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<tr class="memdesc:gaa502e2c995447037d266f939faa43223"><td class="mdescLeft"> </td><td class="mdescRight">Driver Strength 0.7x = 50 Ohms. <a href="group__nand__driver__strength__codes.html#gaa502e2c995447037d266f939faa43223">More...</a><br/></td></tr>
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<tr class="separator:gaa502e2c995447037d266f939faa43223"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7944be4f63c439d5d64053ad9476407b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a7944be4f63c439d5d64053ad9476407b">ARM_NAND_ECC_INDEX_Pos</a>   0</td></tr>
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<tr class="separator:a7944be4f63c439d5d64053ad9476407b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a656537439264ab495c86e4c36051a3c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a656537439264ab495c86e4c36051a3c1">ARM_NAND_ECC_INDEX_Msk</a>   (0xFFUL << ARM_NAND_ECC_INDEX_Pos)</td></tr>
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<tr class="separator:a656537439264ab495c86e4c36051a3c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac2eb4475f12a443209165d29fe200030"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#gac2eb4475f12a443209165d29fe200030">ARM_NAND_ECC</a>(n)   ((n) & <a class="el" href="Driver__NAND_8h.html#a656537439264ab495c86e4c36051a3c1">ARM_NAND_ECC_INDEX_Msk</a>)</td></tr>
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<tr class="memdesc:gac2eb4475f12a443209165d29fe200030"><td class="mdescLeft"> </td><td class="mdescRight">Select ECC. <a href="group__nand__driver__ecc__codes.html#gac2eb4475f12a443209165d29fe200030">More...</a><br/></td></tr>
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<tr class="separator:gac2eb4475f12a443209165d29fe200030"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c79a12200c16f953936635f930df1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#ga15c79a12200c16f953936635f930df1d">ARM_NAND_ECC0</a>   (1UL << 8)</td></tr>
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<tr class="memdesc:ga15c79a12200c16f953936635f930df1d"><td class="mdescLeft"> </td><td class="mdescRight">Use ECC0 of selected ECC. <a href="group__nand__driver__ecc__codes.html#ga15c79a12200c16f953936635f930df1d">More...</a><br/></td></tr>
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<tr class="separator:ga15c79a12200c16f953936635f930df1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee653288a88318ee33d1db81baa69bbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__ecc__codes.html#gaee653288a88318ee33d1db81baa69bbc">ARM_NAND_ECC1</a>   (1UL << 9)</td></tr>
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<tr class="memdesc:gaee653288a88318ee33d1db81baa69bbc"><td class="mdescLeft"> </td><td class="mdescRight">Use ECC1 of selected ECC. <a href="group__nand__driver__ecc__codes.html#gaee653288a88318ee33d1db81baa69bbc">More...</a><br/></td></tr>
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<tr class="separator:gaee653288a88318ee33d1db81baa69bbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf40631ba62411e0ac06c3a945d608581"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__flag__codes.html#gaf40631ba62411e0ac06c3a945d608581">ARM_NAND_DRIVER_DONE_EVENT</a>   (1UL << 16)</td></tr>
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<tr class="memdesc:gaf40631ba62411e0ac06c3a945d608581"><td class="mdescLeft"> </td><td class="mdescRight">Generate <a class="el" href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">ARM_NAND_EVENT_DRIVER_DONE</a>. <a href="group__nand__driver__flag__codes.html#gaf40631ba62411e0ac06c3a945d608581">More...</a><br/></td></tr>
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<tr class="separator:gaf40631ba62411e0ac06c3a945d608581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaef90c96cd4f2309044d7d438c6b0930a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gaef90c96cd4f2309044d7d438c6b0930a">ARM_NAND_CODE_SEND_CMD1</a>   (1UL << 17)</td></tr>
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<tr class="memdesc:gaef90c96cd4f2309044d7d438c6b0930a"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 1. <a href="group__nand__driver__seq__exec__codes.html#gaef90c96cd4f2309044d7d438c6b0930a">More...</a><br/></td></tr>
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<tr class="separator:gaef90c96cd4f2309044d7d438c6b0930a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga891bcba60ebb1195ec80c00c9bec748a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga891bcba60ebb1195ec80c00c9bec748a">ARM_NAND_CODE_SEND_ADDR_COL1</a>   (1UL << 18)</td></tr>
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<tr class="memdesc:ga891bcba60ebb1195ec80c00c9bec748a"><td class="mdescLeft"> </td><td class="mdescRight">Send Column Address 1. <a href="group__nand__driver__seq__exec__codes.html#ga891bcba60ebb1195ec80c00c9bec748a">More...</a><br/></td></tr>
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<tr class="separator:ga891bcba60ebb1195ec80c00c9bec748a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga62a3f6ddcfb9ee317655bbec9e09bc10">ARM_NAND_CODE_SEND_ADDR_COL2</a>   (1UL << 19)</td></tr>
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<tr class="memdesc:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="mdescLeft"> </td><td class="mdescRight">Send Column Address 2. <a href="group__nand__driver__seq__exec__codes.html#ga62a3f6ddcfb9ee317655bbec9e09bc10">More...</a><br/></td></tr>
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<tr class="separator:ga62a3f6ddcfb9ee317655bbec9e09bc10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gadc001e69d1e81dc28a542237c6fe11ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gadc001e69d1e81dc28a542237c6fe11ff">ARM_NAND_CODE_SEND_ADDR_ROW1</a>   (1UL << 20)</td></tr>
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<tr class="memdesc:gadc001e69d1e81dc28a542237c6fe11ff"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 1. <a href="group__nand__driver__seq__exec__codes.html#gadc001e69d1e81dc28a542237c6fe11ff">More...</a><br/></td></tr>
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<tr class="separator:gadc001e69d1e81dc28a542237c6fe11ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga5e55628cb59f5d7d35c529f04ebfcd10">ARM_NAND_CODE_SEND_ADDR_ROW2</a>   (1UL << 21)</td></tr>
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<tr class="memdesc:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 2. <a href="group__nand__driver__seq__exec__codes.html#ga5e55628cb59f5d7d35c529f04ebfcd10">More...</a><br/></td></tr>
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<tr class="separator:ga5e55628cb59f5d7d35c529f04ebfcd10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gaeb5d1be9c13b7ad2ad246d5db10cd419">ARM_NAND_CODE_SEND_ADDR_ROW3</a>   (1UL << 22)</td></tr>
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<tr class="memdesc:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="mdescLeft"> </td><td class="mdescRight">Send Row Address 3. <a href="group__nand__driver__seq__exec__codes.html#gaeb5d1be9c13b7ad2ad246d5db10cd419">More...</a><br/></td></tr>
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<tr class="separator:gaeb5d1be9c13b7ad2ad246d5db10cd419"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga959522c98183036da32984dd5e07979b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga959522c98183036da32984dd5e07979b">ARM_NAND_CODE_INC_ADDR_ROW</a>   (1UL << 23)</td></tr>
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<tr class="memdesc:ga959522c98183036da32984dd5e07979b"><td class="mdescLeft"> </td><td class="mdescRight">Auto-increment Row Address. <a href="group__nand__driver__seq__exec__codes.html#ga959522c98183036da32984dd5e07979b">More...</a><br/></td></tr>
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<tr class="separator:ga959522c98183036da32984dd5e07979b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga1b40fc5fbf22dc4fa8130f5836e30d12">ARM_NAND_CODE_WRITE_DATA</a>   (1UL << 24)</td></tr>
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<tr class="memdesc:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="mdescLeft"> </td><td class="mdescRight">Write Data. <a href="group__nand__driver__seq__exec__codes.html#ga1b40fc5fbf22dc4fa8130f5836e30d12">More...</a><br/></td></tr>
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<tr class="separator:ga1b40fc5fbf22dc4fa8130f5836e30d12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gacffafbbbca74f7ffa4cd3bb6b067c4ef">ARM_NAND_CODE_SEND_CMD2</a>   (1UL << 25)</td></tr>
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<tr class="memdesc:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 2. <a href="group__nand__driver__seq__exec__codes.html#gacffafbbbca74f7ffa4cd3bb6b067c4ef">More...</a><br/></td></tr>
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<tr class="separator:gacffafbbbca74f7ffa4cd3bb6b067c4ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0f4a8b1e97656e09f1c383852f290a37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga0f4a8b1e97656e09f1c383852f290a37">ARM_NAND_CODE_WAIT_BUSY</a>   (1UL << 26)</td></tr>
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<tr class="memdesc:ga0f4a8b1e97656e09f1c383852f290a37"><td class="mdescLeft"> </td><td class="mdescRight">Wait while R/Bn busy. <a href="group__nand__driver__seq__exec__codes.html#ga0f4a8b1e97656e09f1c383852f290a37">More...</a><br/></td></tr>
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<tr class="separator:ga0f4a8b1e97656e09f1c383852f290a37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab524d840ab57c720ce8560144651dc9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#gab524d840ab57c720ce8560144651dc9d">ARM_NAND_CODE_READ_DATA</a>   (1UL << 27)</td></tr>
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<tr class="memdesc:gab524d840ab57c720ce8560144651dc9d"><td class="mdescLeft"> </td><td class="mdescRight">Read Data. <a href="group__nand__driver__seq__exec__codes.html#gab524d840ab57c720ce8560144651dc9d">More...</a><br/></td></tr>
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<tr class="separator:gab524d840ab57c720ce8560144651dc9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga20f96743ab77bda14ba391dc0c3cdba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga20f96743ab77bda14ba391dc0c3cdba5">ARM_NAND_CODE_SEND_CMD3</a>   (1UL << 28)</td></tr>
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<tr class="memdesc:ga20f96743ab77bda14ba391dc0c3cdba5"><td class="mdescLeft"> </td><td class="mdescRight">Send Command 3. <a href="group__nand__driver__seq__exec__codes.html#ga20f96743ab77bda14ba391dc0c3cdba5">More...</a><br/></td></tr>
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<tr class="memitem:ga2250f6a532d2c0834bfdc618761ddc86"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__driver__seq__exec__codes.html#ga2250f6a532d2c0834bfdc618761ddc86">ARM_NAND_CODE_READ_STATUS</a>   (1UL << 29)</td></tr>
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<tr class="memdesc:ga2250f6a532d2c0834bfdc618761ddc86"><td class="mdescLeft"> </td><td class="mdescRight">Read Status byte and check FAIL bit (bit 0) <a href="group__nand__driver__seq__exec__codes.html#ga2250f6a532d2c0834bfdc618761ddc86">More...</a><br/></td></tr>
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<tr class="separator:ga2250f6a532d2c0834bfdc618761ddc86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae34722cf52938f50bf117780a742b6f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae34722cf52938f50bf117780a742b6f1">ARM_NAND_CODE_CMD1_Pos</a>   0</td></tr>
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<tr class="separator:ae34722cf52938f50bf117780a742b6f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac65db62329bb943592afdb523e4aadca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac65db62329bb943592afdb523e4aadca">ARM_NAND_CODE_CMD1_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD1_Pos)</td></tr>
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<tr class="separator:ac65db62329bb943592afdb523e4aadca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeebe274650e7d0c02b478318759972e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aeebe274650e7d0c02b478318759972e5">ARM_NAND_CODE_CMD2_Pos</a>   8</td></tr>
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<tr class="separator:aeebe274650e7d0c02b478318759972e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f963016c81be2ddf7a09d983de226a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a0f963016c81be2ddf7a09d983de226a9">ARM_NAND_CODE_CMD2_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD2_Pos)</td></tr>
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<tr class="separator:a0f963016c81be2ddf7a09d983de226a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0b87b819cf3c94f32e3ef18dcfd1c6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#aa0b87b819cf3c94f32e3ef18dcfd1c6c">ARM_NAND_CODE_CMD3_Pos</a>   16</td></tr>
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<tr class="separator:aa0b87b819cf3c94f32e3ef18dcfd1c6c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16d474e55d0f6ea6efc3cc5436493b22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a16d474e55d0f6ea6efc3cc5436493b22">ARM_NAND_CODE_CMD3_Msk</a>   (0xFFUL << ARM_NAND_CODE_CMD3_Pos)</td></tr>
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<tr class="separator:a16d474e55d0f6ea6efc3cc5436493b22"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8b06772e2b6c5930319b17bbb806133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ab8b06772e2b6c5930319b17bbb806133">ARM_NAND_CODE_ADDR_COL1_Pos</a>   0</td></tr>
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<tr class="separator:ab8b06772e2b6c5930319b17bbb806133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0951de69f3836c1ab229ec60b3996fcc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a0951de69f3836c1ab229ec60b3996fcc">ARM_NAND_CODE_ADDR_COL1_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)</td></tr>
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<tr class="separator:a0951de69f3836c1ab229ec60b3996fcc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c4b9e7f44f77ebf665af8860a3c7528"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a1c4b9e7f44f77ebf665af8860a3c7528">ARM_NAND_CODE_ADDR_COL2_Pos</a>   8</td></tr>
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<tr class="separator:a1c4b9e7f44f77ebf665af8860a3c7528"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6126261e7c53713cee04aeae839d330e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6126261e7c53713cee04aeae839d330e">ARM_NAND_CODE_ADDR_COL2_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)</td></tr>
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<tr class="separator:a6126261e7c53713cee04aeae839d330e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b75efa00810fcf23fb0f12e7f62d338"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a8b75efa00810fcf23fb0f12e7f62d338">ARM_NAND_CODE_ADDR_ROW1_Pos</a>   0</td></tr>
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<tr class="separator:a8b75efa00810fcf23fb0f12e7f62d338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac24600be47e725ab1ad4193fd84daf80"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ac24600be47e725ab1ad4193fd84daf80">ARM_NAND_CODE_ADDR_ROW1_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)</td></tr>
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<tr class="separator:ac24600be47e725ab1ad4193fd84daf80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a326e135c57b38c78ae88cea121722a30"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a326e135c57b38c78ae88cea121722a30">ARM_NAND_CODE_ADDR_ROW2_Pos</a>   8</td></tr>
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<tr class="separator:a326e135c57b38c78ae88cea121722a30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae17a3f9b9fd70a88f9f9f38dd2c17951"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#ae17a3f9b9fd70a88f9f9f38dd2c17951">ARM_NAND_CODE_ADDR_ROW2_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)</td></tr>
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<tr class="separator:ae17a3f9b9fd70a88f9f9f38dd2c17951"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6873f7aedfe81efa8ca21dc85cbb384c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#a6873f7aedfe81efa8ca21dc85cbb384c">ARM_NAND_CODE_ADDR_ROW3_Pos</a>   16</td></tr>
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<tr class="separator:a6873f7aedfe81efa8ca21dc85cbb384c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf1ecacc2b225877c9cfe4f15dafc03c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="Driver__NAND_8h.html#acf1ecacc2b225877c9cfe4f15dafc03c">ARM_NAND_CODE_ADDR_ROW3_Msk</a>   (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)</td></tr>
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<tr class="separator:acf1ecacc2b225877c9cfe4f15dafc03c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafebec6ac091750a47b1d59bc843c15b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__execution__status.html#gafebec6ac091750a47b1d59bc843c15b0">ARM_NAND_ERROR_ECC</a>   (<a class="el" href="group__execution__status.html#ga5a2b5d68f6649598d099b88c0eaee3e5">ARM_DRIVER_ERROR_SPECIFIC</a> - 1)</td></tr>
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<tr class="memdesc:gafebec6ac091750a47b1d59bc843c15b0"><td class="mdescLeft"> </td><td class="mdescRight">ECC generation/correction failed. <a href="group__nand__execution__status.html#gafebec6ac091750a47b1d59bc843c15b0">More...</a><br/></td></tr>
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<tr class="separator:gafebec6ac091750a47b1d59bc843c15b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0be7e1b41188def905de0a1568d442d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">ARM_NAND_EVENT_DEVICE_READY</a>   (1UL << 0)</td></tr>
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<tr class="memdesc:gae0be7e1b41188def905de0a1568d442d"><td class="mdescLeft"> </td><td class="mdescRight">Device Ready: R/Bn rising edge. <a href="group__NAND__events.html#gae0be7e1b41188def905de0a1568d442d">More...</a><br/></td></tr>
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<tr class="separator:gae0be7e1b41188def905de0a1568d442d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">ARM_NAND_EVENT_DRIVER_READY</a>   (1UL << 1)</td></tr>
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<tr class="memdesc:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="mdescLeft"> </td><td class="mdescRight">Driver Ready. <a href="group__NAND__events.html#ga7b390a906db42c5ea4db38e0e85bb9e9">More...</a><br/></td></tr>
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<tr class="separator:ga7b390a906db42c5ea4db38e0e85bb9e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac774a334871789d24107b843d1ebd00c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">ARM_NAND_EVENT_DRIVER_DONE</a>   (1UL << 2)</td></tr>
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<tr class="memdesc:gac774a334871789d24107b843d1ebd00c"><td class="mdescLeft"> </td><td class="mdescRight">Driver operation done. <a href="group__NAND__events.html#gac774a334871789d24107b843d1ebd00c">More...</a><br/></td></tr>
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<tr class="separator:gac774a334871789d24107b843d1ebd00c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7bee0c32528ab991c0c064f895f80664"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NAND__events.html#ga7bee0c32528ab991c0c064f895f80664">ARM_NAND_EVENT_ECC_ERROR</a>   (1UL << 3)</td></tr>
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<tr class="memdesc:ga7bee0c32528ab991c0c064f895f80664"><td class="mdescLeft"> </td><td class="mdescRight">ECC could not correct data. <a href="group__NAND__events.html#ga7bee0c32528ab991c0c064f895f80664">More...</a><br/></td></tr>
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<tr class="separator:ga7bee0c32528ab991c0c064f895f80664"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">ARM_NAND_SignalEvent_t</a> )(uint32_t dev_num, uint32_t event)</td></tr>
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<tr class="memdesc:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="mdescLeft"> </td><td class="mdescRight">Pointer to <a class="el" href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">ARM_NAND_SignalEvent</a> : Signal NAND Event. <a href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">More...</a><br/></td></tr>
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<tr class="separator:ga09f4cf2f2df0bb690bce38b13d77e50f"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<a class="anchor" id="a121ff96c31275cef4bb7e86007665e1c"></a>
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<td class="memname">#define ARM_NAND_API_VERSION   <a class="el" href="Driver__Common_8h.html#a43c7ca1eb0786d818624246c09932a74">ARM_DRIVER_VERSION_MAJOR_MINOR</a>(2,2) /* API version */</td>
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<td class="memname">#define ARM_NAND_POWER_VCC_Pos   0</td>
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<td class="memname">#define ARM_NAND_POWER_VCC_Msk   (0x07UL << ARM_NAND_POWER_VCC_Pos)</td>
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<a class="anchor" id="a323c320a6195b78c2c79f5c6e85f02e1"></a>
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<td class="memname">#define ARM_NAND_POWER_VCC_OFF   (0x01UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC Power off. </p>
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<a class="anchor" id="ad15355d67bc239ff49cceac69c2024b3"></a>
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<td class="memname">#define ARM_NAND_POWER_VCC_3V3   (0x02UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC = 3.3V. </p>
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<a class="anchor" id="aa7b9d5a71125b745caba5c1d7aff6385"></a>
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<td class="memname">#define ARM_NAND_POWER_VCC_1V8   (0x03UL << ARM_NAND_POWER_VCC_Pos)</td>
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<p>VCC = 1.8V. </p>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_Pos   3</td>
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<a class="anchor" id="a7a453227301d7c08d09b22dc8afafbe7"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_Msk   (0x07UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<a class="anchor" id="aca7679e8269ee986559f4218816937c3"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_OFF   (0x01UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ I/O Power off. </p>
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<a class="anchor" id="a6d5a8a33a0fdaaff2e57e1ac53c984c2"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_3V3   (0x02UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ = 3.3V. </p>
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<a class="anchor" id="a653d9b4d7bee173beb49d8fec0469476"></a>
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<td class="memname">#define ARM_NAND_POWER_VCCQ_1V8   (0x03UL << ARM_NAND_POWER_VCCQ_Pos)</td>
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<p>VCCQ = 1.8V. </p>
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<td class="memname">#define ARM_NAND_POWER_VPP_OFF   (1UL << 6)</td>
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<p>VPP off. </p>
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<a class="anchor" id="aeb0d50e30bbcd8ab59c3b78db634aad5"></a>
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_POWER_VPP_ON   (1Ul << 7)</td>
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</tr>
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</div><div class="memdoc">
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<p>VPP on. </p>
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</div>
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<a class="anchor" id="a372fc9b9cc1315046ceaffd6fd99e12c"></a>
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<div class="memitem">
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<td class="memname">#define ARM_NAND_BUS_INTERFACE_Pos   4</td>
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</div><div class="memdoc">
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</div>
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<a class="anchor" id="aea213eb1ba9c67beb6216a630d81b91f"></a>
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<div class="memitem">
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<table class="memname">
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<td class="memname">#define ARM_NAND_BUS_INTERFACE_Msk   (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="acc98e42d23656734c7f9a8a5421842d6"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_TIMING_MODE_Pos   0</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a57f6c319265b00878661656103abe660"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_TIMING_MODE_Msk   (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a57b282c0818c87b79ea4f11d03cc4f3c"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos   8</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ad30dfdbdc50a7ff72a5bb173c5f549dc"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="aa80b898cdf665aa14ff0e181e4ff31f1"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos   12</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ad9ab38101de68a1bc186f5687f63f7c3"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a7944be4f63c439d5d64053ad9476407b"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_ECC_INDEX_Pos   0</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a656537439264ab495c86e4c36051a3c1"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_ECC_INDEX_Msk   (0xFFUL << ARM_NAND_ECC_INDEX_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ae34722cf52938f50bf117780a742b6f1"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD1_Pos   0</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ac65db62329bb943592afdb523e4aadca"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD1_Msk   (0xFFUL << ARM_NAND_CODE_CMD1_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="aeebe274650e7d0c02b478318759972e5"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD2_Pos   8</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a0f963016c81be2ddf7a09d983de226a9"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD2_Msk   (0xFFUL << ARM_NAND_CODE_CMD2_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="aa0b87b819cf3c94f32e3ef18dcfd1c6c"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD3_Pos   16</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a16d474e55d0f6ea6efc3cc5436493b22"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_CMD3_Msk   (0xFFUL << ARM_NAND_CODE_CMD3_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ab8b06772e2b6c5930319b17bbb806133"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL1_Pos   0</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a0951de69f3836c1ab229ec60b3996fcc"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL1_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a1c4b9e7f44f77ebf665af8860a3c7528"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL2_Pos   8</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a6126261e7c53713cee04aeae839d330e"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_COL2_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a8b75efa00810fcf23fb0f12e7f62d338"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW1_Pos   0</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ac24600be47e725ab1ad4193fd84daf80"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW1_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a326e135c57b38c78ae88cea121722a30"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW2_Pos   8</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="ae17a3f9b9fd70a88f9f9f38dd2c17951"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW2_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="a6873f7aedfe81efa8ca21dc85cbb384c"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW3_Pos   16</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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<a class="anchor" id="acf1ecacc2b225877c9cfe4f15dafc03c"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define ARM_NAND_CODE_ADDR_ROW3_Msk   (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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</div>
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</div>
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</div><!-- contents -->
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</div><!-- doc-content -->
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<!-- start footer part -->
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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<ul>
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<li class="navelem"><a class="el" href="dir_7151b3cc910409bb744bd274374c738d.html">Driver</a></li><li class="navelem"><a class="el" href="dir_9c39448ea46a8e15f1aabc7dec307fcf.html">Include</a></li><li class="navelem"><a class="el" href="Driver__NAND_8h.html">Driver_NAND.h</a></li>
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<li class="footer">Generated on Wed Feb 8 2017 10:20:43 for CMSIS-Driver by ARM Ltd. All rights reserved.
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