176 lines
9.8 KiB
C
176 lines
9.8 KiB
C
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/**
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* @file xmc_hrpwm_map.h
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* @date 2015-06-20
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*
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* @cond
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**********************************************************************************
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* XMClib v2.1.16 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification,are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share
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* modifications, enhancements or bug fixes with Infineon Technologies AG
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* dave@infineon.com).
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**********************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-06-20:
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* - Updated copyright and change history section.
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*
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* @endcond
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*
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*/
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/**
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*
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* @brief HRPWM mapping for XMC4 microcontroller family. <br>
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*
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*/
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/*********************************************************************************************************************
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* HEADER FILES
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********************************************************************************************************************/
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#include "xmc_hrpwm.h"
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#ifndef XMC_HRPWM_MAP_H
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#define XMC_HRPWM_MAP_H
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#if ((UC_DEVICE == XMC4400) || (UC_DEVICE == XMC4200) || (UC_DEVICE == XMC4100))
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/* CSG0 - General input to control Blanking and Switch of the Comparator */
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#define XMC_HRPWM_CSG0_BL_P1_4 XMC_HRPWM_CSG_INPUT_SEL_IA
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#define XMC_HRPWM_CSG0_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG0_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG0_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG0_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG0_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG0_BL_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG0_BL_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG0_BL_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG0_BL_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG0_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG0_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG0_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG0_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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/* CSG0 - General input to control start/stop/trigger for Slope Control Logic */
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#define XMC_HRPWM_CSG0_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG0_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG0_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG0_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG0_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG0_SC_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG0_SC_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG0_SC_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG0_SC_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG0_SC_HRPWM_C0O XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG0_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG0_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG0_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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/* CSG1 - General input to control Blanking and Switch of the Comparator */
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#define XMC_HRPWM_CSG1_BL_P2_4 XMC_HRPWM_CSG_INPUT_SEL_IA
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#define XMC_HRPWM_CSG1_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG1_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG1_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG1_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG1_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG1_BL_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG1_BL_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG1_BL_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG1_BL_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG1_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG1_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG1_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG1_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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/* CSG1 - General input to control start/stop/trigger for Slope Control Logic */
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#define XMC_HRPWM_CSG1_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG1_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG1_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG1_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG1_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG1_SC_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG1_SC_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG1_SC_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG1_SC_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG1_SC_HRPWM_C1O XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG1_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG1_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG1_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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/* CSG2 - General input to control Blanking and Switch of the Comparator */
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#define XMC_HRPWM_CSG2_BL_P2_5 XMC_HRPWM_CSG_INPUT_SEL_IA
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#define XMC_HRPWM_CSG2_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG2_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG2_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG2_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG2_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG2_BL_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG2_BL_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG2_BL_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG2_BL_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG2_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG2_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG2_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG2_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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/* CSG2 - General input to control start/stop/trigger for Slope Control Logic */
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#define XMC_HRPWM_CSG2_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
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#define XMC_HRPWM_CSG2_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
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#define XMC_HRPWM_CSG2_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
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#define XMC_HRPWM_CSG2_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
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#define XMC_HRPWM_CSG2_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
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#define XMC_HRPWM_CSG2_SC_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG
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#define XMC_HRPWM_CSG2_SC_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH
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#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II
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#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ
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#define XMC_HRPWM_CSG2_SC_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK
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#define XMC_HRPWM_CSG2_SC_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL
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#define XMC_HRPWM_CSG2_SC_HRPWM_C2O XMC_HRPWM_CSG_INPUT_SEL_IM
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#define XMC_HRPWM_CSG2_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
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#define XMC_HRPWM_CSG2_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
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#define XMC_HRPWM_CSG2_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
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#endif
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#endif /* XMC_HRPWM_MAP_H */
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