218 lines
7.7 KiB
ArmAsm
218 lines
7.7 KiB
ArmAsm
;*******************************************************************************
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;* @file startup_TLE986x.s
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;* @brief CMSIS Core Device Startup File for
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;* Infineon TLE986x Device Series
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;* @version V1.0
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;* @date September 2012
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;*
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;* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
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;*
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;*
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;* @par
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;* Infineon Technologies AG (Infineon) is supplying this software for use with
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;* Infineon's microcontrollers. This file can be freely distributed
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;* within development tools that are supporting such microcontrollers.
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;*
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;* @par
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;* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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;* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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;* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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;* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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;* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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;*
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;******************************************************************************
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;************************** Version History ************************************
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; V1.0, Sep, 9, 2012 DM: initial version
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;*******************************************************************************
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Stack_Size EQU 0x200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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THUMB
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PRESERVE8
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;*******************************************************************************
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; Fill-up the Vector Table entries with the exceptions ISR address
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;*******************************************************************************
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp
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DCD Reset_Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD GPT1_IRQHandler ; 0: GPT1
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DCD GPT2_IRQHandler ; 1: GPT2
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DCD ADC2_IRQHandler ; 2: Measurement Unit, Timer3
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DCD ADC1_IRQHandler ; 3: 10 bit ADC
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DCD CCU6SR0_IRQHandler ; 4: CCU0
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DCD CCU6SR1_IRQHandler ; 5: CCU1
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DCD CCU6SR2_IRQHandler ; 6: CCU2
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DCD CCU6SR3_IRQHandler ; 7: CCU3
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DCD SSC1_IRQHandler ; 8: SSC1
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DCD SSC2_IRQHandler ; 9: SSC2
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DCD UART1_IRQHandler ; 10: UART1
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DCD UART2_IRQHandler ; 11: UART2
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DCD EXINT0_IRQHandler ; 12: EXINT0
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DCD EXINT1_IRQHandler ; 13: EXINT1
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DCD BDRV_IRQHandler ; 14: BDRV
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DCD DMA_IRQHandler ; 15: DMA
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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;-------------------------------------------------------------------------------
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; Reset Handler
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;
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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;-------------------------------------------------------------------------------
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT GPT1_IRQHandler [WEAK]
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EXPORT GPT2_IRQHandler [WEAK]
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EXPORT ADC2_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT CCU6SR0_IRQHandler [WEAK]
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EXPORT CCU6SR1_IRQHandler [WEAK]
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EXPORT CCU6SR2_IRQHandler [WEAK]
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EXPORT CCU6SR3_IRQHandler [WEAK]
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EXPORT SSC1_IRQHandler [WEAK]
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EXPORT SSC2_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT EXINT0_IRQHandler [WEAK]
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EXPORT EXINT1_IRQHandler [WEAK]
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EXPORT BDRV_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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GPT1_IRQHandler
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GPT2_IRQHandler
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ADC2_IRQHandler
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ADC1_IRQHandler
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CCU6SR0_IRQHandler
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CCU6SR1_IRQHandler
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CCU6SR2_IRQHandler
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CCU6SR3_IRQHandler
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SSC1_IRQHandler
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SSC2_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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EXINT0_IRQHandler
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EXINT1_IRQHandler
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BDRV_IRQHandler
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DMA_IRQHandler
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B .
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ENDP
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;-------------------------------------------------------------------------------
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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