166 lines
6.8 KiB
C
166 lines
6.8 KiB
C
/**
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* @file xmc_eth_mac_map.h
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* @date 2015-06-20
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.16 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-06-20:
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* - Initial <br>
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*
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* @endcond
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*/
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#ifndef XMC_ETH_MAC_MAP_H
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#define XMC_ETH_MAC_MAP_H
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/**
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* ETH MAC interface mode
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_MODE
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{
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XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */
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XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */
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} XMC_ETH_MAC_PORT_CTRL_MODE_t;
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/**
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* ETH MAC receive data 0 line
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0
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{
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XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2 = 1U, /**< RXD0B receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8 = 2U, /**< RXD0C receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0 = 3U /**< RXD0D receive data line */
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} XMC_ETH_MAC_PORT_CTRL_RXD0_t;
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/**
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* ETH MAC receive data 1 line
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1
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{
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XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3 = 1U, /**< RXD1B receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9 = 2U, /**< RXD1C receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1 = 3U /**< RXD1D receive data line */
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} XMC_ETH_MAC_PORT_CTRL_RXD1_t;
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/**
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* ETH MAC receive data 2 line
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2
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{
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XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4 = 1U /**< RXD2B receive data line */
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} XMC_ETH_MAC_PORT_CTRL_RXD2_t;
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/**
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* ETH MAC receive data 3 line
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3
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{
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XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */
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XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3 = 1U /**< RXD3B Receive data line */
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} XMC_ETH_MAC_PORT_CTRL_RXD3_t;
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/**
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* ETH MAC PHY clock
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII
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{
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XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */
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XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0 = 1U, /**< XMC_ETH_RMIIB PHY clock */
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XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8 = 2U, /**< XMC_ETH_RMIIC PHY clock */
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XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5 = 3U /**< XMC_ETH_RMIID PHY clock */
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} XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t;
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/**
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* ETH MAC carrier sense data valid
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV
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{
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XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */
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XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1 = 1U, /**< XMC_ETH_CRS_DVB carrier sense data valid */
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XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9 = 2U, /**< XMC_ETH_CRS_DVC carrier sense data valid */
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XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2 = 3U /**< XMC_ETH_CRS_DVD carrier sense data valid */
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} XMC_ETH_MAC_PORT_CTRL_CRS_DV_t;
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/**
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* ETH MAC carrier sense
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_CRS
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{
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XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */
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XMC_ETH_MAC_PORT_CTRL_CRS_P5_4 = 3U /**< XMC_ETH_CRSD carrier sense */
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} XMC_ETH_MAC_PORT_CTRL_CRS_t;
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/**
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* ETH MAC receive error
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_RXER
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{
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XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */
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XMC_ETH_MAC_PORT_CTRL_RXER_P0_11 = 1U, /**< XMC_ETH_RXERB carrier sense */
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XMC_ETH_MAC_PORT_CTRL_RXER_P5_3 = 3U /**< XMC_ETH_RXERD carrier sense */
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} XMC_ETH_MAC_PORT_CTRL_RXER_t;
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/**
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* ETH MAC collision detection
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_COL
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{
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XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */
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XMC_ETH_MAC_PORT_CTRL_COL_P5_5 = 3U /**< XMC_ETH_COLD collision detection */
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} XMC_ETH_MAC_PORT_CTRL_COL_t;
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/**
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* ETH PHY transmit clock
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX
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{
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XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */
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XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6 = 1U /**< XMC_ETH_CLK_TXB PHY transmit clock */
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} XMC_ETH_MAC_PORT_CTRL_CLK_TX_t;
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/**
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* ETH management data I/O
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*/
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typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO
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{
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XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */
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XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0 = 1U, /**< XMC_ETH_MDIOB management data I/O */
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XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11 = 2U /**< XMC_ETH_MDIOC management data I/O */
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} XMC_ETH_MAC_PORT_CTRL_MDIO_t;
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#endif
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