697 lines
24 KiB
C
697 lines
24 KiB
C
/**
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* @file xmc_fce.h
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* @date 2015-06-20
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*
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* @cond
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*********************************************************************************************************************
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* XMClib v2.1.16 - XMC Peripheral Driver Library
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*
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* Copyright (c) 2015-2017, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
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* Infineon Technologies AG dave@infineon.com).
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*********************************************************************************************************************
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*
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* Change History
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* --------------
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*
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* 2015-02-20:
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* - Initial
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*
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* 2015-05-20:
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* - Description updated <br>
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*
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* 2015-06-20:
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* - Removed version macros and declaration of GetDriverVersion API
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* @endcond
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*
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*/
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#ifndef XMC_FCE_H
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#define XMC_FCE_H
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/**********************************************************************************************************************
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* HEADER FILES
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*********************************************************************************************************************/
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#include <xmc_common.h>
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#if defined (FCE)
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/**
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* @addtogroup XMClib
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* @{
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*/
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/**
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* @addtogroup FCE
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* @brief Flexible CRC Engine(FCE) driver for the XMC microcontroller family.
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*
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* The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC)
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* algorithms. The current FCE version for the XMC4000 microcontroller family implements the
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* IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials.
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* The primary target of FCE is to be used as an hardware acceleration engine for software
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* applications or operating systems services using CRC signatures.
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*
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* @image html fce_overview.png
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* @image latex ../images/fce_overview.png
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* FCE Features: <br>
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* @image html fce_polynomials.png
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* @image latex ../images/fce_polynomials.png
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* * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71 <br>
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* * CRC kernel 2: CCITT CRC16 polynomial: 0x1021 <br>
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* * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D <br>
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* * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at
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* the end of a message. <br>
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* * Extended register interface to control reliability of FCE execution in safety applications. <br>
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* * Error notification scheme via dedicated interrupt node for: <br>
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a)Transient error detection: Error interrupt generation (maskable) with local status register
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(cleared by software) <br>
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b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software) <br>
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FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers. <br>
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* @{
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*/
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/**********************************************************************************************************************
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* MACROS
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*********************************************************************************************************************/
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#define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0 <br> */
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#define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1 <br> */
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#define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2 <br> */
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#define XMC_FCE_CRC8 FCE_KE3 /**< Kernel 3 <br> */
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#define XMC_FCE_REFIN_SET (1U) /**< Enables input reflection */
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#define XMC_FCE_REFIN_RESET (0U) /**< Disables input reflection */
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#define XMC_FCE_REFOUT_SET (1U) /**< Enables output reflection */
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#define XMC_FCE_REFOUT_RESET (0U) /**< Disables output reflection */
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#define XMC_FCE_INVSEL_SET (1U) /**< Enables output inversion */
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#define XMC_FCE_INVSEL_RESET (0U) /**< Disables output inversion */
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/**********************************************************************************************************************
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* ENUMS
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*********************************************************************************************************************/
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/**
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* FCE interrupt configuration
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*/
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typedef enum XMC_FCE_CONFIG_INTERRUPT
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{
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XMC_FCE_CFG_CONFIG_CMI = FCE_KE_CFG_CMI_Msk, /**< Enables CRC Mismatch interrupt \n*/
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XMC_FCE_CFG_CONFIG_CEI = FCE_KE_CFG_CEI_Msk, /**< Enables Configuration error interrupt \n*/
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XMC_FCE_CFG_CONFIG_LEI = FCE_KE_CFG_LEI_Msk, /**< Enables Length error interrupt \n*/
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XMC_FCE_CFG_CONFIG_BEI = FCE_KE_CFG_BEI_Msk /**< Enables Bus error interrupt \n*/
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} XMC_FCE_CONFIG_INTERRUPT_t;
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/**
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* FCE operation configuration
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*/
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typedef enum XMC_FCE_CONFIG_OPERATION
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{
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XMC_FCE_CFG_CONFIG_CCE = FCE_KE_CFG_CCE_Msk, /**< Enables CRC check */
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XMC_FCE_CFG_CONFIG_ALR = FCE_KE_CFG_ALR_Msk /**< Enables Automatic length reload */
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} XMC_FCE_CONFIG_OPERATION_t;
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/**
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* FCE algorithm configuration
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*/
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typedef enum XMC_FCE_CONFIG_ALGO
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{
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XMC_FCE_CFG_CONFIG_REFIN = FCE_KE_CFG_REFIN_Msk, /**< Enables input byte reflection */
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XMC_FCE_CFG_CONFIG_REFOUT = FCE_KE_CFG_REFOUT_Msk, /**< Enables Final CRC reflection */
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XMC_FCE_CFG_CONFIG_XSEL = FCE_KE_CFG_XSEL_Msk /**< Enables output inversion */
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} XMC_FCE_CONFIG_ALGO_t;
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/**
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* FCE status flag configuration
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*/
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typedef enum XMC_FCE_STS_FLAG
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{
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XMC_FCE_STS_MISMATCH_CRC = FCE_KE_STS_CMF_Msk, /**< CRC Mismatch flag */
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XMC_FCE_STS_CONFIG_ERROR = FCE_KE_STS_CEF_Msk, /**< Configuration Error flag */
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XMC_FCE_STS_LENGTH_ERROR = FCE_KE_STS_LEF_Msk, /**< Length Error flag */
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XMC_FCE_STS_BUS_ERROR = FCE_KE_STS_BEF_Msk /**< Bus Error flag */
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} XMC_FCE_STS_FLAG_t;
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/**
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* FCE control configuration
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*/
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typedef enum XMC_FCE_CTR_TEST
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{
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XMC_FCE_CTR_MISMATCH_CRC = FCE_KE_CTR_FCM_Msk, /**< Forces CRC mismatch */
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XMC_FCE_CTR_MISMATCH_CFG = FCE_KE_CTR_FRM_CFG_Msk, /**< Forces CFG Register mismatch */
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XMC_FCE_CTR_MISMATCH_CHECK = FCE_KE_CTR_FRM_CHECK_Msk /**< Forces CRC Check Register mismatch */
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} XMC_FCE_CTR_TEST_t;
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/**
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* FCE status enumeration
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*/
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typedef enum XMC_FCE_STATUS
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{
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XMC_FCE_STATUS_OK = 0, /**< Returns OK on success */
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XMC_FCE_STATUS_BUSY, /**< Returns BUSY when API is busy with a previous request */
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XMC_FCE_STATUS_ERROR /**< Returns ERROR when API cannot fulfil request */
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} XMC_FCE_STATUS_t;
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/**********************************************************************************************************************
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* DATA STRUCTURES
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*********************************************************************************************************************/
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/**
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* FCE kernel
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*/
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typedef FCE_KE_TypeDef XMC_FCE_Kernel_t;
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/* Anonymous structure/union guard start */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__TASKING__)
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#pragma warning 586
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#endif
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/**
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* @brief XMC_FCE configuration structure
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*/
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typedef struct XMC_FCE_CONFIG
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{
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union
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{
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uint32_t regval;
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struct
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{
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uint32_t : 8;
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uint32_t config_refin : 1; /**< Enables byte-wise reflection */
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uint32_t config_refout : 1; /**< Enables bit-wise reflection */
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uint32_t config_xsel : 1; /**< Enables output inversion */
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uint32_t : 21; /**< Reserved bits */
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};
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};
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} XMC_FCE_CONFIG_t;
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/* Anonymous structure/union guard end */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__TASKING__)
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#pragma warning restore
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#endif
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/**
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* FCE handler
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*/
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typedef struct XMC_FCE
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{
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XMC_FCE_Kernel_t *kernel_ptr; /**< FCE Kernel Pointer */
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XMC_FCE_CONFIG_t fce_cfg_update; /**< FCE CFG register update */
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uint32_t seedvalue; /**< CRC seed value to be used */
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} XMC_FCE_t;
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/**********************************************************************************************************************
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* API PROTOTYPES
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*********************************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @param None
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* @return uint32_t Module revision number
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*
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* \par<b>Description: </b><br>
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* Read FCE module revision number <br>
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*
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* \par
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* The value of a module revision starts with 0x01 (first revision). The current revision
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* number is 0x01.
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*/
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__STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void)
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{
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return (uint32_t)(FCE->ID & FCE_ID_MOD_REV_Msk);
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}
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/**
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* @param None
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* @return uint32_t Module type
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*
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* \par<b>Description: </b><br>
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* Read the FCE module type <br>
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*
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* \par
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* The return value is currently 0xC0. It defines the module as a 32-bit module.
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*/
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__STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void)
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{
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return (uint32_t)((FCE->ID & FCE_ID_MOD_TYPE_Msk) >> FCE_ID_MOD_TYPE_Pos);
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}
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/**
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* @param None
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* @return uint32_t Module number
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*
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* \par<b>Description: </b><br>
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* Read FCE module number <br>
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*
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* \par
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* The return value for FCE module is currently 0x00CA.
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*/
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__STATIC_INLINE uint32_t XMC_FCE_ReadModuleNumber(void)
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{
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return ((uint32_t)((FCE->ID & FCE_ID_MOD_NUMBER_Msk) >> FCE_ID_MOD_NUMBER_Pos));
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}
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/**
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* @param None
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* @return bool Disable status
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*
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*
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* \par<b>Description: </b><br>
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* Return the disable status <br>
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*
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* \par
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* The function reads the FCE module disable status (DISS) bit. It returns "true" if
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* set, "false" otherwise.
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*/
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__STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void)
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{
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return (bool)(FCE->CLC &= (uint32_t)~FCE_CLC_DISS_Msk);
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}
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/**
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* @param None
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable the FCE module <br>
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*
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* \par
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* The function asserts the FCE peripheral reset and sets the DISR bit in the CLC
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* register.
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*
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* \par<b>Note: </b><br>
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* All pending transactions running on the bus slave interface must be completed before
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* entering the disabled state.
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*/
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void XMC_FCE_Disable(void);
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/**
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* @param None
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable the FCE module <br>
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*
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* \par
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* The function de-asserts the peripheral reset and clears the DISR bit CLC register.
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*/
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void XMC_FCE_Enable(void);
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @return ::XMC_FCE_STATUS_t
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*
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* \par<b>Description: </b><br>
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* Initialize the FCE engine <br>
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*
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* \par
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* The function sets to the CFG and CRC registers with the FCE configuration and
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* seeds values. The function always returns XMC_FCE_STATUS_SUCCESS.
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*
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* \par<b>Note: </b><br>
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* The software must first ensure that the CRC kernel is properly configured with the
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* initial CRC value (seed value).
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*/
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XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine);
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param seedvalue Initial CRC value
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* @return None
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*
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* \par<b>Description: </b><br>
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* Initialize FCE seed value
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*
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* \par
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* The function sets the initial CRC (seed) value in the CRC register.
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*/
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__STATIC_INLINE void XMC_FCE_InitializeSeedValue(const XMC_FCE_t *const engine, uint32_t seedvalue)
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{
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engine->kernel_ptr->CRC = seedvalue;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable FCE event(s) <br>
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*
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* \par
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* The function sets the CFG register to enable FCE event(s).
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*/
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__STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event)
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{
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engine->kernel_ptr->CFG |= (uint32_t)event;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable FCE event(s) <br>
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*
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* \par
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* The function clears the CFG register to disable FCE event(s).
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*/
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__STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event)
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{
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engine->kernel_ptr->CFG &= ~(uint32_t)event;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param event Event of type ::XMC_FCE_STS_FLAG_t
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* @return bool
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*
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* \par<b>Description: </b><br>
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* Return the event status of FCE event <br>
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*
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* \par
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* The function returns the status of a single requested FCE event by reading the
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* appropriate bit-fields of the STS register.
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*/
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__STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
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{
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return (bool) (engine->kernel_ptr->STS & (uint32_t)event);
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param event Event of type ::XMC_FCE_STS_FLAG_t
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* @return None
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*
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* \par<b>Description: </b><br>
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* Clear an FCE event <br>
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*
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* \par
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* The function clears requested FCE events by setting the bit-fields of the STS
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* register.
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*/
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__STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
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{
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engine->kernel_ptr->STS |= (uint32_t)event;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enable CRC operations <br>
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*
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* \par
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* The function enables FRC operations by writing to the CFG register.
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*
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* \par<b>Note: </b><br>
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* CRC comparison check (at the end of message) can be enabled using the CCE bit-field.
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* Automatic reload of LENGTH field (at the end of message) can be enabled using the
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* ALR bit field.
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*/
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__STATIC_INLINE void XMC_FCE_EnableOperation(const XMC_FCE_t *const engine, uint32_t operation)
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{
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engine->kernel_ptr->CFG |= operation;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
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* @return None
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*
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* \par<b>Description: </b><br>
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* Disable CRC operations <br>
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*
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* \par
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* The function disables FRC operations by writing to the CFG register.
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*
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* \par<b>Note: </b><br>
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* CRC comparison check (at the end of message) can be disabled using the CCE bit-field.
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* Automatic reload of LENGTH field (at the end of message) can be disabled using the
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* ALR bit field.
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*/
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__STATIC_INLINE void XMC_FCE_DisableOperation(const XMC_FCE_t *const engine, uint32_t operation)
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{
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engine->kernel_ptr->CFG &= ~(uint32_t)operation;
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}
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/**
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* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
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* @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
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* of logically OR'd algorithms
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* @return None
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*
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* \par<b>Description: </b><br>
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* Enables CRC algorithm(s) <br>
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*
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* \par<b>Note: </b><br>
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* Options for enabling CRC algorithm: <br>
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* REFIN: Input byte wise reflection <br>
|
|
* REFOUT: Output bit wise reflection <br>
|
|
* XSEL: Value to be XORed with final CRC <br>
|
|
*/
|
|
__STATIC_INLINE void XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
|
|
{
|
|
engine->kernel_ptr->CFG |= (uint32_t)algo;
|
|
}
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
|
|
* of logically OR'd algorithms
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Disable CRC algorithm(s) <br>
|
|
*
|
|
* \par<b>Note: </b><br>
|
|
* Options for disabling CRC algorithm: <br>
|
|
* REFIN: Input byte wise reflection <br>
|
|
* REFOUT: Output bit wise reflection <br>
|
|
* XSEL: Value to be XORed with final CRC <br>
|
|
*/
|
|
__STATIC_INLINE void XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
|
|
{
|
|
engine->kernel_ptr->CFG &= ~(uint32_t)algo;
|
|
}
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param checkvalue Checksum value
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Updates CRC check value <br>
|
|
*
|
|
* \par
|
|
* When the CFG.CCE bit field is set, every time the IR register is written, the
|
|
* LENGTH register is decremented by one until it reaches zero. The hardware monitors
|
|
* the transition of the LENGTH register from 1 to 0 to detect the end of the
|
|
* message and proceed with the comparison of the result register (RES) value with
|
|
* the CHECK register value.
|
|
*/
|
|
__STATIC_INLINE void XMC_FCE_UpdateCRCCheck(const XMC_FCE_t *const engine, const uint32_t checkvalue)
|
|
{
|
|
engine->kernel_ptr->CHECK = 0xFACECAFEU;
|
|
engine->kernel_ptr->CHECK = checkvalue;
|
|
}
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param checklength Checksum length
|
|
* @return None <br>
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Updates CRC length specified in the input parameter <br>
|
|
*
|
|
* \par
|
|
* When the ALR bit field is set to 1, every write to the IR register decrements
|
|
* the value of the LENGTH bit field. The LENGTH field shall be reloaded with its
|
|
* configuration value at the end of the cycle where LENGTH reaches 0.
|
|
*/
|
|
__STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const uint32_t checklength)
|
|
{
|
|
engine->kernel_ptr->LENGTH = 0xFACECAFEU;
|
|
engine->kernel_ptr->LENGTH = checklength;
|
|
}
|
|
|
|
/**
|
|
* @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
|
|
* @param data Pointer to the data buffer
|
|
* @param length Total number of bytes of data buffer
|
|
* @param result Pointer to computed CRC result
|
|
* @return XMC_FCE_STATUS_ERROR on error
|
|
* @return XMC_FCE_STATUS_SUCCESS otherwise.
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Calculate and updates the CRC8 checksum in the result pointer <br>
|
|
*
|
|
* \par<b>Note: </b><br>
|
|
* A write to IRm (m = 3) triggers the CRC kernel to update the message checksum
|
|
* according to the IR and current CRC register contents. Any write transaction
|
|
* is allowed to this IRm register. Only the lower 8-bit of the write transactions
|
|
* will be used. ::XMC_FCE_GetCRCResult() should be called after invoking
|
|
* ::XMC_FCE_CalculateCRC8() to get final CRC value.
|
|
*/
|
|
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine,
|
|
const uint8_t *data,
|
|
uint32_t length,
|
|
uint8_t *result);
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param data Pointer to the data buffer
|
|
* @param length Length of data buffer
|
|
* @param result Pointer to computed CRC result
|
|
* @return XMC_FCE_STATUS_ERROR on error
|
|
* @return XMC_FCE_STATUS_SUCCESS otherwise.
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Calculate and update the RC16 checksum in the result pointer <br>
|
|
*
|
|
* \par<b>Note: </b><br>
|
|
* A write to Internal Register (IRm m = 2) triggers the CRC kernel to update the
|
|
* message checksum according to the IR and current CRC register contents. Only 32-bit
|
|
* or 16-bit write transactions are permitted. Any other bus write transaction will
|
|
* lead to a bus error. Only the lower 16-bit of the write transactions will be used.
|
|
* ::XMC_FCE_GetCRCResult() should be called after ::XMC_FCE_CalculateCRC16() to get
|
|
* final CRC value.
|
|
*/
|
|
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine,
|
|
const uint16_t *data,
|
|
uint32_t length,
|
|
uint16_t *result);
|
|
|
|
/**
|
|
* @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
|
|
* @param data Pointer to the data buffer
|
|
* @param length Total number of bytes of data buffer
|
|
* @param result Pointer to computed CRC result
|
|
* @return XMC_FCE_STATUS_ERROR on error
|
|
* @return XMC_FCE_STATUS_SUCCESS otherwise.
|
|
*
|
|
* \par<b>Description</b><br>
|
|
* Calculate and update the calculated CRC32 checksum in the result pointer <br>
|
|
*
|
|
* \par<b>Note:</b><br>
|
|
* A write to Internal Register (IRm, m = 0-1) triggers the CRC kernel to update
|
|
* the message checksum according to the IR and current CRC register contents. Only
|
|
* 32-bit write transactions are permitted. Any other bus write transaction will
|
|
* lead to a bus error. ::XMC_FCE_GetCRCResult() should be called after
|
|
* ::XMC_FCE_CalculateCRC32() to get final CRC value.
|
|
*/
|
|
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine,
|
|
const uint32_t *data,
|
|
uint32_t length,
|
|
uint32_t *result);
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param result Pointer to CRC result
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Read the final CRC value from RES register <br>
|
|
*/
|
|
__STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result)
|
|
{
|
|
*result= engine->kernel_ptr->RES;
|
|
}
|
|
|
|
/**
|
|
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
|
|
* @param test values of type ::XMC_FCE_CTR_TEST_t
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Trigger the CTR register to generate a CRC mismatch/register mismatch/check register
|
|
* mismatch interrupt <br>
|
|
*/
|
|
void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test);
|
|
|
|
/**
|
|
* @param inbuffer Pointer to input data buffer
|
|
* @param outbuffer Pointer to the output data buffer
|
|
* @param length Length of the input buffer
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Convert input data buffer's endianness from big endian to little endian <br>
|
|
*
|
|
* \par
|
|
* The function stores the converted data in output data buffer.
|
|
*
|
|
* \par<b>Note: </b><br>
|
|
* This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute
|
|
* the CRC value.
|
|
*/
|
|
void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length);
|
|
|
|
/**
|
|
* @param inbuffer Pointer to input data buffer
|
|
* @param outbuffer Pointer to the output data buffer
|
|
* @param length Length of the input buffer
|
|
* @return None
|
|
*
|
|
* \par<b>Description: </b><br>
|
|
* Convert input data buffer's endianness from big endian to little endian <br>
|
|
*
|
|
* \par
|
|
* The function stores the converted data in output data buffer.
|
|
*
|
|
* \par<b>Note: </b><br>
|
|
* This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute
|
|
* the CRC value.
|
|
*/
|
|
void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined (FCE) */
|
|
|
|
#endif /* XMC_FCE_H */
|