451 lines
17 KiB
C
451 lines
17 KiB
C
/*
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* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
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*
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* Infineon Technologies AG (Infineon) is supplying this software for use with
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* Infineon's microcontrollers.
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* This file can be freely distributed within development tools that are
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* supporting such microcontrollers.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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/**
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* @file
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* @date 9 November,2015
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* @version 1.0.0
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*
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* @brief Ethernet - EtherCAT loop
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*
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* History
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*
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* Version 1.0.0
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* - Initial
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*
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* Version 1.0.2
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* - Update to latest XMClib
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*/
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#include "xmc_scu.h"
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#include "xmc_gpio.h"
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#include "xmc_eth_mac.h"
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#include "xmc_eth_phy.h"
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#include "xmc_ecat.h"
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#define ETH_PHY_ADDR 0
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#define ECAT_P0_PHY_ADDR 0
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#define ECAT_P1_PHY_ADDR 1
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#define ETH_RXD1 P2_3
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#define ETH_RXD0 P2_2
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#define ETH_RXER P2_4
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#define ETH_CLK_RMII P15_8
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#define ETH_TX_EN P2_5
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#define ETH_TXD1 P2_9
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#define ETH_TXD0 P2_8
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#define ETH_CRS_DV P15_9
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#define ETH_MDIO P2_0
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#define ETH_MDC P2_7
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#define ECAT_MDO P0_12
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#define ECAT_MCLK P3_3
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#define ECAT_CLK25 P6_0
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#define ECAT_PHY_RESET P0_0
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#define ECAT_LED_RUN P0_8
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#define ECAT_LED_ERR P0_7
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#define ECAT_LED8 P3_11
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#define ECAT_LED7 P5_3
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#define ECAT_LED6 P3_13
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#define ECAT_LED5 P1_12
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#define ECAT_LED4 P0_15
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#define ECAT_LED3 P3_14
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#define ECAT_LED2 P0_14
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#define ECAT_LED1 P1_14
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#define ECAT_P0_LINK_STATUS P1_15
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#define ECAT_P0_LED_LINK_ACT P6_3
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#define ECAT_P0_RXD3 P5_7
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#define ECAT_P0_RXD2 P5_2
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#define ECAT_P0_RXD1 P5_1
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#define ECAT_P0_RXD0 P5_0
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#define ECAT_P0_RX_DV P5_6
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#define ECAT_P0_RX_CLK P5_4
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#define ECAT_P0_RX_ERR P2_6
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#define ECAT_P0_TXD3 P6_6
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#define ECAT_P0_TXD2 P6_5
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#define ECAT_P0_TXD1 P6_4
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#define ECAT_P0_TXD0 P6_2
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#define ECAT_P0_TX_EN P6_1
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#define ECAT_P0_TX_CLK P5_5
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#define ECAT_P1_LINK_STATUS P3_4
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#define ECAT_P1_LED_LINK_ACT P3_12
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#define ECAT_P1_RXD3 P0_4
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#define ECAT_P1_RXD2 P0_5
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#define ECAT_P1_RXD1 P0_6
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#define ECAT_P1_RXD0 P0_11
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#define ECAT_P1_RX_DV P0_9
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#define ECAT_P1_RX_CLK P0_1
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#define ECAT_P1_RX_ERR P15_2
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#define ECAT_P1_TXD3 P0_3
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#define ECAT_P1_TXD2 P0_2
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#define ECAT_P1_TXD1 P3_2
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#define ECAT_P1_TXD0 P3_1
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#define ECAT_P1_TX_EN P3_0
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#define ECAT_P1_TX_CLK P0_10
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/* MAC ADDRESS*/
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#define MAC_ADDR0 0x00
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#define MAC_ADDR1 0x00
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#define MAC_ADDR2 0x45
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#define MAC_ADDR3 0x19
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#define MAC_ADDR4 0x03
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#define MAC_ADDR5 0x00
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#define MAC_ADDR ((uint64_t)MAC_ADDR0 | \
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((uint64_t)MAC_ADDR1 << 8) | \
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((uint64_t)MAC_ADDR2 << 16) | \
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((uint64_t)MAC_ADDR3 << 24) | \
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((uint64_t)MAC_ADDR4 << 32) | \
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((uint64_t)MAC_ADDR5 << 40))
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#define XMC_ETH_MAC_NUM_RX_BUF (4)
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#define XMC_ETH_MAC_NUM_TX_BUF (4)
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#if defined(__ICCARM__)
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#pragma data_alignment=4
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static XMC_ETH_MAC_DMA_DESC_t rx_desc[XMC_ETH_MAC_NUM_RX_BUF] @ ".dram";
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#pragma data_alignment=4
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static XMC_ETH_MAC_DMA_DESC_t tx_desc[XMC_ETH_MAC_NUM_TX_BUF] @ ".dram";
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#pragma data_alignment=4
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static uint8_t rx_buf[XMC_ETH_MAC_NUM_RX_BUF][XMC_ETH_MAC_BUF_SIZE] @ ".dram";
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#pragma data_alignment=4
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static uint8_t tx_buf[XMC_ETH_MAC_NUM_TX_BUF][XMC_ETH_MAC_BUF_SIZE] @ ".dram";
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#endif
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#if defined(__CC_ARM)
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static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t rx_desc[XMC_ETH_MAC_NUM_RX_BUF] __attribute__((section ("RW_IRAM1")));
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static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t tx_desc[XMC_ETH_MAC_NUM_TX_BUF] __attribute__((section ("RW_IRAM1")));
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static __attribute__((aligned(4))) uint8_t rx_buf[XMC_ETH_MAC_NUM_RX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("RW_IRAM1")));
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static __attribute__((aligned(4))) uint8_t tx_buf[XMC_ETH_MAC_NUM_TX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("RW_IRAM1")));
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#endif
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#if defined(__GNUC__)
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static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t rx_desc[XMC_ETH_MAC_NUM_RX_BUF] __attribute__((section ("ETH_RAM")));
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static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t tx_desc[XMC_ETH_MAC_NUM_TX_BUF] __attribute__((section ("ETH_RAM")));
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static __attribute__((aligned(4))) uint8_t rx_buf[XMC_ETH_MAC_NUM_RX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));
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static __attribute__((aligned(4))) uint8_t tx_buf[XMC_ETH_MAC_NUM_TX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));
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#endif
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static XMC_ETH_PHY_CONFIG_t eth_phy_config =
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{
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.interface = XMC_ETH_LINK_INTERFACE_RMII,
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.enable_auto_negotiate = true
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};
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static XMC_ETH_MAC_t eth_mac =
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{
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.regs = ETH0,
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.address = MAC_ADDR,
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.rx_desc = rx_desc,
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.tx_desc = tx_desc,
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.rx_buf = &rx_buf[0][0],
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.tx_buf = &tx_buf[0][0],
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.num_rx_buf = XMC_ETH_MAC_NUM_RX_BUF,
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.num_tx_buf = XMC_ETH_MAC_NUM_TX_BUF
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};
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static __attribute__((aligned(4))) uint8_t buffer[XMC_ETH_MAC_BUF_SIZE];
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static __attribute__((aligned(4))) uint8_t brd_frame[60] =
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{
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x14, /* ........ */
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0x4f, 0x23, 0x98, 0xcf, 0x88, 0xa4, 0x0e, 0x10, /* O#...... */
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0x07, 0x02, 0x00, 0x00, 0x30, 0x01, 0x02, 0x00, /* ....0... */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ........ */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ........ */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ........ */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ........ */
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0x00, 0x00, 0x00, 0x00 /* .... */
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};
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/* Clock configuration */
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/* fPLL = 288MHz */
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/* fPLLUSB = 200MHz */
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/* fSYS = 144MHz */
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/* fECAT = 100MHz */
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const XMC_SCU_CLOCK_CONFIG_t clock_config =
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{
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.syspll_config.p_div = 2,
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.syspll_config.n_div = 48,
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.syspll_config.k_div = 1,
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.syspll_config.mode = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
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.syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
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.enable_oschp = true,
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.calibration_mode = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
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.fsys_clksrc = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
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.fsys_clkdiv = 2,
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.fcpu_clkdiv = 1,
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.fccu_clkdiv = 1,
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.fperipheral_clkdiv = 1
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};
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void SystemCoreClockSetup(void)
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{
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/* Setup settings for USB clock */
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XMC_SCU_CLOCK_Init(&clock_config);
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XMC_SCU_CLOCK_EnableUsbPll();
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XMC_SCU_CLOCK_StartUsbPll(3, 100);
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XMC_SCU_CLOCK_SetECATClockDivider(2);
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XMC_SCU_CLOCK_SetECATClockSource(XMC_SCU_CLOCK_ECATCLKSRC_USBPLL);
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SystemCoreClockUpdate();
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}
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void ETH_MAC_Init(void);
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void ECAT_Init(void);
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volatile bool g_received_frame = false;
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int main(void)
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{
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XMC_GPIO_CONFIG_t config;
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config.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
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config.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
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config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE;
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XMC_GPIO_Init(ECAT_LED1, &config);
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XMC_GPIO_Init(ECAT_LED2, &config);
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XMC_GPIO_Init(ECAT_LED3, &config);
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XMC_GPIO_Init(ECAT_LED4, &config);
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XMC_GPIO_Init(ECAT_LED5, &config);
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XMC_GPIO_Init(ECAT_LED6, &config);
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XMC_GPIO_Init(ECAT_LED7, &config);
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XMC_GPIO_Init(ECAT_LED8, &config);
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ECAT_Init();
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ETH_MAC_Init();
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XMC_ETH_MAC_SendFrame(ð_mac, &brd_frame[0], 60, 0);
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while(1)
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{
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if (g_received_frame == true)
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{
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(buffer[29] & 0x01) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED1) : XMC_GPIO_SetOutputLow(ECAT_LED1);
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(buffer[29] & 0x02) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED2) : XMC_GPIO_SetOutputLow(ECAT_LED2);
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(buffer[29] & 0x04) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED3) : XMC_GPIO_SetOutputLow(ECAT_LED3);
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(buffer[29] & 0x08) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED4) : XMC_GPIO_SetOutputLow(ECAT_LED4);
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(buffer[29] & 0x10) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED5) : XMC_GPIO_SetOutputLow(ECAT_LED5);
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(buffer[29] & 0x20) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED6) : XMC_GPIO_SetOutputLow(ECAT_LED6);
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(buffer[29] & 0x40) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED7) : XMC_GPIO_SetOutputLow(ECAT_LED7);
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(buffer[29] & 0x80) == 0 ? XMC_GPIO_SetOutputHigh(ECAT_LED8) : XMC_GPIO_SetOutputLow(ECAT_LED8);
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g_received_frame = false;
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XMC_ETH_MAC_SendFrame(ð_mac, &buffer[0], 60, 0);
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}
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}
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}
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void ETH_MAC_Init(void)
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{
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XMC_ETH_MAC_PORT_CTRL_t port_control;
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XMC_GPIO_CONFIG_t gpio_config;
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gpio_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
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XMC_GPIO_Init(ETH_RXD0, &gpio_config);
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XMC_GPIO_Init(ETH_RXD1, &gpio_config);
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XMC_GPIO_Init(ETH_CLK_RMII, &gpio_config);
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XMC_GPIO_Init(ETH_CRS_DV, &gpio_config);
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XMC_GPIO_Init(ETH_RXER, &gpio_config);
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XMC_GPIO_Init(ETH_MDIO, &gpio_config);
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port_control.mode = XMC_ETH_MAC_PORT_CTRL_MODE_RMII;
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port_control.rxd0 = XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2;
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port_control.rxd1 = XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3;
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port_control.clk_rmii = XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8;
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port_control.crs_dv = XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9;
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port_control.rxer = XMC_ETH_MAC_PORT_CTRL_RXER_P2_4;
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port_control.mdio = XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0;
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XMC_ETH_MAC_SetPortControl(ð_mac, port_control);
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XMC_ETH_MAC_Init(ð_mac);
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XMC_ETH_MAC_DisableJumboFrame(ð_mac);
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gpio_config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
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gpio_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
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gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_8_AF_ETH0_TXD0);
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XMC_GPIO_Init(ETH_TXD0, &gpio_config);
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gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_9_AF_ETH0_TXD1);
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XMC_GPIO_Init(ETH_TXD1, &gpio_config);
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gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_5_AF_ETH0_TX_EN);
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XMC_GPIO_Init(ETH_TX_EN, &gpio_config);
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gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P2_7_AF_ETH0_MDC);
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XMC_GPIO_Init(ETH_MDC, &gpio_config);
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XMC_GPIO_SetHardwareControl(ETH_MDIO, P2_0_HWCTRL_ETH0_MDO);
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XMC_ETH_PHY_Init(ð_mac, ETH_PHY_ADDR, ð_phy_config);
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while(XMC_ETH_PHY_GetLinkStatus(ð_mac, ETH_PHY_ADDR) != XMC_ETH_LINK_STATUS_UP);
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XMC_ETH_LINK_SPEED_t speed = XMC_ETH_PHY_GetLinkSpeed(ð_mac, ETH_PHY_ADDR);
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XMC_ETH_LINK_DUPLEX_t duplex = XMC_ETH_PHY_GetLinkDuplex(ð_mac, ETH_PHY_ADDR);
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XMC_ETH_MAC_SetLink(ð_mac, speed, duplex);
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/* Enable ethernet interrupts */
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XMC_ETH_MAC_EnableEvent(ð_mac, XMC_ETH_MAC_EVENT_RECEIVE);
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NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 0));
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NVIC_ClearPendingIRQ(ETH0_0_IRQn);
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NVIC_EnableIRQ(ETH0_0_IRQn);
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XMC_ETH_MAC_EnableTx(ð_mac);
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XMC_ETH_MAC_EnableRx(ð_mac);
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}
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void ECAT_Init(void)
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{
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XMC_ECAT_PORT_CTRL_t port_control;
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XMC_ECAT_CONFIG_t ecat_config;
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XMC_GPIO_CONFIG_t gpio_config;
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gpio_config.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
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XMC_GPIO_Init(ECAT_P0_LINK_STATUS, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RXD3, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RXD2, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RXD1, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RXD0, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RX_DV, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RX_CLK, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_RX_ERR, &gpio_config);
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XMC_GPIO_Init(ECAT_P0_TX_CLK, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_LINK_STATUS, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RXD3, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RXD2, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RXD1, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RXD0, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RX_DV, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RX_CLK, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_RX_ERR, &gpio_config);
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XMC_GPIO_Init(ECAT_P1_TX_CLK, &gpio_config);
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XMC_GPIO_Init(ECAT_MDO, &gpio_config);
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port_control.common.mdio = XMC_ECAT_PORT_CTRL_MDIO_P0_12;
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port_control.port0.rxd0 = XMC_ECAT_PORT0_CTRL_RXD0_P5_0;
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port_control.port0.rxd1 = XMC_ECAT_PORT0_CTRL_RXD1_P5_1;
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port_control.port0.rxd2 = XMC_ECAT_PORT0_CTRL_RXD2_P5_2;
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port_control.port0.rxd3 = XMC_ECAT_PORT0_CTRL_RXD3_P5_7;
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port_control.port0.rx_clk = XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4;
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port_control.port0.rx_dv = XMC_ECAT_PORT0_CTRL_RX_DV_P5_6;
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port_control.port0.rx_err = XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6;
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port_control.port0.link = XMC_ECAT_PORT0_CTRL_LINK_P1_15;
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port_control.port0.tx_clk = XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5;
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port_control.port1.rxd0 = XMC_ECAT_PORT1_CTRL_RXD0_P0_11;
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port_control.port1.rxd1 = XMC_ECAT_PORT1_CTRL_RXD1_P0_6;
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port_control.port1.rxd2 = XMC_ECAT_PORT1_CTRL_RXD2_P0_5;
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port_control.port1.rxd3 = XMC_ECAT_PORT1_CTRL_RXD3_P0_4;
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port_control.port1.rx_clk = XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1;
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port_control.port1.rx_dv = XMC_ECAT_PORT1_CTRL_RX_DV_P0_9;
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port_control.port1.rx_err = XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2;
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port_control.port1.link = XMC_ECAT_PORT1_CTRL_LINK_P3_4;
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port_control.port1.tx_clk = XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10;
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XMC_ECAT_SetPortControl(port_control);
|
|
|
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ecat_config.enable_dc_sync_out = false;
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ecat_config.enable_dc_latch_in = false;
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ecat_config.enable_enhanced_link_p0 = true;
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ecat_config.enable_enhanced_link_p1 = true;
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ecat_config.sync_pulse_length = 1000;
|
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ecat_config.station_alias = 0;
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ecat_config.checksum = 0x88A4;
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|
|
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XMC_ECAT_Init(&ecat_config);
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|
|
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gpio_config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
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gpio_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE;
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gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_6_AF_ECAT0_P0_TXD3);
|
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XMC_GPIO_Init(ECAT_P0_TXD3, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_5_AF_ECAT0_P0_TXD2);
|
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XMC_GPIO_Init(ECAT_P0_TXD2, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_4_AF_ECAT0_P0_TXD1);
|
|
XMC_GPIO_Init(ECAT_P0_TXD1, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_2_AF_ECAT0_P0_TXD0);
|
|
XMC_GPIO_Init(ECAT_P0_TXD0, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_1_AF_ECAT0_P0_TX_ENA);
|
|
XMC_GPIO_Init(ECAT_P0_TX_EN, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P0_3_AF_ECAT0_P1_TXD3);
|
|
XMC_GPIO_Init(ECAT_P1_TXD3, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P0_2_AF_ECAT0_P1_TXD2);
|
|
XMC_GPIO_Init(ECAT_P1_TXD2, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P3_2_AF_ECAT0_P1_TXD1);
|
|
XMC_GPIO_Init(ECAT_P1_TXD1, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P3_1_AF_ECAT0_P1_TXD0);
|
|
XMC_GPIO_Init(ECAT_P1_TXD0, &gpio_config);
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P3_0_AF_ECAT0_P1_TX_ENA);
|
|
XMC_GPIO_Init(ECAT_P1_TX_EN, &gpio_config);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_0_AF_ECAT0_PHY_CLK25);
|
|
XMC_GPIO_Init(ECAT_CLK25, &gpio_config);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P3_3_AF_ECAT0_MCLK);
|
|
XMC_GPIO_Init(ECAT_MCLK, &gpio_config);
|
|
|
|
gpio_config.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE;
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P6_3_AF_ECAT0_P0_LED_LINK_ACT);
|
|
XMC_GPIO_Init(ECAT_P0_LED_LINK_ACT, &gpio_config);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P3_12_AF_ECAT0_P1_LED_LINK_ACT);
|
|
XMC_GPIO_Init(ECAT_P1_LED_LINK_ACT, &gpio_config);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P0_8_AF_ECAT0_LED_RUN);
|
|
XMC_GPIO_Init(ECAT_LED_RUN, &gpio_config);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P0_8_AF_ECAT0_LED_RUN);
|
|
XMC_GPIO_Init(ECAT_LED_ERR, &gpio_config);
|
|
|
|
XMC_GPIO_SetHardwareControl(ECAT_MDO, P0_12_HWCTRL_ECAT0_MDO);
|
|
|
|
gpio_config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | P0_0_AF_ECAT0_PHY_RESET);
|
|
XMC_GPIO_Init(ECAT_PHY_RESET, &gpio_config);
|
|
|
|
|
|
}
|
|
|
|
void ETH0_0_IRQHandler(void)
|
|
{
|
|
uint32_t status;
|
|
uint32_t len;
|
|
|
|
status = XMC_ETH_MAC_GetEventStatus(ð_mac);
|
|
|
|
if (status & XMC_ETH_MAC_EVENT_RECEIVE)
|
|
{
|
|
XMC_ETH_MAC_DisableEvent(ð_mac, XMC_ETH_MAC_EVENT_RECEIVE);
|
|
|
|
len = XMC_ETH_MAC_GetRxFrameSize(ð_mac);
|
|
XMC_ETH_MAC_ReadFrame(ð_mac, &buffer[0], len);
|
|
|
|
g_received_frame = true;
|
|
|
|
XMC_ETH_MAC_EnableEvent(ð_mac, XMC_ETH_MAC_EVENT_RECEIVE);
|
|
}
|
|
|
|
XMC_ETH_MAC_ClearEventStatus(ð_mac, status);
|
|
|
|
}
|
|
|