90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
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*
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* Infineon Technologies AG (Infineon) is supplying this software for use with
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* Infineon's microcontrollers.
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* This file can be freely distributed within development tools that are
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* supporting such microcontrollers.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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/**
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* @file
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* @date 22 July, 2015
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* @version 1.0.2
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*
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* @brief DMA demo example
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*
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* Transfer data from flash to SRAM
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*
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* History <br>
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*
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* Version 1.0.0 Initial <br>
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* Version 1.0.1 Enable interrupts <br>
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* Version 1.0.2 Included modifications to avoid Keil MDK warning <br>
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*
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*/
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#include <string.h>
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#include <xmc_dma.h>
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#include <xmc_common.h>
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#define DATA_LENGTH 10
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uint32_t source_data[DATA_LENGTH] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
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uint32_t destination_data[DATA_LENGTH];
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XMC_DMA_CH_CONFIG_t dma_ch_config;
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void GPDMA0_0_IRQHandler(void)
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{
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XMC_DMA_CH_ClearEventStatus(XMC_DMA0, 0, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
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if (memcmp(source_data, destination_data, DATA_LENGTH) != 0)
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{
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/* Error array are not equal */
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__BKPT(0);
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}
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}
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int main(void)
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{
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XMC_STRUCT_INIT(dma_ch_config);
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XMC_DMA_CH_CONFIG_t dma_ch_config =
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{
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.block_size = DATA_LENGTH,
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.src_addr = (uint32_t)&source_data[0],
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.dst_addr = (uint32_t)&destination_data[0],
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.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
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.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_32,
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.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
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.src_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_8,
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.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA,
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.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK,
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.enable_interrupt = true
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};
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XMC_DMA_Init(XMC_DMA0);
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XMC_DMA_CH_Init(XMC_DMA0, 0, &dma_ch_config);
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XMC_DMA_CH_EnableEvent(XMC_DMA0, 0, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
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/* Enable DMA event handling */
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NVIC_SetPriority(GPDMA0_0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63, 0));
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NVIC_EnableIRQ(GPDMA0_0_IRQn);
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/* Start DMA transfer */
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XMC_DMA_CH_Enable(XMC_DMA0, 0);
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while(1)
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{
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/* Infinite loop */
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}
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}
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