Add module circuit files

Devices/Module/Hardware/Circuit/.gitignore

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+*-bak
+*-cache*
+*-bak*
+_autosave*

Devices/Module/Hardware/Circuit/Libraries/CUI_TB006-508-03BE.pretty/CUI_TB006-508-03BE.kicad_mod

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+
+(module CUI_TB006-508-03BE (layer F.Cu) (tedit 6113F46A)
+  (descr "")
+  (fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
+    (effects (font (size 1.4 1.4) (thickness 0.15)))
+  )
+  (fp_text value CUI_TB006-508-03BE (at 12.462 5.461 0) (layer F.Fab)
+    (effects (font (size 1.4 1.4) (thickness 0.15)))
+  )
+  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
+  (fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.Fab) (width 0.127))
+  (fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.Fab) (width 0.127))
+  (fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
+  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
+  (fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.SilkS) (width 0.127))
+  (fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.SilkS) (width 0.127))
+  (fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
+  (fp_line (start -2.79 -4.35) (end 12.95 -4.35) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 12.95 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
+  (fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
+  (fp_line (start 12.95 -4.35) (end 12.95 4.35) (layer F.CrtYd) (width 0.05))
+  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
+  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
+  (pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
+  (pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
+  (pad 3 thru_hole circle (at 10.16 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
+)

Devices/Module/Hardware/Circuit/Libraries/TB006-508-03BE.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#(c) SnapEDA 2016 (snapeda.com)
+#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
+#
+# TB006-508-03BE
+#
+DEF TB006-508-03BE J 0 40 Y Y 1 L N
+F0 "J" -220 200 50 H V L BNN
+F1 "TB006-508-03BE" -200 -300 50 H V L BNN
+F2 "CUI_TB006-508-03BE" 0 0 50 H I L BNN
+F3 "" 0 0 50 H I L BNN
+F4 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
+F5 "CUI" 0 0 50 H I L BNN "MANUFACTURER"
+DRAW
+S -200 -200 200 200 0 0 10 f
+X 1 1 -400 100 200 R 40 40 0 0 P 
+X 2 2 -400 0 200 R 40 40 0 0 P 
+X 3 3 -400 -100 200 R 40 40 0 0 P 
+ENDDRAW
+ENDDEF
+#
+# End Library

Devices/Module/Hardware/Circuit/Module.kicad_pcb

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+(kicad_pcb (version 4) (host kicad "dummy file") )

Devices/Module/Hardware/Circuit/Module.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]

Devices/Module/Hardware/Circuit/Module.sch

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+EESchema Schematic File Version 2
+EELAYER 25 0
+EELAYER END
+$EndSCHEMATC

Devices/Module/Hardware/Circuit/fp-lib-table

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+(fp_lib_table
+  (lib (name CUI_TB006-508-03BE)(type KiCad)(uri ${KIPRJMOD}/Libraries/CUI_TB006-508-03BE.pretty)(options "")(descr ""))
+)