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GHOSCHT 2022-04-09 20:07:19 +02:00
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Hardware/Circuit/.gitignore vendored Normal file
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# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
*auto_saved_files*
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
# Backpus
Control-backups/*

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%TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
%TF.CreationDate,2022-03-17T17:24:26+01:00*%
%TF.ProjectId,Module,4d6f6475-6c65-42e6-9b69-6361645f7063,v01*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L2,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (6.0.1)) date 2022-03-17 17:24:26*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
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%TD*%
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%ADD11C,1.950000*%
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%ADD12C,0.800000*%
%TD*%
%TA.AperFunction,Conductor*%
%ADD13C,0.250000*%
%TD*%
G04 APERTURE END LIST*
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26
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1563
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88
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G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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%MOMM*%
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G01*
G04 APERTURE LIST*
G04 Aperture macros list*
%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
%ADD10R,1.950000X1.950000*%
%ADD11C,1.950000*%
%ADD12R,0.800000X1.900000*%
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65
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%MOMM*%
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G01*
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%AMRoundRect*
0 Rectangle with rounded corners*
0 $1 Rounding radius*
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
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%ADD10R,0.800000X1.900000*%
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G01*
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%AMRoundRect*
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0 Add a 4 corners polygon primitive as box body*
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
0 Add four circle primitives for the rounded corners*
1,1,$1+$1,$2,$3*
1,1,$1+$1,$4,$5*
1,1,$1+$1,$6,$7*
1,1,$1+$1,$8,$9*
0 Add four rect primitives between the rounded corners*
20,1,$1+$1,$2,$3,$4,$5,0*
20,1,$1+$1,$4,$5,$6,$7,0*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
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%ADD13C,0.120000*%
%ADD14R,1.950000X1.950000*%
%ADD15C,1.950000*%
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G04 Gerber Fmt 4.5, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (6.0.1)) date 2022-03-17 16:21:22*
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31
Hardware/Circuit/Gerber/Module-PTH.drl Normal file
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M48
; DRILL file {KiCad (6.0.1)} date Thu Mar 17 16:21:21 2022
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2022-03-17T16:21:21+01:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,(6.0.1)
; #@! TF.FileFunction,Plated,1,2,PTH
FMAT,2
METRIC
; #@! TA.AperFunction,Plated,PTH,ViaDrill
T1C0.400
; #@! TA.AperFunction,Plated,PTH,ComponentDrill
T2C1.300
%
G90
G05
T1
X140.97Y-71.755
X148.59Y-91.44
X151.13Y-71.755
T2
X139.954Y-57.404
X142.494Y-94.742
X145.034Y-57.404
X145.034Y-84.074
X147.574Y-94.742
X150.114Y-57.404
X150.114Y-84.074
X152.654Y-94.742
X155.194Y-57.404
T0
M30

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{
"Header": {
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "(6.0.1)"
},
"CreationDate": "2022-03-17T17:24:26+01:00"
},
"GeneralSpecs": {
"ProjectId": {
"Name": "Module",
"GUID": "4d6f6475-6c65-42e6-9b69-6361645f7063",
"Revision": "v01"
},
"Size": {
"X": 22.05,
"Y": 51.621
},
"LayerNumber": 2,
"BoardThickness": 1.6,
"Finish": "None"
},
"DesignRules": [
{
"Layers": "Outer",
"PadToPad": 0.2,
"PadToTrack": 0.2,
"TrackToTrack": 0.2,
"MinLineWidth": 0.25,
"TrackToRegion": 0.508,
"RegionToRegion": 0.508
}
],
"FilesAttributes": [
{
"Path": "Module-F_Cu.gtl",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "Module-B_Cu.gbl",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Module-F_Paste.gtp",
"FileFunction": "SolderPaste,Top",
"FilePolarity": "Positive"
},
{
"Path": "Module-B_Paste.gbp",
"FileFunction": "SolderPaste,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Module-F_Silkscreen.gto",
"FileFunction": "Legend,Top",
"FilePolarity": "Positive"
},
{
"Path": "Module-B_Silkscreen.gbo",
"FileFunction": "Legend,Bot",
"FilePolarity": "Positive"
},
{
"Path": "Module-F_Mask.gts",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "Module-B_Mask.gbs",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "Module-Edge_Cuts.gm1",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup": [
{
"Type": "Legend",
"Name": "Top Silk Screen"
},
{
"Type": "SolderPaste",
"Name": "Top Solder Paste"
},
{
"Type": "SolderMask",
"Name": "Top Solder Mask"
},
{
"Type": "Copper",
"Name": "F.Cu"
},
{
"Type": "Dielectric",
"Material": "FR4",
"Name": "F.Cu/B.Cu",
"Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
},
{
"Type": "Copper",
"Name": "B.Cu"
},
{
"Type": "SolderMask",
"Name": "Bottom Solder Mask"
},
{
"Type": "SolderPaste",
"Name": "Bottom Solder Paste"
},
{
"Type": "Legend",
"Name": "Bottom Silk Screen"
}
]
}

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Hardware/Circuit/Libraries/.gitkeep Normal file
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(module CUI_TB006-508-02BE (layer F.Cu) (tedit 611C079C)
(descr "")
(fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_text value CUI_TB006-508-02BE (at 12.462 5.461 0) (layer F.Fab)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 -4.1) (end 7.62 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start 7.62 -4.1) (end 7.62 4.1) (layer F.Fab) (width 0.127))
(fp_line (start 7.62 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 7.62 -4.1) (end 7.62 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.54 -4.1) (end 7.62 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 7.62 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.79 -4.35) (end 7.87 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.87 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.87 -4.35) (end 7.87 4.35) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
(pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
)

22671
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Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-03BE.kicad_mod Normal file
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(module CUI_TB006-508-03BE (layer F.Cu) (tedit 6113F46A)
(descr "")
(fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_text value CUI_TB006-508-03BE (at 12.462 5.461 0) (layer F.Fab)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.Fab) (width 0.127))
(fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.79 -4.35) (end 12.95 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.95 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.95 -4.35) (end 12.95 4.35) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
(pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 10.16 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
)

28
Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-04BE.kicad_mod Normal file
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(module CUI_TB006-508-04BE (layer F.Cu) (tedit 611C0388)
(descr "")
(fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_text value CUI_TB006-508-04BE (at 12.462 5.461 0) (layer F.Fab)
(effects (font (size 1.4 1.4) (thickness 0.15)))
)
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 -4.1) (end 17.78 -4.1) (layer F.Fab) (width 0.127))
(fp_line (start 17.78 -4.1) (end 17.78 4.1) (layer F.Fab) (width 0.127))
(fp_line (start 17.78 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
(fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 17.78 -4.1) (end 17.78 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.54 -4.1) (end 17.78 -4.1) (layer F.SilkS) (width 0.127))
(fp_line (start 17.78 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
(fp_line (start -2.79 -4.35) (end 18.03 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 18.03 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 18.03 -4.35) (end 18.03 4.35) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
(fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
(pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 10.16 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 15.24 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
)

23
Hardware/Circuit/Libraries/TB006-508-03BE.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#(c) SnapEDA 2016 (snapeda.com)
#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
#
# TB006-508-03BE
#
DEF TB006-508-03BE J 0 40 Y Y 1 L N
F0 "J" -220 200 50 H V L BNN
F1 "TB006-508-03BE" -200 -300 50 H V L BNN
F2 "CUI_TB006-508-03BE" 0 0 50 H I L BNN
F3 "" 0 0 50 H I L BNN
F4 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
F5 "CUI" 0 0 50 H I L BNN "MANUFACTURER"
DRAW
S -200 -200 200 200 0 0 10 f
X 1 1 -400 100 200 R 40 40 0 0 P
X 2 2 -400 0 200 R 40 40 0 0 P
X 3 3 -400 -100 200 R 40 40 0 0 P
ENDDRAW
ENDDEF
#
# End Library

64
Hardware/Circuit/Libraries/logo/logo.kicad_mod Normal file
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(footprint "LOGO" (version 20210606) (generator bitmap2component) (layer "F.Cu")
(at 0 0)
(attr board_only exclude_from_pos_files exclude_from_bom)
(fp_text reference "G***" (at 0 0) (layer F.SilkS)
(effects (font (thickness 0.3)))
)
(fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
(effects (font (thickness 0.3)))
)
(fp_poly (pts (xy 1.006804 -1.905763) (xy 1.031833 -1.905402) (xy 1.052015 -1.904769) (xy 1.067944 -1.903814) (xy 1.080213 -1.902487) (xy 1.089416 -1.900737) (xy 1.096146 -1.898515) (xy 1.100995 -1.895771)
(xy 1.104558 -1.892456) (xy 1.107427 -1.888518) (xy 1.110197 -1.883909) (xy 1.110591 -1.883240) (xy 1.111106 -1.882062) (xy 1.111594 -1.880180) (xy 1.112055 -1.877388) (xy 1.112490 -1.873481)
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)(layer F.SilkS) (width 0.000000)
)
)

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Screw_Terminal_01x02
#
DEF Connector_Screw_Terminal_01x02 J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Screw_Terminal_01x02" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TerminalBlock*:*
$ENDFPLIST
DRAW
C 0 -100 25 1 1 6 N
C 0 0 25 1 1 6 N
S -50 50 50 -150 1 1 10 f
P 2 1 1 6 -21 -87 13 -120 N
P 2 1 1 6 -21 13 13 -20 N
P 2 1 1 6 -14 -80 20 -113 N
P 2 1 1 6 -14 20 20 -13 N
X Pin_1 1 -200 0 150 R 50 50 1 1 P
X Pin_2 2 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Screw_Terminal_01x03
#
DEF Connector_Screw_Terminal_01x03 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Screw_Terminal_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TerminalBlock*:*
$ENDFPLIST
DRAW
C 0 -100 25 1 1 6 N
C 0 0 25 1 1 6 N
C 0 100 25 1 1 6 N
S -50 150 50 -150 1 1 10 f
P 2 1 1 6 -21 -87 13 -120 N
P 2 1 1 6 -21 13 13 -20 N
P 2 1 1 6 -21 113 13 80 N
P 2 1 1 6 -14 -80 20 -113 N
P 2 1 1 6 -14 20 20 -13 N
P 2 1 1 6 -14 120 20 87 N
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Screw_Terminal_01x04
#
DEF Connector_Screw_Terminal_01x04 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Screw_Terminal_01x04" 0 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TerminalBlock*:*
$ENDFPLIST
DRAW
C 0 -200 25 1 1 6 N
C 0 -100 25 1 1 6 N
C 0 0 25 1 1 6 N
C 0 100 25 1 1 6 N
S -50 150 50 -250 1 1 10 f
P 2 1 1 6 -21 -187 13 -220 N
P 2 1 1 6 -21 -87 13 -120 N
P 2 1 1 6 -21 13 13 -20 N
P 2 1 1 6 -21 113 13 80 N
P 2 1 1 6 -14 -180 20 -213 N
P 2 1 1 6 -14 -80 20 -113 N
P 2 1 1 6 -14 20 20 -13 N
P 2 1 1 6 -14 120 20 87 N
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
X Pin_4 4 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Q_NPN_BCE
#
DEF Device_Q_NPN_BCE Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Device_Q_NPN_BCE" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 225 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Jumper_SolderJumper_2_Open
#
DEF Jumper_SolderJumper_2_Open JP 0 0 Y N 1 F N
F0 "JP" 0 80 50 H V C CNN
F1 "Jumper_SolderJumper_2_Open" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*Open*
$ENDFPLIST
DRAW
A -10 0 40 901 -901 0 1 0 N -10 40 -10 -40
A -10 0 40 901 -901 0 1 0 F -10 40 -10 -40
A 10 0 40 -899 899 0 1 0 N 10 -40 10 40
A 10 0 40 -899 899 0 1 0 F 10 -40 10 40
P 2 0 1 0 -10 40 -10 -40 N
P 2 0 1 0 10 40 10 -40 N
X A 1 -150 0 100 R 50 50 1 1 P
X B 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.12,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
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},
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},
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"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
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}
],
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},
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},
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},
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1055
Hardware/Circuit/Module.kicad_sch Normal file
View file

File diff suppressed because it is too large Load diff

249
Hardware/Circuit/Module.pro Normal file
View file

@ -0,0 +1,249 @@
update=19.08.2021 14:20:23
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=Module.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.3
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

304
Hardware/Circuit/Module.sch Normal file
View file

@ -0,0 +1,304 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "LED Module"
Date "2021-08-19"
Rev "v01"
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