Improve repo directory structure

2022-04-09 20:07:19 +02:00 · 2022-04-09 20:07:19 +02:00 · b7a7b5f2ed
commit b7a7b5f2ed
36 changed files with 49218 additions and 0 deletions
--- a/Hardware/Circuit/.gitignore
+++ b/Hardware/Circuit/.gitignore
@ -0,0 +1,33 @@
 # For PCBs designed using KiCad: https://www.kicad.org/
 # Format documentation: https://kicad.org/help/file-formats/
 # Temporary files
 *.000
 *.bak
 *.bck
 *.kicad_pcb-bak
 *.kicad_sch-bak
 *-backups
 *.kicad_prl
 *.sch-bak
 *~
 _autosave-*
 *.tmp
 *-save.pro
 *-save.kicad_pcb
 fp-info-cache
 *auto_saved_files*
 # Netlist files (exported from Eeschema)
 *.net
 # Autorouter files (exported from Pcbnew)
 *.dsn
 *.ses
 # Exported BOM files
 *.xml
 *.csv
 # Backpus
 Control-backups/*
--- a/Hardware/Circuit/Gerber/Module-B_Cu.gbl
+++ b/Hardware/Circuit/Gerber/Module-B_Cu.gbl
@ -0,0 +1,947 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
 %TF.CreationDate,2022-03-17T17:24:26+01:00*%
 %TF.ProjectId,Module,4d6f6475-6c65-42e6-9b69-6361645f7063,v01*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L2,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
 G04 Created by KiCad (PCBNEW (6.0.1)) date 2022-03-17 17:24:26*
 %MOMM*%
 %LPD*%
 G01*
 G04 APERTURE LIST*
 %TA.AperFunction,ComponentPad*%
 %ADD10R,1.950000X1.950000*%
 %TD*%
 %TA.AperFunction,ComponentPad*%
 %ADD11C,1.950000*%
 %TD*%
 %TA.AperFunction,ViaPad*%
 %ADD12C,0.800000*%
 %TD*%
 %TA.AperFunction,Conductor*%
 %ADD13C,0.250000*%
 %TD*%
 G04 APERTURE END LIST*
 D10*
 %TO.P,J1,1,Pin_1*%
 %TO.N,SIG1*%
 X142494000Y-94742000D03*
 D11*
 %TO.P,J1,2,Pin_2*%
 %TO.N,SIG2*%
 X147574000Y-94742000D03*
 %TO.P,J1,3,Pin_3*%
 %TO.N,GND*%
 X152654000Y-94742000D03*
 %TD*%
 D10*
 %TO.P,J2,1,Pin_1*%
 %TO.N,VCC*%
 X155194000Y-57404000D03*
 D11*
 %TO.P,J2,2,Pin_2*%
 %TO.N,LED1N*%
 X150114000Y-57404000D03*
 %TO.P,J2,3,Pin_3*%
 %TO.N,VCC*%
 X145034000Y-57404000D03*
 %TO.P,J2,4,Pin_4*%
 %TO.N,LED2N*%
 X139954000Y-57404000D03*
 %TD*%
 D10*
 %TO.P,J3,1,Pin_1*%
 %TO.N,GND*%
 X150114000Y-84074000D03*
 D11*
 %TO.P,J3,2,Pin_2*%
 %TO.N,VCC*%
 X145034000Y-84074000D03*
 %TD*%
 D12*
 %TO.N,SIG1*%
 X148590000Y-91440000D03*
 %TO.N,GND*%
 X151130000Y-71755000D03*
 X140970000Y-71755000D03*
 %TD*%
 D13*
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 %TO.N,VCC*%
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 %TD*%
 %TA.AperFunction,Conductor*%
 %TO.N,GND*%
 G36*
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 X155436864Y-96950899D01*
 X155473366Y-96950933D01*
 G37*
 %TD*%
 %LPC*%
 D11*
 %TO.C,J1*%
 X142494000Y-94742000D03*
 D12*
 X147574000Y-94742000D03*
 X152654000Y-94742000D03*
 %TD*%
 D11*
 %TO.C,J2*%
 X155194000Y-57404000D03*
 D12*
 X150114000Y-57404000D03*
 X145034000Y-57404000D03*
 X139954000Y-57404000D03*
 %TD*%
 D11*
 %TO.C,J3*%
 X150114000Y-84074000D03*
 D12*
 X145034000Y-84074000D03*
 %TD*%
 M02*
--- a/Hardware/Circuit/Gerber/Module-Edge_Cuts.gm1
+++ b/Hardware/Circuit/Gerber/Module-Edge_Cuts.gm1
@ -0,0 +1,26 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
 %TF.CreationDate,2022-03-17T17:24:26+01:00*%
 %TF.ProjectId,Module,4d6f6475-6c65-42e6-9b69-6361645f7063,v01*%
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 %TF.FileFunction,Profile,NP*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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 %MOMM*%
 %LPD*%
 G01*
 G04 APERTURE LIST*
 %TA.AperFunction,Profile*%
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 %TD*%
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 D10*
 X158652000Y-50165000D02*
 X158652000Y-101736000D01*
 X136652000Y-101736000D02*
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 X136652000Y-50165000D02*
 X136652000Y-101736000D01*
 X136652000Y-50165000D02*
 X158652000Y-50165000D01*
 M02*
--- a/Hardware/Circuit/Gerber/Module-F_Cu.gtl
+++ b/Hardware/Circuit/Gerber/Module-F_Cu.gtl
--- a/Hardware/Circuit/Gerber/Module-F_Mask.gts
+++ b/Hardware/Circuit/Gerber/Module-F_Mask.gts
@ -0,0 +1,88 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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 %MOMM*%
 %LPD*%
 G01*
 G04 APERTURE LIST*
 G04 Aperture macros list*
 %AMRoundRect*
 0 Rectangle with rounded corners*
 0 $1 Rounding radius*
 0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
 0 Add a 4 corners polygon primitive as box body*
 4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
 0 Add four circle primitives for the rounded corners*
 1,1,$1+$1,$2,$3*
 1,1,$1+$1,$4,$5*
 1,1,$1+$1,$6,$7*
 1,1,$1+$1,$8,$9*
 0 Add four rect primitives between the rounded corners*
 20,1,$1+$1,$2,$3,$4,$5,0*
 20,1,$1+$1,$4,$5,$6,$7,0*
 20,1,$1+$1,$6,$7,$8,$9,0*
 20,1,$1+$1,$8,$9,$2,$3,0*%
 G04 Aperture macros list end*
 %ADD10R,1.950000X1.950000*%
 %ADD11C,1.950000*%
 %ADD12R,0.800000X1.900000*%
 %ADD13RoundRect,0.249999X-0.450001X0.350001X-0.450001X-0.350001X0.450001X-0.350001X0.450001X0.350001X0*%
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 D11*
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 %TD*%
 D10*
 %TO.C,J2*%
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 D11*
 X150114000Y-57404000D03*
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 %TD*%
 D12*
 %TO.C,Q1*%
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 %TD*%
 %TO.C,Q2*%
 X141920000Y-66318000D03*
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 %TD*%
 D10*
 %TO.C,J3*%
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 D11*
 X145034000Y-84074000D03*
 %TD*%
 D13*
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 %TD*%
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 %TD*%
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 %TD*%
 D14*
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 X139680000Y-75295000D03*
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 %TD*%
 M02*
--- a/Hardware/Circuit/Gerber/Module-F_Paste.gtp
+++ b/Hardware/Circuit/Gerber/Module-F_Paste.gtp
@ -0,0 +1,65 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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 %MOMM*%
 %LPD*%
 G01*
 G04 APERTURE LIST*
 G04 Aperture macros list*
 %AMRoundRect*
 0 Rectangle with rounded corners*
 0 $1 Rounding radius*
 0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
 0 Add a 4 corners polygon primitive as box body*
 4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
 0 Add four circle primitives for the rounded corners*
 1,1,$1+$1,$2,$3*
 1,1,$1+$1,$4,$5*
 1,1,$1+$1,$6,$7*
 1,1,$1+$1,$8,$9*
 0 Add four rect primitives between the rounded corners*
 20,1,$1+$1,$2,$3,$4,$5,0*
 20,1,$1+$1,$4,$5,$6,$7,0*
 20,1,$1+$1,$6,$7,$8,$9,0*
 20,1,$1+$1,$8,$9,$2,$3,0*%
 G04 Aperture macros list end*
 %ADD10R,0.800000X1.900000*%
 %ADD11RoundRect,0.249999X-0.450001X0.350001X-0.450001X-0.350001X0.450001X-0.350001X0.450001X0.350001X0*%
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 G04 APERTURE END LIST*
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 %TO.C,Q1*%
 X152080000Y-66318000D03*
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 %TD*%
 %TO.C,Q2*%
 X141920000Y-66318000D03*
 X140020000Y-66318000D03*
 X140970000Y-69318000D03*
 %TD*%
 D11*
 %TO.C,R2*%
 X142220000Y-73295000D03*
 X142220000Y-75295000D03*
 %TD*%
 %TO.C,R1*%
 X152400000Y-73295000D03*
 X152400000Y-75295000D03*
 %TD*%
 %TO.C,R3*%
 X149860000Y-73295000D03*
 X149860000Y-75295000D03*
 %TD*%
 D12*
 %TO.C,R4*%
 X139680000Y-75295000D03*
 X139680000Y-73295000D03*
 %TD*%
 M02*
--- a/Hardware/Circuit/Gerber/Module-F_Silkscreen.gto
+++ b/Hardware/Circuit/Gerber/Module-F_Silkscreen.gto
@ -0,0 +1,597 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,(6.0.1)*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
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 %MOMM*%
 %LPD*%
 G01*
 G04 APERTURE LIST*
 G04 Aperture macros list*
 %AMRoundRect*
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 0 Add a 4 corners polygon primitive as box body*
 4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
 0 Add four circle primitives for the rounded corners*
 1,1,$1+$1,$2,$3*
 1,1,$1+$1,$4,$5*
 1,1,$1+$1,$6,$7*
 1,1,$1+$1,$8,$9*
 0 Add four rect primitives between the rounded corners*
 20,1,$1+$1,$2,$3,$4,$5,0*
 20,1,$1+$1,$4,$5,$6,$7,0*
 20,1,$1+$1,$6,$7,$8,$9,0*
 20,1,$1+$1,$8,$9,$2,$3,0*%
 G04 Aperture macros list end*
 %ADD10C,0.150000*%
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 %ADD12C,0.200000*%
 %ADD13C,0.120000*%
 %ADD14R,1.950000X1.950000*%
 %ADD15C,1.950000*%
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 %ADD17RoundRect,0.249999X-0.450001X0.350001X-0.450001X-0.350001X0.450001X-0.350001X0.450001X0.350001X0*%
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--- a/Hardware/Circuit/Gerber/Module-NPTH-drl_map.gbr
+++ b/Hardware/Circuit/Gerber/Module-NPTH-drl_map.gbr
@ -0,0 +1,106 @@
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 G04 Gerber Fmt 4.5, Leading zero omitted, Abs format (unit mm)*
 G04 Created by KiCad (PCBNEW (6.0.1)) date 2022-03-17 16:21:22*
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--- a/Hardware/Circuit/Gerber/Module-NPTH.drl
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 M48
 ; DRILL file {KiCad (6.0.1)} date Thu Mar 17 16:21:21 2022
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--- a/Hardware/Circuit/Gerber/Module-PTH-drl_map.gbr
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@ -0,0 +1,758 @@
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 M02*
--- a/Hardware/Circuit/Gerber/Module-PTH.drl
+++ b/Hardware/Circuit/Gerber/Module-PTH.drl
@ -0,0 +1,31 @@
 M48
 ; DRILL file {KiCad (6.0.1)} date Thu Mar 17 16:21:21 2022
 ; FORMAT={-:-/ absolute / metric / decimal}
 ; #@! TF.CreationDate,2022-03-17T16:21:21+01:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,(6.0.1)
 ; #@! TF.FileFunction,Plated,1,2,PTH
 FMAT,2
 METRIC
 ; #@! TA.AperFunction,Plated,PTH,ViaDrill
 T1C0.400
 ; #@! TA.AperFunction,Plated,PTH,ComponentDrill
 T2C1.300
 %
 G90
 G05
 T1
 X140.97Y-71.755
 X148.59Y-91.44
 X151.13Y-71.755
 T2
 X139.954Y-57.404
 X142.494Y-94.742
 X145.034Y-57.404
 X145.034Y-84.074
 X147.574Y-94.742
 X150.114Y-57.404
 X150.114Y-84.074
 X152.654Y-94.742
 X155.194Y-57.404
 T0
 M30
--- a/Hardware/Circuit/Gerber/Module-job.gbrjob
+++ b/Hardware/Circuit/Gerber/Module-job.gbrjob
@ -0,0 +1,122 @@
 {
  "Header": {
    "GenerationSoftware": {
      "Vendor": "KiCad",
      "Application": "Pcbnew",
      "Version": "(6.0.1)"
    },
    "CreationDate": "2022-03-17T17:24:26+01:00"
  },
  "GeneralSpecs": {
    "ProjectId": {
      "Name": "Module",
      "GUID": "4d6f6475-6c65-42e6-9b69-6361645f7063",
      "Revision": "v01"
    },
    "Size": {
      "X": 22.05,
      "Y": 51.621
    },
    "LayerNumber": 2,
    "BoardThickness": 1.6,
    "Finish": "None"
  },
  "DesignRules": [
    {
      "Layers": "Outer",
      "PadToPad": 0.2,
      "PadToTrack": 0.2,
      "TrackToTrack": 0.2,
      "MinLineWidth": 0.25,
      "TrackToRegion": 0.508,
      "RegionToRegion": 0.508
    }
  ],
  "FilesAttributes": [
    {
      "Path": "Module-F_Cu.gtl",
      "FileFunction": "Copper,L1,Top",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-B_Cu.gbl",
      "FileFunction": "Copper,L2,Bot",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-F_Paste.gtp",
      "FileFunction": "SolderPaste,Top",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-B_Paste.gbp",
      "FileFunction": "SolderPaste,Bot",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-F_Silkscreen.gto",
      "FileFunction": "Legend,Top",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-B_Silkscreen.gbo",
      "FileFunction": "Legend,Bot",
      "FilePolarity": "Positive"
    },
    {
      "Path": "Module-F_Mask.gts",
      "FileFunction": "SolderMask,Top",
      "FilePolarity": "Negative"
    },
    {
      "Path": "Module-B_Mask.gbs",
      "FileFunction": "SolderMask,Bot",
      "FilePolarity": "Negative"
    },
    {
      "Path": "Module-Edge_Cuts.gm1",
      "FileFunction": "Profile",
      "FilePolarity": "Positive"
    }
  ],
  "MaterialStackup": [
    {
      "Type": "Legend",
      "Name": "Top Silk Screen"
    },
    {
      "Type": "SolderPaste",
      "Name": "Top Solder Paste"
    },
    {
      "Type": "SolderMask",
      "Name": "Top Solder Mask"
    },
    {
      "Type": "Copper",
      "Name": "F.Cu"
    },
    {
      "Type": "Dielectric",
      "Material": "FR4",
      "Name": "F.Cu/B.Cu",
      "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)"
    },
    {
      "Type": "Copper",
      "Name": "B.Cu"
    },
    {
      "Type": "SolderMask",
      "Name": "Bottom Solder Mask"
    },
    {
      "Type": "SolderPaste",
      "Name": "Bottom Solder Paste"
    },
    {
      "Type": "Legend",
      "Name": "Bottom Silk Screen"
    }
  ]
 }
--- a/Hardware/Circuit/Gerber/Module.zip
+++ b/Hardware/Circuit/Gerber/Module.zip
--- a/Hardware/Circuit/Libraries/.gitkeep
+++ b/Hardware/Circuit/Libraries/.gitkeep
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-02BE.models/CUI_DEVICES_TB006-508-02BE.step
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-02BE.models/CUI_DEVICES_TB006-508-02BE.step
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-02BE.pretty/CUI_TB006-508-02BE.kicad_mod
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-02BE.pretty/CUI_TB006-508-02BE.kicad_mod
@ -0,0 +1,26 @@
 (module CUI_TB006-508-02BE (layer F.Cu) (tedit 611C079C)
  (descr "")
  (fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_text value CUI_TB006-508-02BE (at 12.462 5.461 0) (layer F.Fab)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 7.62 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 7.62 -4.1) (end 7.62 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 7.62 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 7.62 -4.1) (end 7.62 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 7.62 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 7.62 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.79 -4.35) (end 7.87 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 7.87 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 7.87 -4.35) (end 7.87 4.35) (layer F.CrtYd) (width 0.05))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
  (pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
 )
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-03BE.models/TB006-508-03BE.step
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-03BE.models/TB006-508-03BE.step
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.models/CUI_DEVICES_TB006-508-04BE.step
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.models/CUI_DEVICES_TB006-508-04BE.step
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-03BE.kicad_mod
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-03BE.kicad_mod
@ -0,0 +1,27 @@
 (module CUI_TB006-508-03BE (layer F.Cu) (tedit 6113F46A)
  (descr "")
  (fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_text value CUI_TB006-508-03BE (at 12.462 5.461 0) (layer F.Fab)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 12.7 -4.1) (end 12.7 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 12.7 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 12.7 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.79 -4.35) (end 12.95 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 12.95 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 12.95 -4.35) (end 12.95 4.35) (layer F.CrtYd) (width 0.05))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
  (pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 3 thru_hole circle (at 10.16 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
 )
--- a/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-04BE.kicad_mod
+++ b/Hardware/Circuit/Libraries/CUI_TB006-508-04BE.pretty/CUI_TB006-508-04BE.kicad_mod
@ -0,0 +1,28 @@
 (module CUI_TB006-508-04BE (layer F.Cu) (tedit 611C0388)
  (descr "")
  (fp_text reference REF** (at 0.905 -5.989 0) (layer F.SilkS)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_text value CUI_TB006-508-04BE (at 12.462 5.461 0) (layer F.Fab)
    (effects (font (size 1.4 1.4) (thickness 0.15)))
  )
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 17.78 -4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 17.78 -4.1) (end 17.78 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start 17.78 4.1) (end -2.54 4.1) (layer F.Fab) (width 0.127))
  (fp_line (start -2.54 4.1) (end -2.54 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 17.78 -4.1) (end 17.78 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.54 -4.1) (end 17.78 -4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start 17.78 4.1) (end -2.54 4.1) (layer F.SilkS) (width 0.127))
  (fp_line (start -2.79 -4.35) (end 18.03 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 18.03 4.35) (end -2.79 4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start -2.79 4.35) (end -2.79 -4.35) (layer F.CrtYd) (width 0.05))
  (fp_line (start 18.03 -4.35) (end 18.03 4.35) (layer F.CrtYd) (width 0.05))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.SilkS) (width 0.2))
  (fp_circle (center 0.0 -5.1) (end 0.1 -5.1) (layer F.Fab) (width 0.2))
  (pad 1 thru_hole rect (at 0.0 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 2 thru_hole circle (at 5.08 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 3 thru_hole circle (at 10.16 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
  (pad 4 thru_hole circle (at 15.24 0.0) (size 1.95 1.95) (drill 1.3) (layers *.Cu *.Mask))
 )
--- a/Hardware/Circuit/Libraries/TB006-508-03BE.lib
+++ b/Hardware/Circuit/Libraries/TB006-508-03BE.lib
@ -0,0 +1,23 @@
 EESchema-LIBRARY Version 2.3
 #encoding utf-8
 #(c) SnapEDA 2016 (snapeda.com)
 #This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
 #
 # TB006-508-03BE
 #
 DEF TB006-508-03BE J 0 40 Y Y 1 L N
 F0 "J" -220 200 50 H V L BNN
 F1 "TB006-508-03BE" -200 -300 50 H V L BNN
 F2 "CUI_TB006-508-03BE" 0 0 50 H I L BNN
 F3 "" 0 0 50 H I L BNN
 F4 "Manufacturer Recommendations" 0 0 50 H I L BNN "STANDARD"
 F5 "CUI" 0 0 50 H I L BNN "MANUFACTURER"
 DRAW
 S -200 -200 200 200 0 0 10 f
 X 1 1 -400 100 200 R 40 40 0 0 P 
 X 2 2 -400 0 200 R 40 40 0 0 P 
 X 3 3 -400 -100 200 R 40 40 0 0 P 
 ENDDRAW
 ENDDEF
 #
 # End Library
--- a/Hardware/Circuit/Libraries/logo/logo.kicad_mod
+++ b/Hardware/Circuit/Libraries/logo/logo.kicad_mod
@ -0,0 +1,64 @@
 (footprint "LOGO" (version 20210606) (generator bitmap2component) (layer "F.Cu")
  (at 0 0)
 (attr board_only exclude_from_pos_files exclude_from_bom)
 (fp_text reference "G***" (at 0 0) (layer F.SilkS)
  (effects (font (thickness 0.3)))
  )
  (fp_text value "LOGO" (at 0.75 0) (layer F.SilkS) hide
  (effects (font (thickness 0.3)))
  )
  (fp_poly (pts (xy 1.006804 -1.905763) (xy 1.031833 -1.905402) (xy 1.052015 -1.904769) (xy 1.067944 -1.903814) (xy 1.080213 -1.902487) (xy 1.089416 -1.900737) (xy 1.096146 -1.898515) (xy 1.100995 -1.895771)
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     (xy 0.607410 -1.898231) (xy 0.609983 -1.899621) (xy 0.613701 -1.900793) (xy 0.619170 -1.901771) (xy 0.626999 -1.902575) (xy 0.637794 -1.903230) (xy 0.652163 -1.903757) (xy 0.670713 -1.904178)
     (xy 0.694052 -1.904516) (xy 0.722787 -1.904794) (xy 0.757525 -1.905033) (xy 0.798875 -1.905257) (xy 0.846359 -1.905481) (xy 0.896706 -1.905711) (xy 0.939834 -1.905867) (xy 0.976336 -1.905901)
     )(layer F.SilkS) (width  0.000000)
  )
 )
--- a/Hardware/Circuit/Module-cache.lib
+++ b/Hardware/Circuit/Module-cache.lib
@ -0,0 +1,171 @@
 EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
 # Connector_Screw_Terminal_01x02
 #
 DEF Connector_Screw_Terminal_01x02 J 0 40 Y N 1 F N
 F0 "J" 0 100 50 H V C CNN
 F1 "Connector_Screw_Terminal_01x02" 0 -200 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
 TerminalBlock*:*
 $ENDFPLIST
 DRAW
 C 0 -100 25 1 1 6 N
 C 0 0 25 1 1 6 N
 S -50 50 50 -150 1 1 10 f
 P 2 1 1 6 -21 -87 13 -120 N
 P 2 1 1 6 -21 13 13 -20 N
 P 2 1 1 6 -14 -80 20 -113 N
 P 2 1 1 6 -14 20 20 -13 N
 X Pin_1 1 -200 0 150 R 50 50 1 1 P
 X Pin_2 2 -200 -100 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # Connector_Screw_Terminal_01x03
 #
 DEF Connector_Screw_Terminal_01x03 J 0 40 Y N 1 F N
 F0 "J" 0 200 50 H V C CNN
 F1 "Connector_Screw_Terminal_01x03" 0 -200 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
 TerminalBlock*:*
 $ENDFPLIST
 DRAW
 C 0 -100 25 1 1 6 N
 C 0 0 25 1 1 6 N
 C 0 100 25 1 1 6 N
 S -50 150 50 -150 1 1 10 f
 P 2 1 1 6 -21 -87 13 -120 N
 P 2 1 1 6 -21 13 13 -20 N
 P 2 1 1 6 -21 113 13 80 N
 P 2 1 1 6 -14 -80 20 -113 N
 P 2 1 1 6 -14 20 20 -13 N
 P 2 1 1 6 -14 120 20 87 N
 X Pin_1 1 -200 100 150 R 50 50 1 1 P
 X Pin_2 2 -200 0 150 R 50 50 1 1 P
 X Pin_3 3 -200 -100 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # Connector_Screw_Terminal_01x04
 #
 DEF Connector_Screw_Terminal_01x04 J 0 40 Y N 1 F N
 F0 "J" 0 200 50 H V C CNN
 F1 "Connector_Screw_Terminal_01x04" 0 -300 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
 TerminalBlock*:*
 $ENDFPLIST
 DRAW
 C 0 -200 25 1 1 6 N
 C 0 -100 25 1 1 6 N
 C 0 0 25 1 1 6 N
 C 0 100 25 1 1 6 N
 S -50 150 50 -250 1 1 10 f
 P 2 1 1 6 -21 -187 13 -220 N
 P 2 1 1 6 -21 -87 13 -120 N
 P 2 1 1 6 -21 13 13 -20 N
 P 2 1 1 6 -21 113 13 80 N
 P 2 1 1 6 -14 -180 20 -213 N
 P 2 1 1 6 -14 -80 20 -113 N
 P 2 1 1 6 -14 20 20 -13 N
 P 2 1 1 6 -14 120 20 87 N
 X Pin_1 1 -200 100 150 R 50 50 1 1 P
 X Pin_2 2 -200 0 150 R 50 50 1 1 P
 X Pin_3 3 -200 -100 150 R 50 50 1 1 P
 X Pin_4 4 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # Device_Q_NPN_BCE
 #
 DEF Device_Q_NPN_BCE Q 0 0 Y N 1 F N
 F0 "Q" 200 50 50 H V L CNN
 F1 "Device_Q_NPN_BCE" 200 -50 50 H V L CNN
 F2 "" 200 100 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 DRAW
 C 50 0 111 0 1 10 N
 P 2 0 1 0 25 25 100 100 N
 P 3 0 1 0 25 -25 100 -100 100 -100 N
 P 3 0 1 20 25 75 25 -75 25 -75 N
 P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
 X B 1 -200 0 225 R 50 50 1 1 I
 X C 2 100 200 100 D 50 50 1 1 P
 X E 3 100 -200 100 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # Device_R
 #
 DEF Device_R R 0 0 N Y 1 F N
 F0 "R" 80 0 50 V V C CNN
 F1 "Device_R" 0 0 50 V V C CNN
 F2 "" -70 0 50 V I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
 R_*
 $ENDFPLIST
 DRAW
 S -40 -100 40 100 0 1 10 N
 X ~ 1 0 150 50 D 50 50 1 1 P
 X ~ 2 0 -150 50 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # Jumper_SolderJumper_2_Open
 #
 DEF Jumper_SolderJumper_2_Open JP 0 0 Y N 1 F N
 F0 "JP" 0 80 50 H V C CNN
 F1 "Jumper_SolderJumper_2_Open" 0 -100 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
 SolderJumper*Open*
 $ENDFPLIST
 DRAW
 A -10 0 40 901 -901 0 1 0 N -10 40 -10 -40
 A -10 0 40 901 -901 0 1 0 F -10 40 -10 -40
 A 10 0 40 -899 899 0 1 0 N 10 -40 10 40
 A 10 0 40 -899 899 0 1 0 F 10 -40 10 40
 P 2 0 1 0 -10 40 -10 -40 N
 P 2 0 1 0 10 40 10 -40 N
 X A 1 -150 0 100 R 50 50 1 1 P
 X B 2 150 0 100 L 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
 # power_GND
 #
 DEF power_GND #PWR 0 0 Y Y 1 F P
 F0 "#PWR" 0 -250 50 H I C CNN
 F1 "power_GND" 0 -150 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 DRAW
 P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
 X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
 # power_VCC
 #
 DEF power_VCC #PWR 0 0 Y Y 1 F P
 F0 "#PWR" 0 -150 50 H I C CNN
 F1 "power_VCC" 0 150 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 DRAW
 P 2 0 1 0 -30 50 0 100 N
 P 2 0 1 0 0 0 0 100 N
 P 2 0 1 0 0 100 30 50 N
 X VCC 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
 #End Library
--- a/Hardware/Circuit/Module.kicad_pcb
+++ b/Hardware/Circuit/Module.kicad_pcb
--- a/Hardware/Circuit/Module.kicad_pro
+++ b/Hardware/Circuit/Module.kicad_pro
@ -0,0 +1,424 @@
 {
  "board": {
    "design_settings": {
      "defaults": {
        "board_outline_line_width": 0.049999999999999996,
        "copper_line_width": 0.19999999999999998,
        "copper_text_italic": false,
        "copper_text_size_h": 1.5,
        "copper_text_size_v": 1.5,
        "copper_text_thickness": 0.3,
        "copper_text_upright": false,
        "courtyard_line_width": 0.049999999999999996,
        "dimension_precision": 4,
        "dimension_units": 3,
        "dimensions": {
          "arrow_length": 1270000,
          "extension_offset": 500000,
          "keep_text_aligned": true,
          "suppress_zeroes": false,
          "text_position": 0,
          "units_format": 1
        },
        "fab_line_width": 0.09999999999999999,
        "fab_text_italic": false,
        "fab_text_size_h": 1.0,
        "fab_text_size_v": 1.0,
        "fab_text_thickness": 0.15,
        "fab_text_upright": false,
        "other_line_width": 0.09999999999999999,
        "other_text_italic": false,
        "other_text_size_h": 1.0,
        "other_text_size_v": 1.0,
        "other_text_thickness": 0.15,
        "other_text_upright": false,
        "pads": {
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          "height": 1.524,
          "width": 1.524
        },
        "silk_line_width": 0.12,
        "silk_text_italic": false,
        "silk_text_size_h": 1.0,
        "silk_text_size_v": 1.0,
        "silk_text_thickness": 0.15,
        "silk_text_upright": false,
        "zones": {
          "45_degree_only": false,
          "min_clearance": 0.508
        }
      },
      "diff_pair_dimensions": [],
      "drc_exclusions": [],
      "meta": {
        "filename": "board_design_settings.json",
        "version": 2
      },
      "rule_severities": {
        "annular_width": "error",
        "clearance": "error",
        "copper_edge_clearance": "error",
        "courtyards_overlap": "error",
        "diff_pair_gap_out_of_range": "error",
        "diff_pair_uncoupled_length_too_long": "error",
        "drill_out_of_range": "error",
        "duplicate_footprints": "warning",
        "extra_footprint": "warning",
        "footprint_type_mismatch": "error",
        "hole_clearance": "error",
        "hole_near_hole": "error",
        "invalid_outline": "error",
        "item_on_disabled_layer": "error",
        "items_not_allowed": "error",
        "length_out_of_range": "error",
        "malformed_courtyard": "error",
        "microvia_drill_out_of_range": "error",
        "missing_courtyard": "ignore",
        "missing_footprint": "warning",
        "net_conflict": "warning",
        "npth_inside_courtyard": "ignore",
        "padstack": "error",
        "pth_inside_courtyard": "ignore",
        "shorting_items": "error",
        "silk_over_copper": "warning",
        "silk_overlap": "warning",
        "skew_out_of_range": "error",
        "through_hole_pad_without_hole": "error",
        "too_many_vias": "error",
        "track_dangling": "warning",
        "track_width": "error",
        "tracks_crossing": "error",
        "unconnected_items": "error",
        "unresolved_variable": "error",
        "via_dangling": "warning",
        "zone_has_empty_net": "error",
        "zones_intersect": "error"
      },
      "rule_severitieslegacy_courtyards_overlap": true,
      "rule_severitieslegacy_no_courtyard_defined": false,
      "rules": {
        "allow_blind_buried_vias": false,
        "allow_microvias": false,
        "max_error": 0.005,
        "min_clearance": 0.0,
        "min_copper_edge_clearance": 0.024999999999999998,
        "min_hole_clearance": 0.25,
        "min_hole_to_hole": 0.25,
        "min_microvia_diameter": 0.19999999999999998,
        "min_microvia_drill": 0.09999999999999999,
        "min_silk_clearance": 0.0,
        "min_through_hole_diameter": 0.3,
        "min_track_width": 0.19999999999999998,
        "min_via_annular_width": 0.049999999999999996,
        "min_via_diameter": 0.39999999999999997,
        "use_height_for_length_calcs": true
      },
      "track_widths": [
        0.0,
        0.3
      ],
      "via_dimensions": [],
      "zones_allow_external_fillets": false,
      "zones_use_no_outline": true
    },
    "layer_presets": []
  },
  "boards": [],
  "cvpcb": {
    "equivalence_files": []
  },
  "erc": {
    "erc_exclusions": [],
    "meta": {
      "version": 0
    },
    "pin_map": [
      [
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        0,
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      ],
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        2,
        2,
        2,
        2
      ]
    ],
    "rule_severities": {
      "bus_definition_conflict": "error",
      "bus_entry_needed": "error",
      "bus_label_syntax": "error",
      "bus_to_bus_conflict": "error",
      "bus_to_net_conflict": "error",
      "different_unit_footprint": "error",
      "different_unit_net": "error",
      "duplicate_reference": "error",
      "duplicate_sheet_names": "error",
      "extra_units": "error",
      "global_label_dangling": "warning",
      "hier_label_mismatch": "error",
      "label_dangling": "error",
      "lib_symbol_issues": "warning",
      "multiple_net_names": "warning",
      "net_not_bus_member": "warning",
      "no_connect_connected": "warning",
      "no_connect_dangling": "warning",
      "pin_not_connected": "error",
      "pin_not_driven": "error",
      "pin_to_pin": "warning",
      "power_pin_not_driven": "error",
      "similar_labels": "warning",
      "unannotated": "error",
      "unit_value_mismatch": "error",
      "unresolved_variable": "error",
      "wire_dangling": "error"
    }
  },
  "libraries": {
    "pinned_footprint_libs": [],
    "pinned_symbol_libs": []
  },
  "meta": {
    "filename": "Module.kicad_pro",
    "version": 1
  },
  "net_settings": {
    "classes": [
      {
        "bus_width": 12.0,
        "clearance": 0.2,
        "diff_pair_gap": 0.25,
        "diff_pair_via_gap": 0.25,
        "diff_pair_width": 0.2,
        "line_style": 0,
        "microvia_diameter": 0.3,
        "microvia_drill": 0.1,
        "name": "Default",
        "pcb_color": "rgba(0, 0, 0, 0.000)",
        "schematic_color": "rgba(0, 0, 0, 0.000)",
        "track_width": 0.25,
        "via_diameter": 0.8,
        "via_drill": 0.4,
        "wire_width": 6.0
      }
    ],
    "meta": {
      "version": 2
    },
    "net_colors": null
  },
  "pcbnew": {
    "last_paths": {
      "gencad": "",
      "idf": "",
      "netlist": "Module.net",
      "specctra_dsn": "",
      "step": "",
      "vrml": ""
    },
    "page_layout_descr_file": ""
  },
  "schematic": {
    "annotate_start_num": 0,
    "drawing": {
      "default_line_thickness": 6.0,
      "default_text_size": 50.0,
      "field_names": [],
      "intersheets_ref_own_page": false,
      "intersheets_ref_prefix": "",
      "intersheets_ref_short": false,
      "intersheets_ref_show": false,
      "intersheets_ref_suffix": "",
      "junction_size_choice": 3,
      "label_size_ratio": 0.25,
      "pin_symbol_size": 0.0,
      "text_offset_ratio": 0.08
    },
    "legacy_lib_dir": "",
    "legacy_lib_list": [],
    "meta": {
      "version": 1
    },
    "net_format_name": "Pcbnew",
    "ngspice": {
      "fix_include_paths": true,
      "fix_passive_vals": false,
      "meta": {
        "version": 0
      },
      "model_mode": 0,
      "workbook_filename": ""
    },
    "page_layout_descr_file": "",
    "plot_directory": "",
    "spice_adjust_passive_values": false,
    "spice_external_command": "spice \"%I\"",
    "subpart_first_id": 65,
    "subpart_id_separator": 0
  },
  "sheets": [
    [
      "c201e1b2-fc01-4110-bdaa-a33290468c83",
      ""
    ]
  ],
  "text_variables": {}
 }
--- a/Hardware/Circuit/Module.kicad_sch
+++ b/Hardware/Circuit/Module.kicad_sch
--- a/Hardware/Circuit/Module.pro
+++ b/Hardware/Circuit/Module.pro
@ -0,0 +1,249 @@
 update=19.08.2021 14:20:23
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
 [cvpcb]
 version=1
 NetIExt=net
 [eeschema]
 version=1
 LibDir=
 [eeschema/libraries]
 [schematic_editor]
 version=1
 PageLayoutDescrFile=
 PlotDirectoryName=
 SubpartIdSeparator=0
 SubpartFirstId=65
 NetFmtName=Pcbnew
 SpiceAjustPassiveValues=0
 LabSize=50
 ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
 LastNetListRead=Module.net
 CopperLayerCount=2
 BoardThickness=1.6
 AllowMicroVias=0
 AllowBlindVias=0
 RequireCourtyardDefinitions=0
 ProhibitOverlappingCourtyards=1
 MinTrackWidth=0.2
 MinViaDiameter=0.4
 MinViaDrill=0.3
 MinMicroViaDiameter=0.2
 MinMicroViaDrill=0.09999999999999999
 MinHoleToHole=0.25
 TrackWidth1=0.25
 TrackWidth2=0.3
 ViaDiameter1=0.8
 ViaDrill1=0.4
 dPairWidth1=0.2
 dPairGap1=0.25
 dPairViaGap1=0.25
 SilkLineWidth=0.12
 SilkTextSizeV=1
 SilkTextSizeH=1
 SilkTextSizeThickness=0.15
 SilkTextItalic=0
 SilkTextUpright=1
 CopperLineWidth=0.2
 CopperTextSizeV=1.5
 CopperTextSizeH=1.5
 CopperTextThickness=0.3
 CopperTextItalic=0
 CopperTextUpright=1
 EdgeCutLineWidth=0.05
 CourtyardLineWidth=0.05
 OthersLineWidth=0.15
 OthersTextSizeV=1
 OthersTextSizeH=1
 OthersTextSizeThickness=0.15
 OthersTextItalic=0
 OthersTextUpright=1
 SolderMaskClearance=0
 SolderMaskMinWidth=0
 SolderPasteClearance=0
 SolderPasteRatio=-0
 [pcbnew/Layer.F.Cu]
 Name=F.Cu
 Type=0
 Enabled=1
 [pcbnew/Layer.In1.Cu]
 Name=In1.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In2.Cu]
 Name=In2.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In3.Cu]
 Name=In3.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In4.Cu]
 Name=In4.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In5.Cu]
 Name=In5.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In6.Cu]
 Name=In6.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In7.Cu]
 Name=In7.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In8.Cu]
 Name=In8.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In9.Cu]
 Name=In9.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In10.Cu]
 Name=In10.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In11.Cu]
 Name=In11.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In12.Cu]
 Name=In12.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In13.Cu]
 Name=In13.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In14.Cu]
 Name=In14.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In15.Cu]
 Name=In15.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In16.Cu]
 Name=In16.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In17.Cu]
 Name=In17.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In18.Cu]
 Name=In18.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In19.Cu]
 Name=In19.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In20.Cu]
 Name=In20.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In21.Cu]
 Name=In21.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In22.Cu]
 Name=In22.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In23.Cu]
 Name=In23.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In24.Cu]
 Name=In24.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In25.Cu]
 Name=In25.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In26.Cu]
 Name=In26.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In27.Cu]
 Name=In27.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In28.Cu]
 Name=In28.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In29.Cu]
 Name=In29.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.In30.Cu]
 Name=In30.Cu
 Type=0
 Enabled=0
 [pcbnew/Layer.B.Cu]
 Name=B.Cu
 Type=0
 Enabled=1
 [pcbnew/Layer.B.Adhes]
 Enabled=1
 [pcbnew/Layer.F.Adhes]
 Enabled=1
 [pcbnew/Layer.B.Paste]
 Enabled=1
 [pcbnew/Layer.F.Paste]
 Enabled=1
 [pcbnew/Layer.B.SilkS]
 Enabled=1
 [pcbnew/Layer.F.SilkS]
 Enabled=1
 [pcbnew/Layer.B.Mask]
 Enabled=1
 [pcbnew/Layer.F.Mask]
 Enabled=1
 [pcbnew/Layer.Dwgs.User]
 Enabled=1
 [pcbnew/Layer.Cmts.User]
 Enabled=1
 [pcbnew/Layer.Eco1.User]
 Enabled=1
 [pcbnew/Layer.Eco2.User]
 Enabled=1
 [pcbnew/Layer.Edge.Cuts]
 Enabled=1
 [pcbnew/Layer.Margin]
 Enabled=1
 [pcbnew/Layer.B.CrtYd]
 Enabled=1
 [pcbnew/Layer.F.CrtYd]
 Enabled=1
 [pcbnew/Layer.B.Fab]
 Enabled=1
 [pcbnew/Layer.F.Fab]
 Enabled=1
 [pcbnew/Layer.Rescue]
 Enabled=0
 [pcbnew/Netclasses]
 [pcbnew/Netclasses/Default]
 Name=Default
 Clearance=0.2
 TrackWidth=0.25
 ViaDiameter=0.8
 ViaDrill=0.4
 uViaDiameter=0.3
 uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
--- a/Hardware/Circuit/Module.sch
+++ b/Hardware/Circuit/Module.sch
@ -0,0 +1,304 @@
 EESchema Schematic File Version 4
 EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
 Sheet 1 1
 Title "LED Module"
 Date "2021-08-19"
 Rev "v01"
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 $EndComp
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 	3650 4650 3750 4650
 Wire Wire Line
 	4450 4350 4450 4450
 Wire Wire Line
 	5500 4650 5600 4650
 Wire Wire Line
 	6300 4350 6300 4450
 Wire Wire Line
 	3450 3200 3450 3300
 Wire Wire Line
 	3550 3200 3550 3300
 $Comp
 L Connector:Screw_Terminal_01x02 J3
 U 1 1 611DE627
 P 3450 3000
 F 0 "J3" H 3368 2675 50  0000 C CNN
 F 1 "Screw_Terminal_01x02" H 3368 2766 50  0000 C CNN
 F 2 "CUI_TB006-508-02BE:CUI_TB006-508-02BE" H 3450 3000 50  0001 C CNN
 F 3 "~" H 3450 3000 50  0001 C CNN
 	1    3450 3000
 	0    -1   -1   0   
 $EndComp
 $Comp
 L Jumper:SolderJumper_2_Open JP1
 U 1 1 611EF295
 P 4750 3650
 F 0 "JP1" H 4750 3550 50  0000 C CNN
 F 1 "Jumper" H 4750 3750 50  0000 C CNN
 F 2 "Jumper:SolderJumper-2_P1.3mm_Open_Pad1.0x1.5mm" H 4750 3650 50  0001 C CNN
 F 3 "~" H 4750 3650 50  0001 C CNN
 	1    4750 3650
 	-1   0    0    1   
 $EndComp
 $Comp
 L Jumper:SolderJumper_2_Open JP2
 U 1 1 611F131A
 P 5450 3650
 F 0 "JP2" H 5450 3750 50  0000 C CNN
 F 1 "Jumper" H 5450 3550 50  0000 C CNN
 F 2 "Jumper:SolderJumper-2_P1.3mm_Open_Pad1.0x1.5mm" H 5450 3650 50  0001 C CNN
 F 3 "~" H 5450 3650 50  0001 C CNN
 	1    5450 3650
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
 	4900 3650 5000 3650
 Connection ~ 5000 3650
 Wire Wire Line
 	5000 3650 5000 3750
 Wire Wire Line
 	5200 3650 5300 3650
 Connection ~ 5200 3650
 Wire Wire Line
 	5200 3650 5200 3750
 $Comp
 L Device:R R3
 U 1 1 611F381A
 P 4350 3650
 F 0 "R3" V 4143 3650 50  0000 C CNN
 F 1 "10k" V 4234 3650 50  0000 C CNN
 F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder" V 4280 3650 50  0001 C CNN
 F 3 "~" H 4350 3650 50  0001 C CNN
 	1    4350 3650
 	0    1    1    0   
 $EndComp
 $Comp
 L Device:R R4
 U 1 1 611F53B7
 P 5850 3650
 F 0 "R4" V 5643 3650 50  0000 C CNN
 F 1 "10k" V 5734 3650 50  0000 C CNN
 F 2 "Resistor_SMD:R_0805_2012Metric_Pad1.20x1.40mm_HandSolder" V 5780 3650 50  0001 C CNN
 F 3 "~" H 5850 3650 50  0001 C CNN
 	1    5850 3650
 	0    1    1    0   
 $EndComp
 Wire Wire Line
 	4500 3650 4600 3650
 Wire Wire Line
 	5600 3650 5700 3650
 $Comp
 L power:GND #PWR0108
 U 1 1 611F6AFB
 P 4100 3650
 F 0 "#PWR0108" H 4100 3400 50  0001 C CNN
 F 1 "GND" V 4105 3522 50  0000 R CNN
 F 2 "" H 4100 3650 50  0001 C CNN
 F 3 "" H 4100 3650 50  0001 C CNN
 	1    4100 3650
 	1    0    0    -1  
 $EndComp
 $Comp
 L power:GND #PWR0109
 U 1 1 611F7BD4
 P 6100 3650
 F 0 "#PWR0109" H 6100 3400 50  0001 C CNN
 F 1 "GND" V 6105 3522 50  0000 R CNN
 F 2 "" H 6100 3650 50  0001 C CNN
 F 3 "" H 6100 3650 50  0001 C CNN
 	1    6100 3650
 	1    0    0    -1  
 $EndComp
 Wire Wire Line
 	6000 3650 6100 3650
 Wire Wire Line
 	4100 3650 4200 3650
 $EndSCHEMATC
--- a/Hardware/Circuit/bom/ibom.html
+++ b/Hardware/Circuit/bom/ibom.html
--- a/Hardware/Circuit/fp-lib-table
+++ b/Hardware/Circuit/fp-lib-table
@ -0,0 +1,6 @@
 (fp_lib_table
  (lib (name "CUI_TB006-508-03BE")(type "KiCad")(uri "${KIPRJMOD}/Libraries/CUI_TB006-508-03BE.pretty")(options "")(descr ""))
  (lib (name "CUI_TB006-508-04BE")(type "KiCad")(uri "${KIPRJMOD}/Libraries/CUI_TB006-508-04BE.pretty")(options "")(descr ""))
  (lib (name "CUI_TB006-508-02BE")(type "KiCad")(uri "${KIPRJMOD}/Libraries/CUI_TB006-508-02BE.pretty")(options "")(descr ""))
  (lib (name "Logo")(type "KiCad")(uri "${KIPRJMOD}/Libraries/logo")(options "")(descr ""))
 )
--- a/Hardware/Enclosure/.gitkeep
+++ b/Hardware/Enclosure/.gitkeep
--- a/Hardware/Enclosure/Back
+++ b/Hardware/Enclosure/Back
--- a/Hardware/Enclosure/Front
+++ b/Hardware/Enclosure/Front